rp2040_pac/xip_ctrl/
flush.rs

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1#[doc = "Register `FLUSH` reader"]
2pub type R = crate::R<FLUSH_SPEC>;
3#[doc = "Register `FLUSH` writer"]
4pub type W = crate::W<FLUSH_SPEC>;
5#[doc = "Field `FLUSH` reader - Write 1 to flush the cache. This clears the tag memory, but  
6 the data memory retains its contents. (This means cache-as-SRAM  
7 contents is not affected by flush or reset.)  
8 Reading will hold the bus (stall the processor) until the flush  
9 completes. Alternatively STAT can be polled until completion."]
10pub type FLUSH_R = crate::BitReader;
11#[doc = "Field `FLUSH` writer - Write 1 to flush the cache. This clears the tag memory, but  
12 the data memory retains its contents. (This means cache-as-SRAM  
13 contents is not affected by flush or reset.)  
14 Reading will hold the bus (stall the processor) until the flush  
15 completes. Alternatively STAT can be polled until completion."]
16pub type FLUSH_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but  
19 the data memory retains its contents. (This means cache-as-SRAM  
20 contents is not affected by flush or reset.)  
21 Reading will hold the bus (stall the processor) until the flush  
22 completes. Alternatively STAT can be polled until completion."]
23    #[inline(always)]
24    pub fn flush(&self) -> FLUSH_R {
25        FLUSH_R::new((self.bits & 1) != 0)
26    }
27}
28impl W {
29    #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but  
30 the data memory retains its contents. (This means cache-as-SRAM  
31 contents is not affected by flush or reset.)  
32 Reading will hold the bus (stall the processor) until the flush  
33 completes. Alternatively STAT can be polled until completion."]
34    #[inline(always)]
35    #[must_use]
36    pub fn flush(&mut self) -> FLUSH_W<FLUSH_SPEC> {
37        FLUSH_W::new(self, 0)
38    }
39    #[doc = r" Writes raw bits to the register."]
40    #[doc = r""]
41    #[doc = r" # Safety"]
42    #[doc = r""]
43    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
44    #[inline(always)]
45    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
46        self.bits = bits;
47        self
48    }
49}
50#[doc = "Cache Flush control  
51
52You can [`read`](crate::generic::Reg::read) this register and get [`flush::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flush::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
53pub struct FLUSH_SPEC;
54impl crate::RegisterSpec for FLUSH_SPEC {
55    type Ux = u32;
56}
57#[doc = "`read()` method returns [`flush::R`](R) reader structure"]
58impl crate::Readable for FLUSH_SPEC {}
59#[doc = "`write(|w| ..)` method takes [`flush::W`](W) writer structure"]
60impl crate::Writable for FLUSH_SPEC {
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63}
64#[doc = "`reset()` method sets FLUSH to value 0"]
65impl crate::Resettable for FLUSH_SPEC {
66    const RESET_VALUE: u32 = 0;
67}
rp2040_pac/xip_ctrl/flush.rs

rp2040_pac/xip_ctrl/
flush.rs
