rp2040_pac/usbctrl_dpram/
epx_control.rs

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1#[doc = "Register `EPX_CONTROL` reader"]
2pub type R = crate::R<EPX_CONTROL_SPEC>;
3#[doc = "Register `EPX_CONTROL` writer"]
4pub type W = crate::W<EPX_CONTROL_SPEC>;
5#[doc = "Field `BUFFER_ADDRESS` reader - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
6pub type BUFFER_ADDRESS_R = crate::FieldReader<u16>;
7#[doc = "Field `BUFFER_ADDRESS` writer - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
8pub type BUFFER_ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `INTERRUPT_ON_NAK` reader - Trigger an interrupt if a NAK is sent. Intended for debug only."]
10pub type INTERRUPT_ON_NAK_R = crate::BitReader;
11#[doc = "Field `INTERRUPT_ON_NAK` writer - Trigger an interrupt if a NAK is sent. Intended for debug only."]
12pub type INTERRUPT_ON_NAK_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `INTERRUPT_ON_STALL` reader - Trigger an interrupt if a STALL is sent. Intended for debug only."]
14pub type INTERRUPT_ON_STALL_R = crate::BitReader;
15#[doc = "Field `INTERRUPT_ON_STALL` writer - Trigger an interrupt if a STALL is sent. Intended for debug only."]
16pub type INTERRUPT_ON_STALL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ENDPOINT_TYPE` reader - "]
18pub type ENDPOINT_TYPE_R = crate::FieldReader<ENDPOINT_TYPE_A>;
19#[doc = "  
20
21Value on reset: 0"]
22#[derive(Clone, Copy, Debug, PartialEq, Eq)]
23#[repr(u8)]
24pub enum ENDPOINT_TYPE_A {
25    #[doc = "0: `0`"]
26    CONTROL = 0,
27    #[doc = "1: `1`"]
28    ISOCHRONOUS = 1,
29    #[doc = "2: `10`"]
30    BULK = 2,
31    #[doc = "3: `11`"]
32    INTERRUPT = 3,
33}
34impl From<ENDPOINT_TYPE_A> for u8 {
35    #[inline(always)]
36    fn from(variant: ENDPOINT_TYPE_A) -> Self {
37        variant as _
38    }
39}
40impl crate::FieldSpec for ENDPOINT_TYPE_A {
41    type Ux = u8;
42}
43impl ENDPOINT_TYPE_R {
44    #[doc = "Get enumerated values variant"]
45    #[inline(always)]
46    pub const fn variant(&self) -> ENDPOINT_TYPE_A {
47        match self.bits {
48            0 => ENDPOINT_TYPE_A::CONTROL,
49            1 => ENDPOINT_TYPE_A::ISOCHRONOUS,
50            2 => ENDPOINT_TYPE_A::BULK,
51            3 => ENDPOINT_TYPE_A::INTERRUPT,
52            _ => unreachable!(),
53        }
54    }
55    #[doc = "`0`"]
56    #[inline(always)]
57    pub fn is_control(&self) -> bool {
58        *self == ENDPOINT_TYPE_A::CONTROL
59    }
60    #[doc = "`1`"]
61    #[inline(always)]
62    pub fn is_isochronous(&self) -> bool {
63        *self == ENDPOINT_TYPE_A::ISOCHRONOUS
64    }
65    #[doc = "`10`"]
66    #[inline(always)]
67    pub fn is_bulk(&self) -> bool {
68        *self == ENDPOINT_TYPE_A::BULK
69    }
70    #[doc = "`11`"]
71    #[inline(always)]
72    pub fn is_interrupt(&self) -> bool {
73        *self == ENDPOINT_TYPE_A::INTERRUPT
74    }
75}
76#[doc = "Field `ENDPOINT_TYPE` writer - "]
77pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ENDPOINT_TYPE_A>;
78impl<'a, REG> ENDPOINT_TYPE_W<'a, REG>
79where
80    REG: crate::Writable + crate::RegisterSpec,
81    REG::Ux: From<u8>,
82{
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn control(self) -> &'a mut crate::W<REG> {
86        self.variant(ENDPOINT_TYPE_A::CONTROL)
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn isochronous(self) -> &'a mut crate::W<REG> {
91        self.variant(ENDPOINT_TYPE_A::ISOCHRONOUS)
92    }
93    #[doc = "`10`"]
94    #[inline(always)]
95    pub fn bulk(self) -> &'a mut crate::W<REG> {
96        self.variant(ENDPOINT_TYPE_A::BULK)
97    }
98    #[doc = "`11`"]
99    #[inline(always)]
100    pub fn interrupt(self) -> &'a mut crate::W<REG> {
101        self.variant(ENDPOINT_TYPE_A::INTERRUPT)
102    }
103}
104#[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` reader - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
105pub type INTERRUPT_PER_DOUBLE_BUFF_R = crate::BitReader;
106#[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` writer - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
107pub type INTERRUPT_PER_DOUBLE_BUFF_W<'a, REG> = crate::BitWriter<'a, REG>;
108#[doc = "Field `INTERRUPT_PER_BUFF` reader - Trigger an interrupt each time a buffer is done."]
109pub type INTERRUPT_PER_BUFF_R = crate::BitReader;
110#[doc = "Field `INTERRUPT_PER_BUFF` writer - Trigger an interrupt each time a buffer is done."]
111pub type INTERRUPT_PER_BUFF_W<'a, REG> = crate::BitWriter<'a, REG>;
112#[doc = "Field `DOUBLE_BUFFERED` reader - This endpoint is double buffered."]
113pub type DOUBLE_BUFFERED_R = crate::BitReader;
114#[doc = "Field `DOUBLE_BUFFERED` writer - This endpoint is double buffered."]
115pub type DOUBLE_BUFFERED_W<'a, REG> = crate::BitWriter<'a, REG>;
116#[doc = "Field `ENABLE` reader - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
117pub type ENABLE_R = crate::BitReader;
118#[doc = "Field `ENABLE` writer - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
119pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
120impl R {
121    #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
122    #[inline(always)]
123    pub fn buffer_address(&self) -> BUFFER_ADDRESS_R {
124        BUFFER_ADDRESS_R::new((self.bits & 0xffff) as u16)
125    }
126    #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."]
127    #[inline(always)]
128    pub fn interrupt_on_nak(&self) -> INTERRUPT_ON_NAK_R {
129        INTERRUPT_ON_NAK_R::new(((self.bits >> 16) & 1) != 0)
130    }
131    #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."]
132    #[inline(always)]
133    pub fn interrupt_on_stall(&self) -> INTERRUPT_ON_STALL_R {
134        INTERRUPT_ON_STALL_R::new(((self.bits >> 17) & 1) != 0)
135    }
136    #[doc = "Bits 26:27"]
137    #[inline(always)]
138    pub fn endpoint_type(&self) -> ENDPOINT_TYPE_R {
139        ENDPOINT_TYPE_R::new(((self.bits >> 26) & 3) as u8)
140    }
141    #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
142    #[inline(always)]
143    pub fn interrupt_per_double_buff(&self) -> INTERRUPT_PER_DOUBLE_BUFF_R {
144        INTERRUPT_PER_DOUBLE_BUFF_R::new(((self.bits >> 28) & 1) != 0)
145    }
146    #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."]
147    #[inline(always)]
148    pub fn interrupt_per_buff(&self) -> INTERRUPT_PER_BUFF_R {
149        INTERRUPT_PER_BUFF_R::new(((self.bits >> 29) & 1) != 0)
150    }
151    #[doc = "Bit 30 - This endpoint is double buffered."]
152    #[inline(always)]
153    pub fn double_buffered(&self) -> DOUBLE_BUFFERED_R {
154        DOUBLE_BUFFERED_R::new(((self.bits >> 30) & 1) != 0)
155    }
156    #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
157    #[inline(always)]
158    pub fn enable(&self) -> ENABLE_R {
159        ENABLE_R::new(((self.bits >> 31) & 1) != 0)
160    }
161}
162impl W {
163    #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
164    #[inline(always)]
165    #[must_use]
166    pub fn buffer_address(&mut self) -> BUFFER_ADDRESS_W<EPX_CONTROL_SPEC> {
167        BUFFER_ADDRESS_W::new(self, 0)
168    }
169    #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."]
170    #[inline(always)]
171    #[must_use]
172    pub fn interrupt_on_nak(&mut self) -> INTERRUPT_ON_NAK_W<EPX_CONTROL_SPEC> {
173        INTERRUPT_ON_NAK_W::new(self, 16)
174    }
175    #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."]
176    #[inline(always)]
177    #[must_use]
178    pub fn interrupt_on_stall(&mut self) -> INTERRUPT_ON_STALL_W<EPX_CONTROL_SPEC> {
179        INTERRUPT_ON_STALL_W::new(self, 17)
180    }
181    #[doc = "Bits 26:27"]
182    #[inline(always)]
183    #[must_use]
184    pub fn endpoint_type(&mut self) -> ENDPOINT_TYPE_W<EPX_CONTROL_SPEC> {
185        ENDPOINT_TYPE_W::new(self, 26)
186    }
187    #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
188    #[inline(always)]
189    #[must_use]
190    pub fn interrupt_per_double_buff(&mut self) -> INTERRUPT_PER_DOUBLE_BUFF_W<EPX_CONTROL_SPEC> {
191        INTERRUPT_PER_DOUBLE_BUFF_W::new(self, 28)
192    }
193    #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."]
194    #[inline(always)]
195    #[must_use]
196    pub fn interrupt_per_buff(&mut self) -> INTERRUPT_PER_BUFF_W<EPX_CONTROL_SPEC> {
197        INTERRUPT_PER_BUFF_W::new(self, 29)
198    }
199    #[doc = "Bit 30 - This endpoint is double buffered."]
200    #[inline(always)]
201    #[must_use]
202    pub fn double_buffered(&mut self) -> DOUBLE_BUFFERED_W<EPX_CONTROL_SPEC> {
203        DOUBLE_BUFFERED_W::new(self, 30)
204    }
205    #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
206    #[inline(always)]
207    #[must_use]
208    pub fn enable(&mut self) -> ENABLE_W<EPX_CONTROL_SPEC> {
209        ENABLE_W::new(self, 31)
210    }
211    #[doc = r" Writes raw bits to the register."]
212    #[doc = r""]
213    #[doc = r" # Safety"]
214    #[doc = r""]
215    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
216    #[inline(always)]
217    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
218        self.bits = bits;
219        self
220    }
221}
222#[doc = "EPx Control (Host-mode only!)  
223
224You can [`read`](crate::generic::Reg::read) this register and get [`epx_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`epx_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
225pub struct EPX_CONTROL_SPEC;
226impl crate::RegisterSpec for EPX_CONTROL_SPEC {
227    type Ux = u32;
228}
229#[doc = "`read()` method returns [`epx_control::R`](R) reader structure"]
230impl crate::Readable for EPX_CONTROL_SPEC {}
231#[doc = "`write(|w| ..)` method takes [`epx_control::W`](W) writer structure"]
232impl crate::Writable for EPX_CONTROL_SPEC {
233    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
234    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
235}
236#[doc = "`reset()` method sets EPX_CONTROL to value 0"]
237impl crate::Resettable for EPX_CONTROL_SPEC {
238    const RESET_VALUE: u32 = 0;
239}
rp2040_pac/usbctrl_dpram/epx_control.rs

rp2040_pac/usbctrl_dpram/
epx_control.rs
