portable_atomic/imp/fallback/
utils.rs

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1// SPDX-License-Identifier: Apache-2.0 OR MIT
2
3use core::ops;
4
5// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.21/crossbeam-utils/src/cache_padded.rs.
6/// Pads and aligns a value to the length of a cache line.
7// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache
8// lines at a time, so we have to align to 128 bytes rather than 64.
9//
10// Sources:
11// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
12// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
13//
14// aarch64/arm64ec's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
15//
16// Sources:
17// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
18//
19// powerpc64 has 128-byte cache line size.
20//
21// Sources:
22// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
23// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/powerpc/include/asm/cache.h#L26
24#[cfg_attr(
25    any(
26        target_arch = "x86_64",
27        target_arch = "aarch64",
28        target_arch = "arm64ec",
29        target_arch = "powerpc64",
30    ),
31    repr(align(128))
32)]
33// arm, mips, mips64, sparc, and hexagon have 32-byte cache line size.
34//
35// Sources:
36// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
37// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
38// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
39// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
40// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L17
41// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/hexagon/include/asm/cache.h#L12
42#[cfg_attr(
43    any(
44        target_arch = "arm",
45        target_arch = "mips",
46        target_arch = "mips32r6",
47        target_arch = "mips64",
48        target_arch = "mips64r6",
49        target_arch = "sparc",
50        target_arch = "hexagon",
51    ),
52    repr(align(32))
53)]
54// m68k has 16-byte cache line size.
55//
56// Sources:
57// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/m68k/include/asm/cache.h#L9
58#[cfg_attr(target_arch = "m68k", repr(align(16)))]
59// s390x has 256-byte cache line size.
60//
61// Sources:
62// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
63// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/s390/include/asm/cache.h#L13
64#[cfg_attr(target_arch = "s390x", repr(align(256)))]
65// x86, wasm, riscv, and sparc64 have 64-byte cache line size.
66//
67// Sources:
68// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
69// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
70// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/riscv/include/asm/cache.h#L10
71// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L19
72//
73// All others are assumed to have 64-byte cache line size.
74#[cfg_attr(
75    not(any(
76        target_arch = "x86_64",
77        target_arch = "aarch64",
78        target_arch = "arm64ec",
79        target_arch = "powerpc64",
80        target_arch = "arm",
81        target_arch = "mips",
82        target_arch = "mips32r6",
83        target_arch = "mips64",
84        target_arch = "mips64r6",
85        target_arch = "sparc",
86        target_arch = "hexagon",
87        target_arch = "m68k",
88        target_arch = "s390x",
89    )),
90    repr(align(64))
91)]
92pub(crate) struct CachePadded<T> {
93    value: T,
94}
95
96impl<T> CachePadded<T> {
97    #[inline]
98    pub(crate) const fn new(value: T) -> Self {
99        Self { value }
100    }
101}
102
103impl<T> ops::Deref for CachePadded<T> {
104    type Target = T;
105
106    #[inline]
107    fn deref(&self) -> &Self::Target {
108        &self.value
109    }
110}
111
112// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.7/crossbeam-utils/src/backoff.rs.
113// Adjusted to reduce spinning.
114/// Performs exponential backoff in spin loops.
115pub(crate) struct Backoff {
116    step: u32,
117}
118
119// https://github.com/oneapi-src/oneTBB/blob/v2021.5.0/include/oneapi/tbb/detail/_utils.h#L46-L48
120const SPIN_LIMIT: u32 = 4;
121
122impl Backoff {
123    #[inline]
124    pub(crate) const fn new() -> Self {
125        Self { step: 0 }
126    }
127
128    #[inline]
129    pub(crate) fn snooze(&mut self) {
130        if self.step <= SPIN_LIMIT {
131            for _ in 0..1 << self.step {
132                #[allow(deprecated)]
133                core::sync::atomic::spin_loop_hint();
134            }
135            self.step += 1;
136        } else {
137            #[cfg(not(feature = "std"))]
138            for _ in 0..1 << self.step {
139                #[allow(deprecated)]
140                core::sync::atomic::spin_loop_hint();
141            }
142
143            #[cfg(feature = "std")]
144            std::thread::yield_now();
145        }
146    }
147}
portable_atomic/imp/fallback/utils.rs

portable_atomic/imp/fallback/
utils.rs
