rp2040_pac/
syscfg.rs

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1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    proc0_nmi_mask: PROC0_NMI_MASK,
5    proc1_nmi_mask: PROC1_NMI_MASK,
6    proc_config: PROC_CONFIG,
7    proc_in_sync_bypass: PROC_IN_SYNC_BYPASS,
8    proc_in_sync_bypass_hi: PROC_IN_SYNC_BYPASS_HI,
9    dbgforce: DBGFORCE,
10    mempowerdown: MEMPOWERDOWN,
11}
12impl RegisterBlock {
13    #[doc = "0x00 - Processor core 0 NMI source mask  
14 Set a bit high to enable NMI from that IRQ"]
15    #[inline(always)]
16    pub const fn proc0_nmi_mask(&self) -> &PROC0_NMI_MASK {
17        &self.proc0_nmi_mask
18    }
19    #[doc = "0x04 - Processor core 1 NMI source mask  
20 Set a bit high to enable NMI from that IRQ"]
21    #[inline(always)]
22    pub const fn proc1_nmi_mask(&self) -> &PROC1_NMI_MASK {
23        &self.proc1_nmi_mask
24    }
25    #[doc = "0x08 - Configuration for processors"]
26    #[inline(always)]
27    pub const fn proc_config(&self) -> &PROC_CONFIG {
28        &self.proc_config
29    }
30    #[doc = "0x0c - For each bit, if 1, bypass the input synchronizer between that GPIO  
31 and the GPIO input register in the SIO. The input synchronizers should  
32 generally be unbypassed, to avoid injecting metastabilities into processors.  
33 If you're feeling brave, you can bypass to save two cycles of input  
34 latency. This register applies to GPIO 0...29."]
35    #[inline(always)]
36    pub const fn proc_in_sync_bypass(&self) -> &PROC_IN_SYNC_BYPASS {
37        &self.proc_in_sync_bypass
38    }
39    #[doc = "0x10 - For each bit, if 1, bypass the input synchronizer between that GPIO  
40 and the GPIO input register in the SIO. The input synchronizers should  
41 generally be unbypassed, to avoid injecting metastabilities into processors.  
42 If you're feeling brave, you can bypass to save two cycles of input  
43 latency. This register applies to GPIO 30...35 (the QSPI IOs)."]
44    #[inline(always)]
45    pub const fn proc_in_sync_bypass_hi(&self) -> &PROC_IN_SYNC_BYPASS_HI {
46        &self.proc_in_sync_bypass_hi
47    }
48    #[doc = "0x14 - Directly control the SWD debug port of either processor"]
49    #[inline(always)]
50    pub const fn dbgforce(&self) -> &DBGFORCE {
51        &self.dbgforce
52    }
53    #[doc = "0x18 - Control power downs to memories. Set high to power down memories.  
54 Use with extreme caution"]
55    #[inline(always)]
56    pub const fn mempowerdown(&self) -> &MEMPOWERDOWN {
57        &self.mempowerdown
58    }
59}
60#[doc = "PROC0_NMI_MASK (rw) register accessor: Processor core 0 NMI source mask  
61 Set a bit high to enable NMI from that IRQ  
62
63You can [`read`](crate::generic::Reg::read) this register and get [`proc0_nmi_mask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
64
65For information about available fields see [`mod@proc0_nmi_mask`]
66module"]
67pub type PROC0_NMI_MASK = crate::Reg<proc0_nmi_mask::PROC0_NMI_MASK_SPEC>;
68#[doc = "Processor core 0 NMI source mask  
69 Set a bit high to enable NMI from that IRQ"]
70pub mod proc0_nmi_mask;
71#[doc = "PROC1_NMI_MASK (rw) register accessor: Processor core 1 NMI source mask  
72 Set a bit high to enable NMI from that IRQ  
73
74You can [`read`](crate::generic::Reg::read) this register and get [`proc1_nmi_mask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
75
76For information about available fields see [`mod@proc1_nmi_mask`]
77module"]
78pub type PROC1_NMI_MASK = crate::Reg<proc1_nmi_mask::PROC1_NMI_MASK_SPEC>;
79#[doc = "Processor core 1 NMI source mask  
80 Set a bit high to enable NMI from that IRQ"]
81pub mod proc1_nmi_mask;
82#[doc = "PROC_CONFIG (rw) register accessor: Configuration for processors  
83
84You can [`read`](crate::generic::Reg::read) this register and get [`proc_config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
85
86For information about available fields see [`mod@proc_config`]
87module"]
88pub type PROC_CONFIG = crate::Reg<proc_config::PROC_CONFIG_SPEC>;
89#[doc = "Configuration for processors"]
90pub mod proc_config;
91#[doc = "PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO  
92 and the GPIO input register in the SIO. The input synchronizers should  
93 generally be unbypassed, to avoid injecting metastabilities into processors.  
94 If you're feeling brave, you can bypass to save two cycles of input  
95 latency. This register applies to GPIO 0...29.  
96
97You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
98
99For information about available fields see [`mod@proc_in_sync_bypass`]
100module"]
101pub type PROC_IN_SYNC_BYPASS = crate::Reg<proc_in_sync_bypass::PROC_IN_SYNC_BYPASS_SPEC>;
102#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO  
103 and the GPIO input register in the SIO. The input synchronizers should  
104 generally be unbypassed, to avoid injecting metastabilities into processors.  
105 If you're feeling brave, you can bypass to save two cycles of input  
106 latency. This register applies to GPIO 0...29."]
107pub mod proc_in_sync_bypass;
108#[doc = "PROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO  
109 and the GPIO input register in the SIO. The input synchronizers should  
110 generally be unbypassed, to avoid injecting metastabilities into processors.  
111 If you're feeling brave, you can bypass to save two cycles of input  
112 latency. This register applies to GPIO 30...35 (the QSPI IOs).  
113
114You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
115
116For information about available fields see [`mod@proc_in_sync_bypass_hi`]
117module"]
118pub type PROC_IN_SYNC_BYPASS_HI = crate::Reg<proc_in_sync_bypass_hi::PROC_IN_SYNC_BYPASS_HI_SPEC>;
119#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO  
120 and the GPIO input register in the SIO. The input synchronizers should  
121 generally be unbypassed, to avoid injecting metastabilities into processors.  
122 If you're feeling brave, you can bypass to save two cycles of input  
123 latency. This register applies to GPIO 30...35 (the QSPI IOs)."]
124pub mod proc_in_sync_bypass_hi;
125#[doc = "DBGFORCE (rw) register accessor: Directly control the SWD debug port of either processor  
126
127You can [`read`](crate::generic::Reg::read) this register and get [`dbgforce::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgforce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
128
129For information about available fields see [`mod@dbgforce`]
130module"]
131pub type DBGFORCE = crate::Reg<dbgforce::DBGFORCE_SPEC>;
132#[doc = "Directly control the SWD debug port of either processor"]
133pub mod dbgforce;
134#[doc = "MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories.  
135 Use with extreme caution  
136
137You can [`read`](crate::generic::Reg::read) this register and get [`mempowerdown::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mempowerdown::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
138
139For information about available fields see [`mod@mempowerdown`]
140module"]
141pub type MEMPOWERDOWN = crate::Reg<mempowerdown::MEMPOWERDOWN_SPEC>;
142#[doc = "Control power downs to memories. Set high to power down memories.  
143 Use with extreme caution"]
144pub mod mempowerdown;
rp2040_pac/syscfg.rs

rp2040_pac/
syscfg.rs
