nrf52840_pac/spim0/iftiming/
rxdelay.rs

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1#[doc = "Register `RXDELAY` reader"]
2pub struct R(crate::R<RXDELAY_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RXDELAY_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RXDELAY_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RXDELAY_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RXDELAY` writer"]
17pub struct W(crate::W<RXDELAY_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RXDELAY_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RXDELAY_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RXDELAY_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RXDELAY` reader - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK."]
38pub type RXDELAY_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `RXDELAY` writer - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK."]
40pub type RXDELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXDELAY_SPEC, u8, u8, 3, O>;
41impl R {
42    #[doc = "Bits 0:2 - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK."]
43    #[inline(always)]
44    pub fn rxdelay(&self) -> RXDELAY_R {
45        RXDELAY_R::new((self.bits & 7) as u8)
46    }
47}
48impl W {
49    #[doc = "Bits 0:2 - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK."]
50    #[inline(always)]
51    pub fn rxdelay(&mut self) -> RXDELAY_W<0> {
52        RXDELAY_W::new(self)
53    }
54    #[doc = "Writes raw bits to the register."]
55    #[inline(always)]
56    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
57        self.0.bits(bits);
58        self
59    }
60}
61#[doc = "Sample delay for input serial data on MISO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxdelay](index.html) module"]
62pub struct RXDELAY_SPEC;
63impl crate::RegisterSpec for RXDELAY_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [rxdelay::R](R) reader structure"]
67impl crate::Readable for RXDELAY_SPEC {
68    type Reader = R;
69}
70#[doc = "`write(|w| ..)` method takes [rxdelay::W](W) writer structure"]
71impl crate::Writable for RXDELAY_SPEC {
72    type Writer = W;
73}
74#[doc = "`reset()` method sets RXDELAY to value 0x02"]
75impl crate::Resettable for RXDELAY_SPEC {
76    #[inline(always)]
77    fn reset_value() -> Self::Ux {
78        0x02
79    }
80}
nrf52840_pac/spim0/iftiming/rxdelay.rs

nrf52840_pac/spim0/iftiming/
rxdelay.rs
