rp2040_pac/pio0/
irq_force.rs

Help
1#[doc = "Register `IRQ_FORCE` writer"]
2pub type W = crate::W<IRQ_FORCE_SPEC>;
3#[doc = "Field `IRQ_FORCE` writer - "]
4pub type IRQ_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
5impl W {
6    #[doc = "Bits 0:7"]
7    #[inline(always)]
8    #[must_use]
9    pub fn irq_force(&mut self) -> IRQ_FORCE_W<IRQ_FORCE_SPEC> {
10        IRQ_FORCE_W::new(self, 0)
11    }
12    #[doc = r" Writes raw bits to the register."]
13    #[doc = r""]
14    #[doc = r" # Safety"]
15    #[doc = r""]
16    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
17    #[inline(always)]
18    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
19        self.bits = bits;
20        self
21    }
22}
23#[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.  
24
25You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26pub struct IRQ_FORCE_SPEC;
27impl crate::RegisterSpec for IRQ_FORCE_SPEC {
28    type Ux = u32;
29}
30#[doc = "`write(|w| ..)` method takes [`irq_force::W`](W) writer structure"]
31impl crate::Writable for IRQ_FORCE_SPEC {
32    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
33    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
34}
35#[doc = "`reset()` method sets IRQ_FORCE to value 0"]
36impl crate::Resettable for IRQ_FORCE_SPEC {
37    const RESET_VALUE: u32 = 0;
38}
rp2040_pac/pio0/irq_force.rs

rp2040_pac/pio0/
irq_force.rs
