imxrt_ral/blocks/imxrt1011/
rtwdog.rs

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1#[doc = "WDOG"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "Watchdog Control and Status Register"]
5    pub CS: crate::RWRegister<u32>,
6    #[doc = "Watchdog Counter Register"]
7    pub CNT: crate::RWRegister<u32>,
8    #[doc = "Watchdog Timeout Value Register"]
9    pub TOVAL: crate::RWRegister<u32>,
10    #[doc = "Watchdog Window Register"]
11    pub WIN: crate::RWRegister<u32>,
12}
13#[doc = "Watchdog Control and Status Register"]
14pub mod CS {
15    #[doc = "Stop Enable"]
16    pub mod STOP {
17        pub const offset: u32 = 0;
18        pub const mask: u32 = 0x01 << offset;
19        pub mod R {}
20        pub mod W {}
21        pub mod RW {
22            #[doc = "Watchdog disabled in chip stop mode."]
23            pub const STOP_0: u32 = 0;
24            #[doc = "Watchdog enabled in chip stop mode."]
25            pub const STOP_1: u32 = 0x01;
26        }
27    }
28    #[doc = "Wait Enable"]
29    pub mod WAIT {
30        pub const offset: u32 = 1;
31        pub const mask: u32 = 0x01 << offset;
32        pub mod R {}
33        pub mod W {}
34        pub mod RW {
35            #[doc = "Watchdog disabled in chip wait mode."]
36            pub const WAIT_0: u32 = 0;
37            #[doc = "Watchdog enabled in chip wait mode."]
38            pub const WAIT_1: u32 = 0x01;
39        }
40    }
41    #[doc = "Debug Enable"]
42    pub mod DBG {
43        pub const offset: u32 = 2;
44        pub const mask: u32 = 0x01 << offset;
45        pub mod R {}
46        pub mod W {}
47        pub mod RW {
48            #[doc = "Watchdog disabled in chip debug mode."]
49            pub const DBG_0: u32 = 0;
50            #[doc = "Watchdog enabled in chip debug mode."]
51            pub const DBG_1: u32 = 0x01;
52        }
53    }
54    #[doc = "Watchdog Test"]
55    pub mod TST {
56        pub const offset: u32 = 3;
57        pub const mask: u32 = 0x03 << offset;
58        pub mod R {}
59        pub mod W {}
60        pub mod RW {
61            #[doc = "Watchdog test mode disabled."]
62            pub const TST_0: u32 = 0;
63            #[doc = "Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode."]
64            pub const TST_1: u32 = 0x01;
65            #[doc = "Watchdog test mode enabled, only the low byte is used. CNT\\[CNTLOW\\] is compared with TOVAL\\[TOVALLOW\\]."]
66            pub const TST_2: u32 = 0x02;
67            #[doc = "Watchdog test mode enabled, only the high byte is used. CNT\\[CNTHIGH\\] is compared with TOVAL\\[TOVALHIGH\\]."]
68            pub const TST_3: u32 = 0x03;
69        }
70    }
71    #[doc = "Allow updates"]
72    pub mod UPDATE {
73        pub const offset: u32 = 5;
74        pub const mask: u32 = 0x01 << offset;
75        pub mod R {}
76        pub mod W {}
77        pub mod RW {
78            #[doc = "Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset."]
79            pub const UPDATE_0: u32 = 0;
80            #[doc = "Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence."]
81            pub const UPDATE_1: u32 = 0x01;
82        }
83    }
84    #[doc = "Watchdog Interrupt"]
85    pub mod INT {
86        pub const offset: u32 = 6;
87        pub const mask: u32 = 0x01 << offset;
88        pub mod R {}
89        pub mod W {}
90        pub mod RW {
91            #[doc = "Watchdog interrupts are disabled. Watchdog resets are not delayed."]
92            pub const INT_0: u32 = 0;
93            #[doc = "Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch."]
94            pub const INT_1: u32 = 0x01;
95        }
96    }
97    #[doc = "Watchdog Enable"]
98    pub mod EN {
99        pub const offset: u32 = 7;
100        pub const mask: u32 = 0x01 << offset;
101        pub mod R {}
102        pub mod W {}
103        pub mod RW {
104            #[doc = "Watchdog disabled."]
105            pub const EN_0: u32 = 0;
106            #[doc = "Watchdog enabled."]
107            pub const EN_1: u32 = 0x01;
108        }
109    }
110    #[doc = "Watchdog Clock"]
111    pub mod CLK {
112        pub const offset: u32 = 8;
113        pub const mask: u32 = 0x03 << offset;
114        pub mod R {}
115        pub mod W {}
116        pub mod RW {
117            #[doc = "Bus clock"]
118            pub const CLK_0: u32 = 0;
119            #[doc = "LPO clock"]
120            pub const CLK_1: u32 = 0x01;
121            #[doc = "INTCLK (internal clock)"]
122            pub const CLK_2: u32 = 0x02;
123            #[doc = "ERCLK (external reference clock)"]
124            pub const CLK_3: u32 = 0x03;
125        }
126    }
127    #[doc = "Reconfiguration Success"]
128    pub mod RCS {
129        pub const offset: u32 = 10;
130        pub const mask: u32 = 0x01 << offset;
131        pub mod R {}
132        pub mod W {}
133        pub mod RW {
134            #[doc = "Reconfiguring WDOG."]
135            pub const RCS_0: u32 = 0;
136            #[doc = "Reconfiguration is successful."]
137            pub const RCS_1: u32 = 0x01;
138        }
139    }
140    #[doc = "Unlock status"]
141    pub mod ULK {
142        pub const offset: u32 = 11;
143        pub const mask: u32 = 0x01 << offset;
144        pub mod R {}
145        pub mod W {}
146        pub mod RW {
147            #[doc = "WDOG is locked."]
148            pub const ULK_0: u32 = 0;
149            #[doc = "WDOG is unlocked."]
150            pub const ULK_1: u32 = 0x01;
151        }
152    }
153    #[doc = "Watchdog prescaler"]
154    pub mod PRES {
155        pub const offset: u32 = 12;
156        pub const mask: u32 = 0x01 << offset;
157        pub mod R {}
158        pub mod W {}
159        pub mod RW {
160            #[doc = "256 prescaler disabled."]
161            pub const PRES_0: u32 = 0;
162            #[doc = "256 prescaler enabled."]
163            pub const PRES_1: u32 = 0x01;
164        }
165    }
166    #[doc = "Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words"]
167    pub mod CMD32EN {
168        pub const offset: u32 = 13;
169        pub const mask: u32 = 0x01 << offset;
170        pub mod R {}
171        pub mod W {}
172        pub mod RW {
173            #[doc = "Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported."]
174            pub const CMD32EN_0: u32 = 0;
175            #[doc = "Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported."]
176            pub const CMD32EN_1: u32 = 0x01;
177        }
178    }
179    #[doc = "Watchdog Interrupt Flag"]
180    pub mod FLG {
181        pub const offset: u32 = 14;
182        pub const mask: u32 = 0x01 << offset;
183        pub mod R {}
184        pub mod W {}
185        pub mod RW {
186            #[doc = "No interrupt occurred."]
187            pub const FLG_0: u32 = 0;
188            #[doc = "An interrupt occurred."]
189            pub const FLG_1: u32 = 0x01;
190        }
191    }
192    #[doc = "Watchdog Window"]
193    pub mod WIN {
194        pub const offset: u32 = 15;
195        pub const mask: u32 = 0x01 << offset;
196        pub mod R {}
197        pub mod W {}
198        pub mod RW {
199            #[doc = "Window mode disabled."]
200            pub const WIN_0: u32 = 0;
201            #[doc = "Window mode enabled."]
202            pub const WIN_1: u32 = 0x01;
203        }
204    }
205}
206#[doc = "Watchdog Counter Register"]
207pub mod CNT {
208    #[doc = "Low byte of the Watchdog Counter"]
209    pub mod CNTLOW {
210        pub const offset: u32 = 0;
211        pub const mask: u32 = 0xff << offset;
212        pub mod R {}
213        pub mod W {}
214        pub mod RW {}
215    }
216    #[doc = "High byte of the Watchdog Counter"]
217    pub mod CNTHIGH {
218        pub const offset: u32 = 8;
219        pub const mask: u32 = 0xff << offset;
220        pub mod R {}
221        pub mod W {}
222        pub mod RW {}
223    }
224}
225#[doc = "Watchdog Timeout Value Register"]
226pub mod TOVAL {
227    #[doc = "Low byte of the timeout value"]
228    pub mod TOVALLOW {
229        pub const offset: u32 = 0;
230        pub const mask: u32 = 0xff << offset;
231        pub mod R {}
232        pub mod W {}
233        pub mod RW {}
234    }
235    #[doc = "High byte of the timeout value"]
236    pub mod TOVALHIGH {
237        pub const offset: u32 = 8;
238        pub const mask: u32 = 0xff << offset;
239        pub mod R {}
240        pub mod W {}
241        pub mod RW {}
242    }
243}
244#[doc = "Watchdog Window Register"]
245pub mod WIN {
246    #[doc = "Low byte of Watchdog Window"]
247    pub mod WINLOW {
248        pub const offset: u32 = 0;
249        pub const mask: u32 = 0xff << offset;
250        pub mod R {}
251        pub mod W {}
252        pub mod RW {}
253    }
254    #[doc = "High byte of Watchdog Window"]
255    pub mod WINHIGH {
256        pub const offset: u32 = 8;
257        pub const mask: u32 = 0xff << offset;
258        pub mod R {}
259        pub mod W {}
260        pub mod RW {}
261    }
262}
imxrt_ral/blocks/imxrt1011/rtwdog.rs

imxrt_ral/blocks/imxrt1011/
rtwdog.rs
