rp2040_pac/i2c0/
ic_comp_param_1.rs

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1#[doc = "Register `IC_COMP_PARAM_1` reader"]
2pub type R = crate::R<IC_COMP_PARAM_1_SPEC>;
3#[doc = "Field `APB_DATA_WIDTH` reader - APB data bus width is 32 bits"]
4pub type APB_DATA_WIDTH_R = crate::FieldReader;
5#[doc = "Field `MAX_SPEED_MODE` reader - MAX SPEED MODE = FAST MODE"]
6pub type MAX_SPEED_MODE_R = crate::FieldReader;
7#[doc = "Field `HC_COUNT_VALUES` reader - Programmable count values for each mode."]
8pub type HC_COUNT_VALUES_R = crate::BitReader;
9#[doc = "Field `INTR_IO` reader - COMBINED Interrupt outputs"]
10pub type INTR_IO_R = crate::BitReader;
11#[doc = "Field `HAS_DMA` reader - DMA handshaking signals are enabled"]
12pub type HAS_DMA_R = crate::BitReader;
13#[doc = "Field `ADD_ENCODED_PARAMS` reader - Encoded parameters not visible"]
14pub type ADD_ENCODED_PARAMS_R = crate::BitReader;
15#[doc = "Field `RX_BUFFER_DEPTH` reader - RX Buffer Depth = 16"]
16pub type RX_BUFFER_DEPTH_R = crate::FieldReader;
17#[doc = "Field `TX_BUFFER_DEPTH` reader - TX Buffer Depth = 16"]
18pub type TX_BUFFER_DEPTH_R = crate::FieldReader;
19impl R {
20    #[doc = "Bits 0:1 - APB data bus width is 32 bits"]
21    #[inline(always)]
22    pub fn apb_data_width(&self) -> APB_DATA_WIDTH_R {
23        APB_DATA_WIDTH_R::new((self.bits & 3) as u8)
24    }
25    #[doc = "Bits 2:3 - MAX SPEED MODE = FAST MODE"]
26    #[inline(always)]
27    pub fn max_speed_mode(&self) -> MAX_SPEED_MODE_R {
28        MAX_SPEED_MODE_R::new(((self.bits >> 2) & 3) as u8)
29    }
30    #[doc = "Bit 4 - Programmable count values for each mode."]
31    #[inline(always)]
32    pub fn hc_count_values(&self) -> HC_COUNT_VALUES_R {
33        HC_COUNT_VALUES_R::new(((self.bits >> 4) & 1) != 0)
34    }
35    #[doc = "Bit 5 - COMBINED Interrupt outputs"]
36    #[inline(always)]
37    pub fn intr_io(&self) -> INTR_IO_R {
38        INTR_IO_R::new(((self.bits >> 5) & 1) != 0)
39    }
40    #[doc = "Bit 6 - DMA handshaking signals are enabled"]
41    #[inline(always)]
42    pub fn has_dma(&self) -> HAS_DMA_R {
43        HAS_DMA_R::new(((self.bits >> 6) & 1) != 0)
44    }
45    #[doc = "Bit 7 - Encoded parameters not visible"]
46    #[inline(always)]
47    pub fn add_encoded_params(&self) -> ADD_ENCODED_PARAMS_R {
48        ADD_ENCODED_PARAMS_R::new(((self.bits >> 7) & 1) != 0)
49    }
50    #[doc = "Bits 8:15 - RX Buffer Depth = 16"]
51    #[inline(always)]
52    pub fn rx_buffer_depth(&self) -> RX_BUFFER_DEPTH_R {
53        RX_BUFFER_DEPTH_R::new(((self.bits >> 8) & 0xff) as u8)
54    }
55    #[doc = "Bits 16:23 - TX Buffer Depth = 16"]
56    #[inline(always)]
57    pub fn tx_buffer_depth(&self) -> TX_BUFFER_DEPTH_R {
58        TX_BUFFER_DEPTH_R::new(((self.bits >> 16) & 0xff) as u8)
59    }
60}
61#[doc = "Component Parameter Register 1  
62
63 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters  
64
65You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
66pub struct IC_COMP_PARAM_1_SPEC;
67impl crate::RegisterSpec for IC_COMP_PARAM_1_SPEC {
68    type Ux = u32;
69}
70#[doc = "`read()` method returns [`ic_comp_param_1::R`](R) reader structure"]
71impl crate::Readable for IC_COMP_PARAM_1_SPEC {}
72#[doc = "`reset()` method sets IC_COMP_PARAM_1 to value 0"]
73impl crate::Resettable for IC_COMP_PARAM_1_SPEC {
74    const RESET_VALUE: u32 = 0;
75}
rp2040_pac/i2c0/ic_comp_param_1.rs

rp2040_pac/i2c0/
ic_comp_param_1.rs
