rp2040_pac/clocks/
clk_sys_resus_ctrl.rs

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1#[doc = "Register `CLK_SYS_RESUS_CTRL` reader"]
2pub type R = crate::R<CLK_SYS_RESUS_CTRL_SPEC>;
3#[doc = "Register `CLK_SYS_RESUS_CTRL` writer"]
4pub type W = crate::W<CLK_SYS_RESUS_CTRL_SPEC>;
5#[doc = "Field `TIMEOUT` reader - This is expressed as a number of clk_ref cycles  
6 and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
7pub type TIMEOUT_R = crate::FieldReader;
8#[doc = "Field `TIMEOUT` writer - This is expressed as a number of clk_ref cycles  
9 and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
10pub type TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
11#[doc = "Field `ENABLE` reader - Enable resus"]
12pub type ENABLE_R = crate::BitReader;
13#[doc = "Field `ENABLE` writer - Enable resus"]
14pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `FRCE` reader - Force a resus, for test purposes only"]
16pub type FRCE_R = crate::BitReader;
17#[doc = "Field `FRCE` writer - Force a resus, for test purposes only"]
18pub type FRCE_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `CLEAR` reader - For clearing the resus after the fault that triggered it has been corrected"]
20pub type CLEAR_R = crate::BitReader;
21#[doc = "Field `CLEAR` writer - For clearing the resus after the fault that triggered it has been corrected"]
22pub type CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
23impl R {
24    #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles  
25 and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
26    #[inline(always)]
27    pub fn timeout(&self) -> TIMEOUT_R {
28        TIMEOUT_R::new((self.bits & 0xff) as u8)
29    }
30    #[doc = "Bit 8 - Enable resus"]
31    #[inline(always)]
32    pub fn enable(&self) -> ENABLE_R {
33        ENABLE_R::new(((self.bits >> 8) & 1) != 0)
34    }
35    #[doc = "Bit 12 - Force a resus, for test purposes only"]
36    #[inline(always)]
37    pub fn frce(&self) -> FRCE_R {
38        FRCE_R::new(((self.bits >> 12) & 1) != 0)
39    }
40    #[doc = "Bit 16 - For clearing the resus after the fault that triggered it has been corrected"]
41    #[inline(always)]
42    pub fn clear(&self) -> CLEAR_R {
43        CLEAR_R::new(((self.bits >> 16) & 1) != 0)
44    }
45}
46impl W {
47    #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles  
48 and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
49    #[inline(always)]
50    #[must_use]
51    pub fn timeout(&mut self) -> TIMEOUT_W<CLK_SYS_RESUS_CTRL_SPEC> {
52        TIMEOUT_W::new(self, 0)
53    }
54    #[doc = "Bit 8 - Enable resus"]
55    #[inline(always)]
56    #[must_use]
57    pub fn enable(&mut self) -> ENABLE_W<CLK_SYS_RESUS_CTRL_SPEC> {
58        ENABLE_W::new(self, 8)
59    }
60    #[doc = "Bit 12 - Force a resus, for test purposes only"]
61    #[inline(always)]
62    #[must_use]
63    pub fn frce(&mut self) -> FRCE_W<CLK_SYS_RESUS_CTRL_SPEC> {
64        FRCE_W::new(self, 12)
65    }
66    #[doc = "Bit 16 - For clearing the resus after the fault that triggered it has been corrected"]
67    #[inline(always)]
68    #[must_use]
69    pub fn clear(&mut self) -> CLEAR_W<CLK_SYS_RESUS_CTRL_SPEC> {
70        CLEAR_W::new(self, 16)
71    }
72    #[doc = r" Writes raw bits to the register."]
73    #[doc = r""]
74    #[doc = r" # Safety"]
75    #[doc = r""]
76    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.bits = bits;
80        self
81    }
82}
83#[doc = "  
84
85You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
86pub struct CLK_SYS_RESUS_CTRL_SPEC;
87impl crate::RegisterSpec for CLK_SYS_RESUS_CTRL_SPEC {
88    type Ux = u32;
89}
90#[doc = "`read()` method returns [`clk_sys_resus_ctrl::R`](R) reader structure"]
91impl crate::Readable for CLK_SYS_RESUS_CTRL_SPEC {}
92#[doc = "`write(|w| ..)` method takes [`clk_sys_resus_ctrl::W`](W) writer structure"]
93impl crate::Writable for CLK_SYS_RESUS_CTRL_SPEC {
94    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
95    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
96}
97#[doc = "`reset()` method sets CLK_SYS_RESUS_CTRL to value 0xff"]
98impl crate::Resettable for CLK_SYS_RESUS_CTRL_SPEC {
99    const RESET_VALUE: u32 = 0xff;
100}
rp2040_pac/clocks/clk_sys_resus_ctrl.rs

rp2040_pac/clocks/
clk_sys_resus_ctrl.rs
