rp2040_pac/xip_ctrl/
stream_addr.rs

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1#[doc = "Register `STREAM_ADDR` reader"]
2pub type R = crate::R<STREAM_ADDR_SPEC>;
3#[doc = "Register `STREAM_ADDR` writer"]
4pub type W = crate::W<STREAM_ADDR_SPEC>;
5#[doc = "Field `STREAM_ADDR` reader - The address of the next word to be streamed from flash to the streaming FIFO.  
6 Increments automatically after each flash access.  
7 Write the initial access address here before starting a streaming read."]
8pub type STREAM_ADDR_R = crate::FieldReader<u32>;
9#[doc = "Field `STREAM_ADDR` writer - The address of the next word to be streamed from flash to the streaming FIFO.  
10 Increments automatically after each flash access.  
11 Write the initial access address here before starting a streaming read."]
12pub type STREAM_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
13impl R {
14    #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO.  
15 Increments automatically after each flash access.  
16 Write the initial access address here before starting a streaming read."]
17    #[inline(always)]
18    pub fn stream_addr(&self) -> STREAM_ADDR_R {
19        STREAM_ADDR_R::new((self.bits >> 2) & 0x3fff_ffff)
20    }
21}
22impl W {
23    #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO.  
24 Increments automatically after each flash access.  
25 Write the initial access address here before starting a streaming read."]
26    #[inline(always)]
27    #[must_use]
28    pub fn stream_addr(&mut self) -> STREAM_ADDR_W<STREAM_ADDR_SPEC> {
29        STREAM_ADDR_W::new(self, 2)
30    }
31    #[doc = r" Writes raw bits to the register."]
32    #[doc = r""]
33    #[doc = r" # Safety"]
34    #[doc = r""]
35    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
36    #[inline(always)]
37    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
38        self.bits = bits;
39        self
40    }
41}
42#[doc = "FIFO stream address  
43
44You can [`read`](crate::generic::Reg::read) this register and get [`stream_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
45pub struct STREAM_ADDR_SPEC;
46impl crate::RegisterSpec for STREAM_ADDR_SPEC {
47    type Ux = u32;
48}
49#[doc = "`read()` method returns [`stream_addr::R`](R) reader structure"]
50impl crate::Readable for STREAM_ADDR_SPEC {}
51#[doc = "`write(|w| ..)` method takes [`stream_addr::W`](W) writer structure"]
52impl crate::Writable for STREAM_ADDR_SPEC {
53    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
54    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
55}
56#[doc = "`reset()` method sets STREAM_ADDR to value 0"]
57impl crate::Resettable for STREAM_ADDR_SPEC {
58    const RESET_VALUE: u32 = 0;
59}
rp2040_pac/xip_ctrl/stream_addr.rs

rp2040_pac/xip_ctrl/
stream_addr.rs
