rp2040_pac/busctrl/
perfsel1.rs

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1#[doc = "Register `PERFSEL1` reader"]
2pub type R = crate::R<PERFSEL1_SPEC>;
3#[doc = "Register `PERFSEL1` writer"]
4pub type W = crate::W<PERFSEL1_SPEC>;
5#[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
6pub type PERFSEL1_R = crate::FieldReader<PERFSEL1_A>;
7#[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.  
8
9Value on reset: 31"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum PERFSEL1_A {
13    #[doc = "0: `0`"]
14    APB_CONTESTED = 0,
15    #[doc = "1: `1`"]
16    APB = 1,
17    #[doc = "2: `10`"]
18    FASTPERI_CONTESTED = 2,
19    #[doc = "3: `11`"]
20    FASTPERI = 3,
21    #[doc = "4: `100`"]
22    SRAM5_CONTESTED = 4,
23    #[doc = "5: `101`"]
24    SRAM5 = 5,
25    #[doc = "6: `110`"]
26    SRAM4_CONTESTED = 6,
27    #[doc = "7: `111`"]
28    SRAM4 = 7,
29    #[doc = "8: `1000`"]
30    SRAM3_CONTESTED = 8,
31    #[doc = "9: `1001`"]
32    SRAM3 = 9,
33    #[doc = "10: `1010`"]
34    SRAM2_CONTESTED = 10,
35    #[doc = "11: `1011`"]
36    SRAM2 = 11,
37    #[doc = "12: `1100`"]
38    SRAM1_CONTESTED = 12,
39    #[doc = "13: `1101`"]
40    SRAM1 = 13,
41    #[doc = "14: `1110`"]
42    SRAM0_CONTESTED = 14,
43    #[doc = "15: `1111`"]
44    SRAM0 = 15,
45    #[doc = "16: `10000`"]
46    XIP_MAIN_CONTESTED = 16,
47    #[doc = "17: `10001`"]
48    XIP_MAIN = 17,
49    #[doc = "18: `10010`"]
50    ROM_CONTESTED = 18,
51    #[doc = "19: `10011`"]
52    ROM = 19,
53}
54impl From<PERFSEL1_A> for u8 {
55    #[inline(always)]
56    fn from(variant: PERFSEL1_A) -> Self {
57        variant as _
58    }
59}
60impl crate::FieldSpec for PERFSEL1_A {
61    type Ux = u8;
62}
63impl PERFSEL1_R {
64    #[doc = "Get enumerated values variant"]
65    #[inline(always)]
66    pub const fn variant(&self) -> Option<PERFSEL1_A> {
67        match self.bits {
68            0 => Some(PERFSEL1_A::APB_CONTESTED),
69            1 => Some(PERFSEL1_A::APB),
70            2 => Some(PERFSEL1_A::FASTPERI_CONTESTED),
71            3 => Some(PERFSEL1_A::FASTPERI),
72            4 => Some(PERFSEL1_A::SRAM5_CONTESTED),
73            5 => Some(PERFSEL1_A::SRAM5),
74            6 => Some(PERFSEL1_A::SRAM4_CONTESTED),
75            7 => Some(PERFSEL1_A::SRAM4),
76            8 => Some(PERFSEL1_A::SRAM3_CONTESTED),
77            9 => Some(PERFSEL1_A::SRAM3),
78            10 => Some(PERFSEL1_A::SRAM2_CONTESTED),
79            11 => Some(PERFSEL1_A::SRAM2),
80            12 => Some(PERFSEL1_A::SRAM1_CONTESTED),
81            13 => Some(PERFSEL1_A::SRAM1),
82            14 => Some(PERFSEL1_A::SRAM0_CONTESTED),
83            15 => Some(PERFSEL1_A::SRAM0),
84            16 => Some(PERFSEL1_A::XIP_MAIN_CONTESTED),
85            17 => Some(PERFSEL1_A::XIP_MAIN),
86            18 => Some(PERFSEL1_A::ROM_CONTESTED),
87            19 => Some(PERFSEL1_A::ROM),
88            _ => None,
89        }
90    }
91    #[doc = "`0`"]
92    #[inline(always)]
93    pub fn is_apb_contested(&self) -> bool {
94        *self == PERFSEL1_A::APB_CONTESTED
95    }
96    #[doc = "`1`"]
97    #[inline(always)]
98    pub fn is_apb(&self) -> bool {
99        *self == PERFSEL1_A::APB
100    }
101    #[doc = "`10`"]
102    #[inline(always)]
103    pub fn is_fastperi_contested(&self) -> bool {
104        *self == PERFSEL1_A::FASTPERI_CONTESTED
105    }
106    #[doc = "`11`"]
107    #[inline(always)]
108    pub fn is_fastperi(&self) -> bool {
109        *self == PERFSEL1_A::FASTPERI
110    }
111    #[doc = "`100`"]
112    #[inline(always)]
113    pub fn is_sram5_contested(&self) -> bool {
114        *self == PERFSEL1_A::SRAM5_CONTESTED
115    }
116    #[doc = "`101`"]
117    #[inline(always)]
118    pub fn is_sram5(&self) -> bool {
119        *self == PERFSEL1_A::SRAM5
120    }
121    #[doc = "`110`"]
122    #[inline(always)]
123    pub fn is_sram4_contested(&self) -> bool {
124        *self == PERFSEL1_A::SRAM4_CONTESTED
125    }
126    #[doc = "`111`"]
127    #[inline(always)]
128    pub fn is_sram4(&self) -> bool {
129        *self == PERFSEL1_A::SRAM4
130    }
131    #[doc = "`1000`"]
132    #[inline(always)]
133    pub fn is_sram3_contested(&self) -> bool {
134        *self == PERFSEL1_A::SRAM3_CONTESTED
135    }
136    #[doc = "`1001`"]
137    #[inline(always)]
138    pub fn is_sram3(&self) -> bool {
139        *self == PERFSEL1_A::SRAM3
140    }
141    #[doc = "`1010`"]
142    #[inline(always)]
143    pub fn is_sram2_contested(&self) -> bool {
144        *self == PERFSEL1_A::SRAM2_CONTESTED
145    }
146    #[doc = "`1011`"]
147    #[inline(always)]
148    pub fn is_sram2(&self) -> bool {
149        *self == PERFSEL1_A::SRAM2
150    }
151    #[doc = "`1100`"]
152    #[inline(always)]
153    pub fn is_sram1_contested(&self) -> bool {
154        *self == PERFSEL1_A::SRAM1_CONTESTED
155    }
156    #[doc = "`1101`"]
157    #[inline(always)]
158    pub fn is_sram1(&self) -> bool {
159        *self == PERFSEL1_A::SRAM1
160    }
161    #[doc = "`1110`"]
162    #[inline(always)]
163    pub fn is_sram0_contested(&self) -> bool {
164        *self == PERFSEL1_A::SRAM0_CONTESTED
165    }
166    #[doc = "`1111`"]
167    #[inline(always)]
168    pub fn is_sram0(&self) -> bool {
169        *self == PERFSEL1_A::SRAM0
170    }
171    #[doc = "`10000`"]
172    #[inline(always)]
173    pub fn is_xip_main_contested(&self) -> bool {
174        *self == PERFSEL1_A::XIP_MAIN_CONTESTED
175    }
176    #[doc = "`10001`"]
177    #[inline(always)]
178    pub fn is_xip_main(&self) -> bool {
179        *self == PERFSEL1_A::XIP_MAIN
180    }
181    #[doc = "`10010`"]
182    #[inline(always)]
183    pub fn is_rom_contested(&self) -> bool {
184        *self == PERFSEL1_A::ROM_CONTESTED
185    }
186    #[doc = "`10011`"]
187    #[inline(always)]
188    pub fn is_rom(&self) -> bool {
189        *self == PERFSEL1_A::ROM
190    }
191}
192#[doc = "Field `PERFSEL1` writer - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
193pub type PERFSEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 5, PERFSEL1_A>;
194impl<'a, REG> PERFSEL1_W<'a, REG>
195where
196    REG: crate::Writable + crate::RegisterSpec,
197    REG::Ux: From<u8>,
198{
199    #[doc = "`0`"]
200    #[inline(always)]
201    pub fn apb_contested(self) -> &'a mut crate::W<REG> {
202        self.variant(PERFSEL1_A::APB_CONTESTED)
203    }
204    #[doc = "`1`"]
205    #[inline(always)]
206    pub fn apb(self) -> &'a mut crate::W<REG> {
207        self.variant(PERFSEL1_A::APB)
208    }
209    #[doc = "`10`"]
210    #[inline(always)]
211    pub fn fastperi_contested(self) -> &'a mut crate::W<REG> {
212        self.variant(PERFSEL1_A::FASTPERI_CONTESTED)
213    }
214    #[doc = "`11`"]
215    #[inline(always)]
216    pub fn fastperi(self) -> &'a mut crate::W<REG> {
217        self.variant(PERFSEL1_A::FASTPERI)
218    }
219    #[doc = "`100`"]
220    #[inline(always)]
221    pub fn sram5_contested(self) -> &'a mut crate::W<REG> {
222        self.variant(PERFSEL1_A::SRAM5_CONTESTED)
223    }
224    #[doc = "`101`"]
225    #[inline(always)]
226    pub fn sram5(self) -> &'a mut crate::W<REG> {
227        self.variant(PERFSEL1_A::SRAM5)
228    }
229    #[doc = "`110`"]
230    #[inline(always)]
231    pub fn sram4_contested(self) -> &'a mut crate::W<REG> {
232        self.variant(PERFSEL1_A::SRAM4_CONTESTED)
233    }
234    #[doc = "`111`"]
235    #[inline(always)]
236    pub fn sram4(self) -> &'a mut crate::W<REG> {
237        self.variant(PERFSEL1_A::SRAM4)
238    }
239    #[doc = "`1000`"]
240    #[inline(always)]
241    pub fn sram3_contested(self) -> &'a mut crate::W<REG> {
242        self.variant(PERFSEL1_A::SRAM3_CONTESTED)
243    }
244    #[doc = "`1001`"]
245    #[inline(always)]
246    pub fn sram3(self) -> &'a mut crate::W<REG> {
247        self.variant(PERFSEL1_A::SRAM3)
248    }
249    #[doc = "`1010`"]
250    #[inline(always)]
251    pub fn sram2_contested(self) -> &'a mut crate::W<REG> {
252        self.variant(PERFSEL1_A::SRAM2_CONTESTED)
253    }
254    #[doc = "`1011`"]
255    #[inline(always)]
256    pub fn sram2(self) -> &'a mut crate::W<REG> {
257        self.variant(PERFSEL1_A::SRAM2)
258    }
259    #[doc = "`1100`"]
260    #[inline(always)]
261    pub fn sram1_contested(self) -> &'a mut crate::W<REG> {
262        self.variant(PERFSEL1_A::SRAM1_CONTESTED)
263    }
264    #[doc = "`1101`"]
265    #[inline(always)]
266    pub fn sram1(self) -> &'a mut crate::W<REG> {
267        self.variant(PERFSEL1_A::SRAM1)
268    }
269    #[doc = "`1110`"]
270    #[inline(always)]
271    pub fn sram0_contested(self) -> &'a mut crate::W<REG> {
272        self.variant(PERFSEL1_A::SRAM0_CONTESTED)
273    }
274    #[doc = "`1111`"]
275    #[inline(always)]
276    pub fn sram0(self) -> &'a mut crate::W<REG> {
277        self.variant(PERFSEL1_A::SRAM0)
278    }
279    #[doc = "`10000`"]
280    #[inline(always)]
281    pub fn xip_main_contested(self) -> &'a mut crate::W<REG> {
282        self.variant(PERFSEL1_A::XIP_MAIN_CONTESTED)
283    }
284    #[doc = "`10001`"]
285    #[inline(always)]
286    pub fn xip_main(self) -> &'a mut crate::W<REG> {
287        self.variant(PERFSEL1_A::XIP_MAIN)
288    }
289    #[doc = "`10010`"]
290    #[inline(always)]
291    pub fn rom_contested(self) -> &'a mut crate::W<REG> {
292        self.variant(PERFSEL1_A::ROM_CONTESTED)
293    }
294    #[doc = "`10011`"]
295    #[inline(always)]
296    pub fn rom(self) -> &'a mut crate::W<REG> {
297        self.variant(PERFSEL1_A::ROM)
298    }
299}
300impl R {
301    #[doc = "Bits 0:4 - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
302    #[inline(always)]
303    pub fn perfsel1(&self) -> PERFSEL1_R {
304        PERFSEL1_R::new((self.bits & 0x1f) as u8)
305    }
306}
307impl W {
308    #[doc = "Bits 0:4 - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
309    #[inline(always)]
310    #[must_use]
311    pub fn perfsel1(&mut self) -> PERFSEL1_W<PERFSEL1_SPEC> {
312        PERFSEL1_W::new(self, 0)
313    }
314    #[doc = r" Writes raw bits to the register."]
315    #[doc = r""]
316    #[doc = r" # Safety"]
317    #[doc = r""]
318    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
319    #[inline(always)]
320    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
321        self.bits = bits;
322        self
323    }
324}
325#[doc = "Bus fabric performance event select for PERFCTR1  
326
327You can [`read`](crate::generic::Reg::read) this register and get [`perfsel1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
328pub struct PERFSEL1_SPEC;
329impl crate::RegisterSpec for PERFSEL1_SPEC {
330    type Ux = u32;
331}
332#[doc = "`read()` method returns [`perfsel1::R`](R) reader structure"]
333impl crate::Readable for PERFSEL1_SPEC {}
334#[doc = "`write(|w| ..)` method takes [`perfsel1::W`](W) writer structure"]
335impl crate::Writable for PERFSEL1_SPEC {
336    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
337    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
338}
339#[doc = "`reset()` method sets PERFSEL1 to value 0x1f"]
340impl crate::Resettable for PERFSEL1_SPEC {
341    const RESET_VALUE: u32 = 0x1f;
342}
rp2040_pac/busctrl/perfsel1.rs

rp2040_pac/busctrl/
perfsel1.rs
