rp2040_pac/sio/
interp0_base_1and0.rs

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1#[doc = "Register `INTERP0_BASE_1AND0` writer"]
2pub type W = crate::W<INTERP0_BASE_1AND0_SPEC>;
3impl core::fmt::Debug for crate::generic::Reg<INTERP0_BASE_1AND0_SPEC> {
4    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
5        write!(f, "(not readable)")
6    }
7}
8impl W {
9    #[doc = r" Writes raw bits to the register."]
10    #[doc = r""]
11    #[doc = r" # Safety"]
12    #[doc = r""]
13    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
14    #[inline(always)]
15    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
16        self.bits = bits;
17        self
18    }
19}
20#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.  
21 Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.  
22
23You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24pub struct INTERP0_BASE_1AND0_SPEC;
25impl crate::RegisterSpec for INTERP0_BASE_1AND0_SPEC {
26    type Ux = u32;
27}
28#[doc = "`write(|w| ..)` method takes [`interp0_base_1and0::W`](W) writer structure"]
29impl crate::Writable for INTERP0_BASE_1AND0_SPEC {
30    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
31    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
32}
33#[doc = "`reset()` method sets INTERP0_BASE_1AND0 to value 0"]
34impl crate::Resettable for INTERP0_BASE_1AND0_SPEC {
35    const RESET_VALUE: u32 = 0;
36}
rp2040_pac/sio/interp0_base_1and0.rs

rp2040_pac/sio/
interp0_base_1and0.rs
