imxrt_ral/blocks/imxrt1011/
trng.rs

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1#[doc = "TRNG"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "Miscellaneous Control Register"]
5    pub MCTL: crate::RWRegister<u32>,
6    #[doc = "Statistical Check Miscellaneous Register"]
7    pub SCMISC: crate::RWRegister<u32>,
8    #[doc = "Poker Range Register"]
9    pub PKRRNG: crate::RWRegister<u32>,
10    #[doc = "Poker Maximum Limit Register"]
11    pub PKRMAX: crate::RWRegister<u32>,
12    #[doc = "Seed Control Register"]
13    pub SDCTL: crate::RWRegister<u32>,
14    #[doc = "Sparse Bit Limit Register"]
15    pub SBLIM: crate::RWRegister<u32>,
16    #[doc = "Frequency Count Minimum Limit Register"]
17    pub FRQMIN: crate::RWRegister<u32>,
18    #[doc = "Frequency Count Maximum Limit Register"]
19    pub FRQMAX: crate::RWRegister<u32>,
20    #[doc = "Statistical Check Monobit Limit Register"]
21    pub SCML: crate::RWRegister<u32>,
22    #[doc = "Statistical Check Run Length 1 Limit Register"]
23    pub SCR1L: crate::RWRegister<u32>,
24    #[doc = "Statistical Check Run Length 2 Limit Register"]
25    pub SCR2L: crate::RWRegister<u32>,
26    #[doc = "Statistical Check Run Length 3 Limit Register"]
27    pub SCR3L: crate::RWRegister<u32>,
28    #[doc = "Statistical Check Run Length 4 Limit Register"]
29    pub SCR4L: crate::RWRegister<u32>,
30    #[doc = "Statistical Check Run Length 5 Limit Register"]
31    pub SCR5L: crate::RWRegister<u32>,
32    #[doc = "Statistical Check Run Length 6+ Limit Register"]
33    pub SCR6PL: crate::RWRegister<u32>,
34    #[doc = "Status Register"]
35    pub STATUS: crate::RORegister<u32>,
36    #[doc = "Entropy Read Register"]
37    pub ENT: [crate::RORegister<u32>; 16usize],
38    #[doc = "Statistical Check Poker Count 1 and 0 Register"]
39    pub PKRCNT10: crate::RORegister<u32>,
40    #[doc = "Statistical Check Poker Count 3 and 2 Register"]
41    pub PKRCNT32: crate::RORegister<u32>,
42    #[doc = "Statistical Check Poker Count 5 and 4 Register"]
43    pub PKRCNT54: crate::RORegister<u32>,
44    #[doc = "Statistical Check Poker Count 7 and 6 Register"]
45    pub PKRCNT76: crate::RORegister<u32>,
46    #[doc = "Statistical Check Poker Count 9 and 8 Register"]
47    pub PKRCNT98: crate::RORegister<u32>,
48    #[doc = "Statistical Check Poker Count B and A Register"]
49    pub PKRCNTBA: crate::RORegister<u32>,
50    #[doc = "Statistical Check Poker Count D and C Register"]
51    pub PKRCNTDC: crate::RORegister<u32>,
52    #[doc = "Statistical Check Poker Count F and E Register"]
53    pub PKRCNTFE: crate::RORegister<u32>,
54    #[doc = "Security Configuration Register"]
55    pub SEC_CFG: crate::RWRegister<u32>,
56    #[doc = "Interrupt Control Register"]
57    pub INT_CTRL: crate::RWRegister<u32>,
58    #[doc = "Mask Register"]
59    pub INT_MASK: crate::RWRegister<u32>,
60    #[doc = "Interrupt Status Register"]
61    pub INT_STATUS: crate::RORegister<u32>,
62    _reserved0: [u8; 0x40],
63    #[doc = "Version ID Register (MS)"]
64    pub VID1: crate::RORegister<u32>,
65    #[doc = "Version ID Register (LS)"]
66    pub VID2: crate::RORegister<u32>,
67}
68#[doc = "Miscellaneous Control Register"]
69pub mod MCTL {
70    #[doc = "Sample Mode"]
71    pub mod SAMP_MODE {
72        pub const offset: u32 = 0;
73        pub const mask: u32 = 0x03 << offset;
74        pub mod R {}
75        pub mod W {}
76        pub mod RW {
77            #[doc = "use Von Neumann data into both Entropy shifter and Statistical Checker"]
78            pub const SAMP_MODE_0: u32 = 0;
79            #[doc = "use raw data into both Entropy shifter and Statistical Checker"]
80            pub const SAMP_MODE_1: u32 = 0x01;
81            #[doc = "use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker"]
82            pub const SAMP_MODE_2: u32 = 0x02;
83            #[doc = "undefined/reserved."]
84            pub const SAMP_MODE_3: u32 = 0x03;
85        }
86    }
87    #[doc = "Oscillator Divide"]
88    pub mod OSC_DIV {
89        pub const offset: u32 = 2;
90        pub const mask: u32 = 0x03 << offset;
91        pub mod R {}
92        pub mod W {}
93        pub mod RW {
94            #[doc = "use ring oscillator with no divide"]
95            pub const OSC_DIV_0: u32 = 0;
96            #[doc = "use ring oscillator divided-by-2"]
97            pub const OSC_DIV_1: u32 = 0x01;
98            #[doc = "use ring oscillator divided-by-4"]
99            pub const OSC_DIV_2: u32 = 0x02;
100            #[doc = "use ring oscillator divided-by-8"]
101            pub const OSC_DIV_3: u32 = 0x03;
102        }
103    }
104    #[doc = "This bit is unused. Always reads zero."]
105    pub mod UNUSED4 {
106        pub const offset: u32 = 4;
107        pub const mask: u32 = 0x01 << offset;
108        pub mod R {}
109        pub mod W {}
110        pub mod RW {}
111    }
112    #[doc = "This bit is unused. Always reads zero."]
113    pub mod UNUSED5 {
114        pub const offset: u32 = 5;
115        pub const mask: u32 = 0x01 << offset;
116        pub mod R {}
117        pub mod W {}
118        pub mod RW {}
119    }
120    #[doc = "Reset Defaults"]
121    pub mod RST_DEF {
122        pub const offset: u32 = 6;
123        pub const mask: u32 = 0x01 << offset;
124        pub mod R {}
125        pub mod W {}
126        pub mod RW {}
127    }
128    #[doc = "Force System Clock"]
129    pub mod FOR_SCLK {
130        pub const offset: u32 = 7;
131        pub const mask: u32 = 0x01 << offset;
132        pub mod R {}
133        pub mod W {}
134        pub mod RW {}
135    }
136    #[doc = "Read only: Frequency Count Fail"]
137    pub mod FCT_FAIL {
138        pub const offset: u32 = 8;
139        pub const mask: u32 = 0x01 << offset;
140        pub mod R {}
141        pub mod W {}
142        pub mod RW {}
143    }
144    #[doc = "Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT."]
145    pub mod FCT_VAL {
146        pub const offset: u32 = 9;
147        pub const mask: u32 = 0x01 << offset;
148        pub mod R {}
149        pub mod W {}
150        pub mod RW {}
151    }
152    #[doc = "Read only: Entropy Valid"]
153    pub mod ENT_VAL {
154        pub const offset: u32 = 10;
155        pub const mask: u32 = 0x01 << offset;
156        pub mod R {}
157        pub mod W {}
158        pub mod RW {}
159    }
160    #[doc = "Read only: Test point inside ring oscillator."]
161    pub mod TST_OUT {
162        pub const offset: u32 = 11;
163        pub const mask: u32 = 0x01 << offset;
164        pub mod R {}
165        pub mod W {}
166        pub mod RW {}
167    }
168    #[doc = "Read: Error status"]
169    pub mod ERR {
170        pub const offset: u32 = 12;
171        pub const mask: u32 = 0x01 << offset;
172        pub mod R {}
173        pub mod W {}
174        pub mod RW {}
175    }
176    #[doc = "TRNG_OK_TO_STOP"]
177    pub mod TSTOP_OK {
178        pub const offset: u32 = 13;
179        pub const mask: u32 = 0x01 << offset;
180        pub mod R {}
181        pub mod W {}
182        pub mod RW {}
183    }
184    #[doc = "Long run count continues between entropy generations"]
185    pub mod LRUN_CONT {
186        pub const offset: u32 = 14;
187        pub const mask: u32 = 0x01 << offset;
188        pub mod R {}
189        pub mod W {}
190        pub mod RW {}
191    }
192    #[doc = "Programming Mode Select"]
193    pub mod PRGM {
194        pub const offset: u32 = 16;
195        pub const mask: u32 = 0x01 << offset;
196        pub mod R {}
197        pub mod W {}
198        pub mod RW {}
199    }
200}
201#[doc = "Statistical Check Miscellaneous Register"]
202pub mod SCMISC {
203    #[doc = "LONG RUN MAX LIMIT"]
204    pub mod LRUN_MAX {
205        pub const offset: u32 = 0;
206        pub const mask: u32 = 0xff << offset;
207        pub mod R {}
208        pub mod W {}
209        pub mod RW {}
210    }
211    #[doc = "RETRY COUNT"]
212    pub mod RTY_CT {
213        pub const offset: u32 = 16;
214        pub const mask: u32 = 0x0f << offset;
215        pub mod R {}
216        pub mod W {}
217        pub mod RW {}
218    }
219}
220#[doc = "Poker Range Register"]
221pub mod PKRRNG {
222    #[doc = "Poker Range"]
223    pub mod PKR_RNG {
224        pub const offset: u32 = 0;
225        pub const mask: u32 = 0xffff << offset;
226        pub mod R {}
227        pub mod W {}
228        pub mod RW {}
229    }
230}
231#[doc = "Poker Maximum Limit Register"]
232pub mod PKRMAX {
233    #[doc = "Poker Maximum Limit."]
234    pub mod PKR_MAX {
235        pub const offset: u32 = 0;
236        pub const mask: u32 = 0x00ff_ffff << offset;
237        pub mod R {}
238        pub mod W {}
239        pub mod RW {}
240    }
241}
242#[doc = "Seed Control Register"]
243pub mod SDCTL {
244    #[doc = "Sample Size"]
245    pub mod SAMP_SIZE {
246        pub const offset: u32 = 0;
247        pub const mask: u32 = 0xffff << offset;
248        pub mod R {}
249        pub mod W {}
250        pub mod RW {}
251    }
252    #[doc = "Entropy Delay"]
253    pub mod ENT_DLY {
254        pub const offset: u32 = 16;
255        pub const mask: u32 = 0xffff << offset;
256        pub mod R {}
257        pub mod W {}
258        pub mod RW {}
259    }
260}
261#[doc = "Sparse Bit Limit Register"]
262pub mod SBLIM {
263    #[doc = "Sparse Bit Limit"]
264    pub mod SB_LIM {
265        pub const offset: u32 = 0;
266        pub const mask: u32 = 0x03ff << offset;
267        pub mod R {}
268        pub mod W {}
269        pub mod RW {}
270    }
271}
272#[doc = "Frequency Count Minimum Limit Register"]
273pub mod FRQMIN {
274    #[doc = "Frequency Count Minimum Limit"]
275    pub mod FRQ_MIN {
276        pub const offset: u32 = 0;
277        pub const mask: u32 = 0x003f_ffff << offset;
278        pub mod R {}
279        pub mod W {}
280        pub mod RW {}
281    }
282}
283#[doc = "Frequency Count Maximum Limit Register"]
284pub mod FRQMAX {
285    #[doc = "Frequency Counter Maximum Limit"]
286    pub mod FRQ_MAX {
287        pub const offset: u32 = 0;
288        pub const mask: u32 = 0x003f_ffff << offset;
289        pub mod R {}
290        pub mod W {}
291        pub mod RW {}
292    }
293}
294#[doc = "Statistical Check Monobit Limit Register"]
295pub mod SCML {
296    #[doc = "Monobit Maximum Limit"]
297    pub mod MONO_MAX {
298        pub const offset: u32 = 0;
299        pub const mask: u32 = 0xffff << offset;
300        pub mod R {}
301        pub mod W {}
302        pub mod RW {}
303    }
304    #[doc = "Monobit Range"]
305    pub mod MONO_RNG {
306        pub const offset: u32 = 16;
307        pub const mask: u32 = 0xffff << offset;
308        pub mod R {}
309        pub mod W {}
310        pub mod RW {}
311    }
312}
313#[doc = "Statistical Check Run Length 1 Limit Register"]
314pub mod SCR1L {
315    #[doc = "Run Length 1 Maximum Limit"]
316    pub mod RUN1_MAX {
317        pub const offset: u32 = 0;
318        pub const mask: u32 = 0x7fff << offset;
319        pub mod R {}
320        pub mod W {}
321        pub mod RW {}
322    }
323    #[doc = "Run Length 1 Range"]
324    pub mod RUN1_RNG {
325        pub const offset: u32 = 16;
326        pub const mask: u32 = 0x7fff << offset;
327        pub mod R {}
328        pub mod W {}
329        pub mod RW {}
330    }
331}
332#[doc = "Statistical Check Run Length 2 Limit Register"]
333pub mod SCR2L {
334    #[doc = "Run Length 2 Maximum Limit"]
335    pub mod RUN2_MAX {
336        pub const offset: u32 = 0;
337        pub const mask: u32 = 0x3fff << offset;
338        pub mod R {}
339        pub mod W {}
340        pub mod RW {}
341    }
342    #[doc = "Run Length 2 Range"]
343    pub mod RUN2_RNG {
344        pub const offset: u32 = 16;
345        pub const mask: u32 = 0x3fff << offset;
346        pub mod R {}
347        pub mod W {}
348        pub mod RW {}
349    }
350}
351#[doc = "Statistical Check Run Length 3 Limit Register"]
352pub mod SCR3L {
353    #[doc = "Run Length 3 Maximum Limit"]
354    pub mod RUN3_MAX {
355        pub const offset: u32 = 0;
356        pub const mask: u32 = 0x1fff << offset;
357        pub mod R {}
358        pub mod W {}
359        pub mod RW {}
360    }
361    #[doc = "Run Length 3 Range"]
362    pub mod RUN3_RNG {
363        pub const offset: u32 = 16;
364        pub const mask: u32 = 0x1fff << offset;
365        pub mod R {}
366        pub mod W {}
367        pub mod RW {}
368    }
369}
370#[doc = "Statistical Check Run Length 4 Limit Register"]
371pub mod SCR4L {
372    #[doc = "Run Length 4 Maximum Limit"]
373    pub mod RUN4_MAX {
374        pub const offset: u32 = 0;
375        pub const mask: u32 = 0x0fff << offset;
376        pub mod R {}
377        pub mod W {}
378        pub mod RW {}
379    }
380    #[doc = "Run Length 4 Range"]
381    pub mod RUN4_RNG {
382        pub const offset: u32 = 16;
383        pub const mask: u32 = 0x0fff << offset;
384        pub mod R {}
385        pub mod W {}
386        pub mod RW {}
387    }
388}
389#[doc = "Statistical Check Run Length 5 Limit Register"]
390pub mod SCR5L {
391    #[doc = "Run Length 5 Maximum Limit"]
392    pub mod RUN5_MAX {
393        pub const offset: u32 = 0;
394        pub const mask: u32 = 0x07ff << offset;
395        pub mod R {}
396        pub mod W {}
397        pub mod RW {}
398    }
399    #[doc = "Run Length 5 Range"]
400    pub mod RUN5_RNG {
401        pub const offset: u32 = 16;
402        pub const mask: u32 = 0x07ff << offset;
403        pub mod R {}
404        pub mod W {}
405        pub mod RW {}
406    }
407}
408#[doc = "Statistical Check Run Length 6+ Limit Register"]
409pub mod SCR6PL {
410    #[doc = "Run Length 6+ Maximum Limit"]
411    pub mod RUN6P_MAX {
412        pub const offset: u32 = 0;
413        pub const mask: u32 = 0x07ff << offset;
414        pub mod R {}
415        pub mod W {}
416        pub mod RW {}
417    }
418    #[doc = "Run Length 6+ Range"]
419    pub mod RUN6P_RNG {
420        pub const offset: u32 = 16;
421        pub const mask: u32 = 0x07ff << offset;
422        pub mod R {}
423        pub mod W {}
424        pub mod RW {}
425    }
426}
427#[doc = "Status Register"]
428pub mod STATUS {
429    #[doc = "Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed."]
430    pub mod TF1BR0 {
431        pub const offset: u32 = 0;
432        pub const mask: u32 = 0x01 << offset;
433        pub mod R {}
434        pub mod W {}
435        pub mod RW {}
436    }
437    #[doc = "Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed."]
438    pub mod TF1BR1 {
439        pub const offset: u32 = 1;
440        pub const mask: u32 = 0x01 << offset;
441        pub mod R {}
442        pub mod W {}
443        pub mod RW {}
444    }
445    #[doc = "Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed."]
446    pub mod TF2BR0 {
447        pub const offset: u32 = 2;
448        pub const mask: u32 = 0x01 << offset;
449        pub mod R {}
450        pub mod W {}
451        pub mod RW {}
452    }
453    #[doc = "Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed."]
454    pub mod TF2BR1 {
455        pub const offset: u32 = 3;
456        pub const mask: u32 = 0x01 << offset;
457        pub mod R {}
458        pub mod W {}
459        pub mod RW {}
460    }
461    #[doc = "Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed."]
462    pub mod TF3BR0 {
463        pub const offset: u32 = 4;
464        pub const mask: u32 = 0x01 << offset;
465        pub mod R {}
466        pub mod W {}
467        pub mod RW {}
468    }
469    #[doc = "Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed."]
470    pub mod TF3BR1 {
471        pub const offset: u32 = 5;
472        pub const mask: u32 = 0x01 << offset;
473        pub mod R {}
474        pub mod W {}
475        pub mod RW {}
476    }
477    #[doc = "Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed."]
478    pub mod TF4BR0 {
479        pub const offset: u32 = 6;
480        pub const mask: u32 = 0x01 << offset;
481        pub mod R {}
482        pub mod W {}
483        pub mod RW {}
484    }
485    #[doc = "Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed."]
486    pub mod TF4BR1 {
487        pub const offset: u32 = 7;
488        pub const mask: u32 = 0x01 << offset;
489        pub mod R {}
490        pub mod W {}
491        pub mod RW {}
492    }
493    #[doc = "Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed."]
494    pub mod TF5BR0 {
495        pub const offset: u32 = 8;
496        pub const mask: u32 = 0x01 << offset;
497        pub mod R {}
498        pub mod W {}
499        pub mod RW {}
500    }
501    #[doc = "Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed."]
502    pub mod TF5BR1 {
503        pub const offset: u32 = 9;
504        pub const mask: u32 = 0x01 << offset;
505        pub mod R {}
506        pub mod W {}
507        pub mod RW {}
508    }
509    #[doc = "Test Fail, 6 Plus Bit Run, Sampling 0s"]
510    pub mod TF6PBR0 {
511        pub const offset: u32 = 10;
512        pub const mask: u32 = 0x01 << offset;
513        pub mod R {}
514        pub mod W {}
515        pub mod RW {}
516    }
517    #[doc = "Test Fail, 6 Plus Bit Run, Sampling 1s"]
518    pub mod TF6PBR1 {
519        pub const offset: u32 = 11;
520        pub const mask: u32 = 0x01 << offset;
521        pub mod R {}
522        pub mod W {}
523        pub mod RW {}
524    }
525    #[doc = "Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed."]
526    pub mod TFSB {
527        pub const offset: u32 = 12;
528        pub const mask: u32 = 0x01 << offset;
529        pub mod R {}
530        pub mod W {}
531        pub mod RW {}
532    }
533    #[doc = "Test Fail, Long Run. If TFLR=1, the Long Run Test has failed."]
534    pub mod TFLR {
535        pub const offset: u32 = 13;
536        pub const mask: u32 = 0x01 << offset;
537        pub mod R {}
538        pub mod W {}
539        pub mod RW {}
540    }
541    #[doc = "Test Fail, Poker. If TFP=1, the Poker Test has failed."]
542    pub mod TFP {
543        pub const offset: u32 = 14;
544        pub const mask: u32 = 0x01 << offset;
545        pub mod R {}
546        pub mod W {}
547        pub mod RW {}
548    }
549    #[doc = "Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed."]
550    pub mod TFMB {
551        pub const offset: u32 = 15;
552        pub const mask: u32 = 0x01 << offset;
553        pub mod R {}
554        pub mod W {}
555        pub mod RW {}
556    }
557    #[doc = "RETRY COUNT"]
558    pub mod RETRY_CT {
559        pub const offset: u32 = 16;
560        pub const mask: u32 = 0x0f << offset;
561        pub mod R {}
562        pub mod W {}
563        pub mod RW {}
564    }
565}
566#[doc = "Entropy Read Register"]
567pub mod ENT {
568    #[doc = "Entropy Value"]
569    pub mod ENT {
570        pub const offset: u32 = 0;
571        pub const mask: u32 = 0xffff_ffff << offset;
572        pub mod R {}
573        pub mod W {}
574        pub mod RW {}
575    }
576}
577#[doc = "Statistical Check Poker Count 1 and 0 Register"]
578pub mod PKRCNT10 {
579    #[doc = "Poker 0h Count"]
580    pub mod PKR_0_CT {
581        pub const offset: u32 = 0;
582        pub const mask: u32 = 0xffff << offset;
583        pub mod R {}
584        pub mod W {}
585        pub mod RW {}
586    }
587    #[doc = "Poker 1h Count"]
588    pub mod PKR_1_CT {
589        pub const offset: u32 = 16;
590        pub const mask: u32 = 0xffff << offset;
591        pub mod R {}
592        pub mod W {}
593        pub mod RW {}
594    }
595}
596#[doc = "Statistical Check Poker Count 3 and 2 Register"]
597pub mod PKRCNT32 {
598    #[doc = "Poker 2h Count"]
599    pub mod PKR_2_CT {
600        pub const offset: u32 = 0;
601        pub const mask: u32 = 0xffff << offset;
602        pub mod R {}
603        pub mod W {}
604        pub mod RW {}
605    }
606    #[doc = "Poker 3h Count"]
607    pub mod PKR_3_CT {
608        pub const offset: u32 = 16;
609        pub const mask: u32 = 0xffff << offset;
610        pub mod R {}
611        pub mod W {}
612        pub mod RW {}
613    }
614}
615#[doc = "Statistical Check Poker Count 5 and 4 Register"]
616pub mod PKRCNT54 {
617    #[doc = "Poker 4h Count"]
618    pub mod PKR_4_CT {
619        pub const offset: u32 = 0;
620        pub const mask: u32 = 0xffff << offset;
621        pub mod R {}
622        pub mod W {}
623        pub mod RW {}
624    }
625    #[doc = "Poker 5h Count"]
626    pub mod PKR_5_CT {
627        pub const offset: u32 = 16;
628        pub const mask: u32 = 0xffff << offset;
629        pub mod R {}
630        pub mod W {}
631        pub mod RW {}
632    }
633}
634#[doc = "Statistical Check Poker Count 7 and 6 Register"]
635pub mod PKRCNT76 {
636    #[doc = "Poker 6h Count"]
637    pub mod PKR_6_CT {
638        pub const offset: u32 = 0;
639        pub const mask: u32 = 0xffff << offset;
640        pub mod R {}
641        pub mod W {}
642        pub mod RW {}
643    }
644    #[doc = "Poker 7h Count"]
645    pub mod PKR_7_CT {
646        pub const offset: u32 = 16;
647        pub const mask: u32 = 0xffff << offset;
648        pub mod R {}
649        pub mod W {}
650        pub mod RW {}
651    }
652}
653#[doc = "Statistical Check Poker Count 9 and 8 Register"]
654pub mod PKRCNT98 {
655    #[doc = "Poker 8h Count"]
656    pub mod PKR_8_CT {
657        pub const offset: u32 = 0;
658        pub const mask: u32 = 0xffff << offset;
659        pub mod R {}
660        pub mod W {}
661        pub mod RW {}
662    }
663    #[doc = "Poker 9h Count"]
664    pub mod PKR_9_CT {
665        pub const offset: u32 = 16;
666        pub const mask: u32 = 0xffff << offset;
667        pub mod R {}
668        pub mod W {}
669        pub mod RW {}
670    }
671}
672#[doc = "Statistical Check Poker Count B and A Register"]
673pub mod PKRCNTBA {
674    #[doc = "Poker Ah Count"]
675    pub mod PKR_A_CT {
676        pub const offset: u32 = 0;
677        pub const mask: u32 = 0xffff << offset;
678        pub mod R {}
679        pub mod W {}
680        pub mod RW {}
681    }
682    #[doc = "Poker Bh Count"]
683    pub mod PKR_B_CT {
684        pub const offset: u32 = 16;
685        pub const mask: u32 = 0xffff << offset;
686        pub mod R {}
687        pub mod W {}
688        pub mod RW {}
689    }
690}
691#[doc = "Statistical Check Poker Count D and C Register"]
692pub mod PKRCNTDC {
693    #[doc = "Poker Ch Count"]
694    pub mod PKR_C_CT {
695        pub const offset: u32 = 0;
696        pub const mask: u32 = 0xffff << offset;
697        pub mod R {}
698        pub mod W {}
699        pub mod RW {}
700    }
701    #[doc = "Poker Dh Count"]
702    pub mod PKR_D_CT {
703        pub const offset: u32 = 16;
704        pub const mask: u32 = 0xffff << offset;
705        pub mod R {}
706        pub mod W {}
707        pub mod RW {}
708    }
709}
710#[doc = "Statistical Check Poker Count F and E Register"]
711pub mod PKRCNTFE {
712    #[doc = "Poker Eh Count"]
713    pub mod PKR_E_CT {
714        pub const offset: u32 = 0;
715        pub const mask: u32 = 0xffff << offset;
716        pub mod R {}
717        pub mod W {}
718        pub mod RW {}
719    }
720    #[doc = "Poker Fh Count"]
721    pub mod PKR_F_CT {
722        pub const offset: u32 = 16;
723        pub const mask: u32 = 0xffff << offset;
724        pub mod R {}
725        pub mod W {}
726        pub mod RW {}
727    }
728}
729#[doc = "Security Configuration Register"]
730pub mod SEC_CFG {
731    #[doc = "This bit is unused. Ignore."]
732    pub mod UNUSED0 {
733        pub const offset: u32 = 0;
734        pub const mask: u32 = 0x01 << offset;
735        pub mod R {}
736        pub mod W {}
737        pub mod RW {}
738    }
739    #[doc = "If set, the TRNG registers cannot be programmed"]
740    pub mod NO_PRGM {
741        pub const offset: u32 = 1;
742        pub const mask: u32 = 0x01 << offset;
743        pub mod R {}
744        pub mod W {}
745        pub mod RW {
746            #[doc = "Programability of registers controlled only by the Miscellaneous Control Register's access mode bit."]
747            pub const NO_PRGM_0: u32 = 0;
748            #[doc = "Overides Miscellaneous Control Register access mode and prevents TRNG register programming."]
749            pub const NO_PRGM_1: u32 = 0x01;
750        }
751    }
752    #[doc = "This bit is unused. Ignore."]
753    pub mod UNUSED2 {
754        pub const offset: u32 = 2;
755        pub const mask: u32 = 0x01 << offset;
756        pub mod R {}
757        pub mod W {}
758        pub mod RW {}
759    }
760}
761#[doc = "Interrupt Control Register"]
762pub mod INT_CTRL {
763    #[doc = "Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted."]
764    pub mod HW_ERR {
765        pub const offset: u32 = 0;
766        pub const mask: u32 = 0x01 << offset;
767        pub mod R {}
768        pub mod W {}
769        pub mod RW {
770            #[doc = "Corresponding bit of INT_STATUS register cleared."]
771            pub const HW_ERR_0: u32 = 0;
772            #[doc = "Corresponding bit of INT_STATUS register active."]
773            pub const HW_ERR_1: u32 = 0x01;
774        }
775    }
776    #[doc = "Same behavior as bit 0 of this register."]
777    pub mod ENT_VAL {
778        pub const offset: u32 = 1;
779        pub const mask: u32 = 0x01 << offset;
780        pub mod R {}
781        pub mod W {}
782        pub mod RW {
783            #[doc = "Same behavior as bit 0 of this register."]
784            pub const ENT_VAL_0: u32 = 0;
785            #[doc = "Same behavior as bit 0 of this register."]
786            pub const ENT_VAL_1: u32 = 0x01;
787        }
788    }
789    #[doc = "Same behavior as bit 0 of this register."]
790    pub mod FRQ_CT_FAIL {
791        pub const offset: u32 = 2;
792        pub const mask: u32 = 0x01 << offset;
793        pub mod R {}
794        pub mod W {}
795        pub mod RW {
796            #[doc = "Same behavior as bit 0 of this register."]
797            pub const FRQ_CT_FAIL_0: u32 = 0;
798            #[doc = "Same behavior as bit 0 of this register."]
799            pub const FRQ_CT_FAIL_1: u32 = 0x01;
800        }
801    }
802}
803#[doc = "Mask Register"]
804pub mod INT_MASK {
805    #[doc = "Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted."]
806    pub mod HW_ERR {
807        pub const offset: u32 = 0;
808        pub const mask: u32 = 0x01 << offset;
809        pub mod R {}
810        pub mod W {}
811        pub mod RW {
812            #[doc = "Corresponding interrupt of INT_STATUS is masked."]
813            pub const HW_ERR_0: u32 = 0;
814            #[doc = "Corresponding bit of INT_STATUS is active."]
815            pub const HW_ERR_1: u32 = 0x01;
816        }
817    }
818    #[doc = "Same behavior as bit 0 of this register."]
819    pub mod ENT_VAL {
820        pub const offset: u32 = 1;
821        pub const mask: u32 = 0x01 << offset;
822        pub mod R {}
823        pub mod W {}
824        pub mod RW {
825            #[doc = "Same behavior as bit 0 of this register."]
826            pub const ENT_VAL_0: u32 = 0;
827            #[doc = "Same behavior as bit 0 of this register."]
828            pub const ENT_VAL_1: u32 = 0x01;
829        }
830    }
831    #[doc = "Same behavior as bit 0 of this register."]
832    pub mod FRQ_CT_FAIL {
833        pub const offset: u32 = 2;
834        pub const mask: u32 = 0x01 << offset;
835        pub mod R {}
836        pub mod W {}
837        pub mod RW {
838            #[doc = "Same behavior as bit 0 of this register."]
839            pub const FRQ_CT_FAIL_0: u32 = 0;
840            #[doc = "Same behavior as bit 0 of this register."]
841            pub const FRQ_CT_FAIL_1: u32 = 0x01;
842        }
843    }
844}
845#[doc = "Interrupt Status Register"]
846pub mod INT_STATUS {
847    #[doc = "Read: Error status"]
848    pub mod HW_ERR {
849        pub const offset: u32 = 0;
850        pub const mask: u32 = 0x01 << offset;
851        pub mod R {}
852        pub mod W {}
853        pub mod RW {
854            #[doc = "no error"]
855            pub const HW_ERR_0: u32 = 0;
856            #[doc = "error detected."]
857            pub const HW_ERR_1: u32 = 0x01;
858        }
859    }
860    #[doc = "Read only: Entropy Valid"]
861    pub mod ENT_VAL {
862        pub const offset: u32 = 1;
863        pub const mask: u32 = 0x01 << offset;
864        pub mod R {}
865        pub mod W {}
866        pub mod RW {
867            #[doc = "Busy generation entropy. Any value read is invalid."]
868            pub const ENT_VAL_0: u32 = 0;
869            #[doc = "TRNG can be stopped and entropy is valid if read."]
870            pub const ENT_VAL_1: u32 = 0x01;
871        }
872    }
873    #[doc = "Read only: Frequency Count Fail"]
874    pub mod FRQ_CT_FAIL {
875        pub const offset: u32 = 2;
876        pub const mask: u32 = 0x01 << offset;
877        pub mod R {}
878        pub mod W {}
879        pub mod RW {
880            #[doc = "No hardware nor self test frequency errors."]
881            pub const FRQ_CT_FAIL_0: u32 = 0;
882            #[doc = "The frequency counter has detected a failure."]
883            pub const FRQ_CT_FAIL_1: u32 = 0x01;
884        }
885    }
886}
887#[doc = "Version ID Register (MS)"]
888pub mod VID1 {
889    #[doc = "Shows the IP's Minor revision of the TRNG."]
890    pub mod MIN_REV {
891        pub const offset: u32 = 0;
892        pub const mask: u32 = 0xff << offset;
893        pub mod R {}
894        pub mod W {}
895        pub mod RW {
896            #[doc = "Minor revision number for TRNG."]
897            pub const MIN_REV_0: u32 = 0;
898        }
899    }
900    #[doc = "Shows the IP's Major revision of the TRNG."]
901    pub mod MAJ_REV {
902        pub const offset: u32 = 8;
903        pub const mask: u32 = 0xff << offset;
904        pub mod R {}
905        pub mod W {}
906        pub mod RW {
907            #[doc = "Major revision number for TRNG."]
908            pub const MAJ_REV_1: u32 = 0x01;
909        }
910    }
911    #[doc = "Shows the IP ID."]
912    pub mod IP_ID {
913        pub const offset: u32 = 16;
914        pub const mask: u32 = 0xffff << offset;
915        pub mod R {}
916        pub mod W {}
917        pub mod RW {
918            #[doc = "ID for TRNG."]
919            pub const IP_ID_48: u32 = 0x30;
920        }
921    }
922}
923#[doc = "Version ID Register (LS)"]
924pub mod VID2 {
925    #[doc = "Shows the IP's Configuaration options for the TRNG."]
926    pub mod CONFIG_OPT {
927        pub const offset: u32 = 0;
928        pub const mask: u32 = 0xff << offset;
929        pub mod R {}
930        pub mod W {}
931        pub mod RW {
932            #[doc = "TRNG_CONFIG_OPT for TRNG."]
933            pub const CONFIG_OPT_0: u32 = 0;
934        }
935    }
936    #[doc = "Shows the IP's ECO revision of the TRNG."]
937    pub mod ECO_REV {
938        pub const offset: u32 = 8;
939        pub const mask: u32 = 0xff << offset;
940        pub mod R {}
941        pub mod W {}
942        pub mod RW {
943            #[doc = "TRNG_ECO_REV for TRNG."]
944            pub const ECO_REV_0: u32 = 0;
945        }
946    }
947    #[doc = "Shows the integration options for the TRNG."]
948    pub mod INTG_OPT {
949        pub const offset: u32 = 16;
950        pub const mask: u32 = 0xff << offset;
951        pub mod R {}
952        pub mod W {}
953        pub mod RW {
954            #[doc = "INTG_OPT for TRNG."]
955            pub const INTG_OPT_0: u32 = 0;
956        }
957    }
958    #[doc = "Shows the compile options for the TRNG."]
959    pub mod ERA {
960        pub const offset: u32 = 24;
961        pub const mask: u32 = 0xff << offset;
962        pub mod R {}
963        pub mod W {}
964        pub mod RW {
965            #[doc = "COMPILE_OPT for TRNG."]
966            pub const ERA_0: u32 = 0;
967        }
968    }
969}
imxrt_ral/blocks/imxrt1011/trng.rs

imxrt_ral/blocks/imxrt1011/
trng.rs
