imxrt_ral/blocks/imxrt1011/
usbnc.rs

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1#[doc = "USB"]
2#[repr(C)]
3pub struct RegisterBlock {
4    _reserved0: [u8; 0x0800],
5    #[doc = "USB OTG1 Control Register"]
6    pub USB_OTG1_CTRL: crate::RWRegister<u32>,
7    _reserved1: [u8; 0x14],
8    #[doc = "OTG1 UTMI PHY Control 0 Register"]
9    pub USB_OTG1_PHY_CTRL_0: crate::RWRegister<u32>,
10}
11#[doc = "USB OTG1 Control Register"]
12pub mod USB_OTG1_CTRL {
13    #[doc = "Disable OTG1 Overcurrent Detection"]
14    pub mod OVER_CUR_DIS {
15        pub const offset: u32 = 7;
16        pub const mask: u32 = 0x01 << offset;
17        pub mod R {}
18        pub mod W {}
19        pub mod RW {
20            #[doc = "Enables overcurrent detection"]
21            pub const OVER_CUR_DIS_0: u32 = 0;
22            #[doc = "Disables overcurrent detection"]
23            pub const OVER_CUR_DIS_1: u32 = 0x01;
24        }
25    }
26    #[doc = "OTG1 Polarity of Overcurrent The polarity of OTG1 port overcurrent event"]
27    pub mod OVER_CUR_POL {
28        pub const offset: u32 = 8;
29        pub const mask: u32 = 0x01 << offset;
30        pub mod R {}
31        pub mod W {}
32        pub mod RW {
33            #[doc = "High active (high on this signal represents an overcurrent condition)"]
34            pub const OVER_CUR_POL_0: u32 = 0;
35            #[doc = "Low active (low on this signal represents an overcurrent condition)"]
36            pub const OVER_CUR_POL_1: u32 = 0x01;
37        }
38    }
39    #[doc = "OTG1 Power Polarity This bit should be set according to PMIC Power Pin polarity."]
40    pub mod PWR_POL {
41        pub const offset: u32 = 9;
42        pub const mask: u32 = 0x01 << offset;
43        pub mod R {}
44        pub mod W {}
45        pub mod RW {
46            #[doc = "PMIC Power Pin is Low active."]
47            pub const PWR_POL_0: u32 = 0;
48            #[doc = "PMIC Power Pin is High active."]
49            pub const PWR_POL_1: u32 = 0x01;
50        }
51    }
52    #[doc = "OTG1 Wake-up Interrupt Enable This bit enables or disables the OTG1 wake-up interrupt"]
53    pub mod WIE {
54        pub const offset: u32 = 10;
55        pub const mask: u32 = 0x01 << offset;
56        pub mod R {}
57        pub mod W {}
58        pub mod RW {
59            #[doc = "Interrupt Disabled"]
60            pub const WIE_0: u32 = 0;
61            #[doc = "Interrupt Enabled"]
62            pub const WIE_1: u32 = 0x01;
63        }
64    }
65    #[doc = "OTG1 Software Wake-up Enable"]
66    pub mod WKUP_SW_EN {
67        pub const offset: u32 = 14;
68        pub const mask: u32 = 0x01 << offset;
69        pub mod R {}
70        pub mod W {}
71        pub mod RW {
72            #[doc = "Disable"]
73            pub const WKUP_SW_EN_0: u32 = 0;
74            #[doc = "Enable"]
75            pub const WKUP_SW_EN_1: u32 = 0x01;
76        }
77    }
78    #[doc = "OTG1 Software Wake-up"]
79    pub mod WKUP_SW {
80        pub const offset: u32 = 15;
81        pub const mask: u32 = 0x01 << offset;
82        pub mod R {}
83        pub mod W {}
84        pub mod RW {
85            #[doc = "Inactive"]
86            pub const WKUP_SW_0: u32 = 0;
87            #[doc = "Force wake-up"]
88            pub const WKUP_SW_1: u32 = 0x01;
89        }
90    }
91    #[doc = "OTG1 Wake-up on ID change enable"]
92    pub mod WKUP_ID_EN {
93        pub const offset: u32 = 16;
94        pub const mask: u32 = 0x01 << offset;
95        pub mod R {}
96        pub mod W {}
97        pub mod RW {
98            #[doc = "Disable"]
99            pub const WKUP_ID_EN_0: u32 = 0;
100            #[doc = "Enable"]
101            pub const WKUP_ID_EN_1: u32 = 0x01;
102        }
103    }
104    #[doc = "OTG1 wake-up on VBUS change enable"]
105    pub mod WKUP_VBUS_EN {
106        pub const offset: u32 = 17;
107        pub const mask: u32 = 0x01 << offset;
108        pub mod R {}
109        pub mod W {}
110        pub mod RW {
111            #[doc = "Disable"]
112            pub const WKUP_VBUS_EN_0: u32 = 0;
113            #[doc = "Enable"]
114            pub const WKUP_VBUS_EN_1: u32 = 0x01;
115        }
116    }
117    #[doc = "Wake-up on DPDM change enable"]
118    pub mod WKUP_DPDM_EN {
119        pub const offset: u32 = 29;
120        pub const mask: u32 = 0x01 << offset;
121        pub mod R {}
122        pub mod W {}
123        pub mod RW {
124            #[doc = "DPDM changes wake-up to be disabled only when VBUS is 0."]
125            pub const WKUP_DPDM_EN_0: u32 = 0;
126            #[doc = "(Default) DPDM changes wake-up to be enabled, it is for device only."]
127            pub const WKUP_DPDM_EN_1: u32 = 0x01;
128        }
129    }
130    #[doc = "OTG1 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG1 port"]
131    pub mod WIR {
132        pub const offset: u32 = 31;
133        pub const mask: u32 = 0x01 << offset;
134        pub mod R {}
135        pub mod W {}
136        pub mod RW {
137            #[doc = "No wake-up interrupt request received"]
138            pub const WIR_0: u32 = 0;
139            #[doc = "Wake-up Interrupt Request received"]
140            pub const WIR_1: u32 = 0x01;
141        }
142    }
143}
144#[doc = "OTG1 UTMI PHY Control 0 Register"]
145pub mod USB_OTG1_PHY_CTRL_0 {
146    #[doc = "Indicating whether OTG1 UTMI PHY clock is valid"]
147    pub mod UTMI_CLK_VLD {
148        pub const offset: u32 = 31;
149        pub const mask: u32 = 0x01 << offset;
150        pub mod R {}
151        pub mod W {}
152        pub mod RW {
153            #[doc = "Invalid"]
154            pub const UTMI_CLK_VLD_0: u32 = 0;
155            #[doc = "Valid"]
156            pub const UTMI_CLK_VLD_1: u32 = 0x01;
157        }
158    }
159}
imxrt_ral/blocks/imxrt1011/usbnc.rs

imxrt_ral/blocks/imxrt1011/
usbnc.rs
