imxrt_ral/blocks/imxrt1011/
flexio.rs

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1#[doc = "FLEXIO"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "Version ID Register"]
5    pub VERID: crate::RORegister<u32>,
6    #[doc = "Parameter Register"]
7    pub PARAM: crate::RORegister<u32>,
8    #[doc = "FlexIO Control Register"]
9    pub CTRL: crate::RWRegister<u32>,
10    #[doc = "Pin State Register"]
11    pub PIN: crate::RORegister<u32>,
12    #[doc = "Shifter Status Register"]
13    pub SHIFTSTAT: crate::RWRegister<u32>,
14    #[doc = "Shifter Error Register"]
15    pub SHIFTERR: crate::RWRegister<u32>,
16    #[doc = "Timer Status Register"]
17    pub TIMSTAT: crate::RWRegister<u32>,
18    _reserved0: [u8; 0x04],
19    #[doc = "Shifter Status Interrupt Enable"]
20    pub SHIFTSIEN: crate::RWRegister<u32>,
21    #[doc = "Shifter Error Interrupt Enable"]
22    pub SHIFTEIEN: crate::RWRegister<u32>,
23    #[doc = "Timer Interrupt Enable Register"]
24    pub TIMIEN: crate::RWRegister<u32>,
25    _reserved1: [u8; 0x04],
26    #[doc = "Shifter Status DMA Enable"]
27    pub SHIFTSDEN: crate::RWRegister<u32>,
28    _reserved2: [u8; 0x0c],
29    #[doc = "Shifter State Register"]
30    pub SHIFTSTATE: crate::RWRegister<u32>,
31    _reserved3: [u8; 0x3c],
32    #[doc = "Shifter Control N Register"]
33    pub SHIFTCTL: [crate::RWRegister<u32>; 8usize],
34    _reserved4: [u8; 0x60],
35    #[doc = "Shifter Configuration N Register"]
36    pub SHIFTCFG: [crate::RWRegister<u32>; 8usize],
37    _reserved5: [u8; 0xe0],
38    #[doc = "Shifter Buffer N Register"]
39    pub SHIFTBUF: [crate::RWRegister<u32>; 8usize],
40    _reserved6: [u8; 0x60],
41    #[doc = "Shifter Buffer N Bit Swapped Register"]
42    pub SHIFTBUFBIS: [crate::RWRegister<u32>; 8usize],
43    _reserved7: [u8; 0x60],
44    #[doc = "Shifter Buffer N Byte Swapped Register"]
45    pub SHIFTBUFBYS: [crate::RWRegister<u32>; 8usize],
46    _reserved8: [u8; 0x60],
47    #[doc = "Shifter Buffer N Bit Byte Swapped Register"]
48    pub SHIFTBUFBBS: [crate::RWRegister<u32>; 8usize],
49    _reserved9: [u8; 0x60],
50    #[doc = "Timer Control N Register"]
51    pub TIMCTL: [crate::RWRegister<u32>; 8usize],
52    _reserved10: [u8; 0x60],
53    #[doc = "Timer Configuration N Register"]
54    pub TIMCFG: [crate::RWRegister<u32>; 8usize],
55    _reserved11: [u8; 0x60],
56    #[doc = "Timer Compare N Register"]
57    pub TIMCMP: [crate::RWRegister<u32>; 8usize],
58    _reserved12: [u8; 0x0160],
59    #[doc = "Shifter Buffer N Nibble Byte Swapped Register"]
60    pub SHIFTBUFNBS: [crate::RWRegister<u32>; 8usize],
61    _reserved13: [u8; 0x60],
62    #[doc = "Shifter Buffer N Half Word Swapped Register"]
63    pub SHIFTBUFHWS: [crate::RWRegister<u32>; 8usize],
64    _reserved14: [u8; 0x60],
65    #[doc = "Shifter Buffer N Nibble Swapped Register"]
66    pub SHIFTBUFNIS: [crate::RWRegister<u32>; 8usize],
67}
68#[doc = "Version ID Register"]
69pub mod VERID {
70    #[doc = "Feature Specification Number"]
71    pub mod FEATURE {
72        pub const offset: u32 = 0;
73        pub const mask: u32 = 0xffff << offset;
74        pub mod R {}
75        pub mod W {}
76        pub mod RW {
77            #[doc = "Standard features implemented."]
78            pub const FEATURE_0: u32 = 0;
79            #[doc = "Supports state, logic and parallel modes."]
80            pub const FEATURE_1: u32 = 0x01;
81        }
82    }
83    #[doc = "Minor Version Number"]
84    pub mod MINOR {
85        pub const offset: u32 = 16;
86        pub const mask: u32 = 0xff << offset;
87        pub mod R {}
88        pub mod W {}
89        pub mod RW {}
90    }
91    #[doc = "Major Version Number"]
92    pub mod MAJOR {
93        pub const offset: u32 = 24;
94        pub const mask: u32 = 0xff << offset;
95        pub mod R {}
96        pub mod W {}
97        pub mod RW {}
98    }
99}
100#[doc = "Parameter Register"]
101pub mod PARAM {
102    #[doc = "Shifter Number"]
103    pub mod SHIFTER {
104        pub const offset: u32 = 0;
105        pub const mask: u32 = 0xff << offset;
106        pub mod R {}
107        pub mod W {}
108        pub mod RW {}
109    }
110    #[doc = "Timer Number"]
111    pub mod TIMER {
112        pub const offset: u32 = 8;
113        pub const mask: u32 = 0xff << offset;
114        pub mod R {}
115        pub mod W {}
116        pub mod RW {}
117    }
118    #[doc = "Pin Number"]
119    pub mod PIN {
120        pub const offset: u32 = 16;
121        pub const mask: u32 = 0xff << offset;
122        pub mod R {}
123        pub mod W {}
124        pub mod RW {}
125    }
126    #[doc = "Trigger Number"]
127    pub mod TRIGGER {
128        pub const offset: u32 = 24;
129        pub const mask: u32 = 0xff << offset;
130        pub mod R {}
131        pub mod W {}
132        pub mod RW {}
133    }
134}
135#[doc = "FlexIO Control Register"]
136pub mod CTRL {
137    #[doc = "FlexIO Enable"]
138    pub mod FLEXEN {
139        pub const offset: u32 = 0;
140        pub const mask: u32 = 0x01 << offset;
141        pub mod R {}
142        pub mod W {}
143        pub mod RW {
144            #[doc = "FlexIO module is disabled."]
145            pub const FLEXEN_0: u32 = 0;
146            #[doc = "FlexIO module is enabled."]
147            pub const FLEXEN_1: u32 = 0x01;
148        }
149    }
150    #[doc = "Software Reset"]
151    pub mod SWRST {
152        pub const offset: u32 = 1;
153        pub const mask: u32 = 0x01 << offset;
154        pub mod R {}
155        pub mod W {}
156        pub mod RW {
157            #[doc = "Software reset is disabled"]
158            pub const SWRST_0: u32 = 0;
159            #[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
160            pub const SWRST_1: u32 = 0x01;
161        }
162    }
163    #[doc = "Fast Access"]
164    pub mod FASTACC {
165        pub const offset: u32 = 2;
166        pub const mask: u32 = 0x01 << offset;
167        pub mod R {}
168        pub mod W {}
169        pub mod RW {
170            #[doc = "Configures for normal register accesses to FlexIO"]
171            pub const FASTACC_0: u32 = 0;
172            #[doc = "Configures for fast register accesses to FlexIO"]
173            pub const FASTACC_1: u32 = 0x01;
174        }
175    }
176    #[doc = "Debug Enable"]
177    pub mod DBGE {
178        pub const offset: u32 = 30;
179        pub const mask: u32 = 0x01 << offset;
180        pub mod R {}
181        pub mod W {}
182        pub mod RW {
183            #[doc = "FlexIO is disabled in debug modes."]
184            pub const DBGE_0: u32 = 0;
185            #[doc = "FlexIO is enabled in debug modes"]
186            pub const DBGE_1: u32 = 0x01;
187        }
188    }
189    #[doc = "Doze Enable"]
190    pub mod DOZEN {
191        pub const offset: u32 = 31;
192        pub const mask: u32 = 0x01 << offset;
193        pub mod R {}
194        pub mod W {}
195        pub mod RW {
196            #[doc = "FlexIO enabled in Doze modes."]
197            pub const DOZEN_0: u32 = 0;
198            #[doc = "FlexIO disabled in Doze modes."]
199            pub const DOZEN_1: u32 = 0x01;
200        }
201    }
202}
203#[doc = "Pin State Register"]
204pub mod PIN {
205    #[doc = "Pin Data Input"]
206    pub mod PDI {
207        pub const offset: u32 = 0;
208        pub const mask: u32 = 0xffff_ffff << offset;
209        pub mod R {}
210        pub mod W {}
211        pub mod RW {}
212    }
213}
214#[doc = "Shifter Status Register"]
215pub mod SHIFTSTAT {
216    #[doc = "Shifter Status Flag"]
217    pub mod SSF {
218        pub const offset: u32 = 0;
219        pub const mask: u32 = 0xff << offset;
220        pub mod R {}
221        pub mod W {}
222        pub mod RW {}
223    }
224}
225#[doc = "Shifter Error Register"]
226pub mod SHIFTERR {
227    #[doc = "Shifter Error Flags"]
228    pub mod SEF {
229        pub const offset: u32 = 0;
230        pub const mask: u32 = 0xff << offset;
231        pub mod R {}
232        pub mod W {}
233        pub mod RW {}
234    }
235}
236#[doc = "Timer Status Register"]
237pub mod TIMSTAT {
238    #[doc = "Timer Status Flags"]
239    pub mod TSF {
240        pub const offset: u32 = 0;
241        pub const mask: u32 = 0xff << offset;
242        pub mod R {}
243        pub mod W {}
244        pub mod RW {}
245    }
246}
247#[doc = "Shifter Status Interrupt Enable"]
248pub mod SHIFTSIEN {
249    #[doc = "Shifter Status Interrupt Enable"]
250    pub mod SSIE {
251        pub const offset: u32 = 0;
252        pub const mask: u32 = 0xff << offset;
253        pub mod R {}
254        pub mod W {}
255        pub mod RW {}
256    }
257}
258#[doc = "Shifter Error Interrupt Enable"]
259pub mod SHIFTEIEN {
260    #[doc = "Shifter Error Interrupt Enable"]
261    pub mod SEIE {
262        pub const offset: u32 = 0;
263        pub const mask: u32 = 0xff << offset;
264        pub mod R {}
265        pub mod W {}
266        pub mod RW {}
267    }
268}
269#[doc = "Timer Interrupt Enable Register"]
270pub mod TIMIEN {
271    #[doc = "Timer Status Interrupt Enable"]
272    pub mod TEIE {
273        pub const offset: u32 = 0;
274        pub const mask: u32 = 0xff << offset;
275        pub mod R {}
276        pub mod W {}
277        pub mod RW {}
278    }
279}
280#[doc = "Shifter Status DMA Enable"]
281pub mod SHIFTSDEN {
282    #[doc = "Shifter Status DMA Enable"]
283    pub mod SSDE {
284        pub const offset: u32 = 0;
285        pub const mask: u32 = 0xff << offset;
286        pub mod R {}
287        pub mod W {}
288        pub mod RW {}
289    }
290}
291#[doc = "Shifter State Register"]
292pub mod SHIFTSTATE {
293    #[doc = "Current State Pointer"]
294    pub mod STATE {
295        pub const offset: u32 = 0;
296        pub const mask: u32 = 0x07 << offset;
297        pub mod R {}
298        pub mod W {}
299        pub mod RW {}
300    }
301}
302#[doc = "Shifter Control N Register"]
303pub mod SHIFTCTL {
304    #[doc = "Shifter Mode"]
305    pub mod SMOD {
306        pub const offset: u32 = 0;
307        pub const mask: u32 = 0x07 << offset;
308        pub mod R {}
309        pub mod W {}
310        pub mod RW {
311            #[doc = "Disabled."]
312            pub const SMOD_0: u32 = 0;
313            #[doc = "Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer."]
314            pub const SMOD_1: u32 = 0x01;
315            #[doc = "Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer."]
316            pub const SMOD_2: u32 = 0x02;
317            #[doc = "Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer."]
318            pub const SMOD_4: u32 = 0x04;
319            #[doc = "Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents."]
320            pub const SMOD_5: u32 = 0x05;
321            #[doc = "State mode. SHIFTBUF contents are used for storing programmable state attributes."]
322            pub const SMOD_6: u32 = 0x06;
323            #[doc = "Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table."]
324            pub const SMOD_7: u32 = 0x07;
325        }
326    }
327    #[doc = "Shifter Pin Polarity"]
328    pub mod PINPOL {
329        pub const offset: u32 = 7;
330        pub const mask: u32 = 0x01 << offset;
331        pub mod R {}
332        pub mod W {}
333        pub mod RW {
334            #[doc = "Pin is active high"]
335            pub const PINPOL_0: u32 = 0;
336            #[doc = "Pin is active low"]
337            pub const PINPOL_1: u32 = 0x01;
338        }
339    }
340    #[doc = "Shifter Pin Select"]
341    pub mod PINSEL {
342        pub const offset: u32 = 8;
343        pub const mask: u32 = 0x1f << offset;
344        pub mod R {}
345        pub mod W {}
346        pub mod RW {}
347    }
348    #[doc = "Shifter Pin Configuration"]
349    pub mod PINCFG {
350        pub const offset: u32 = 16;
351        pub const mask: u32 = 0x03 << offset;
352        pub mod R {}
353        pub mod W {}
354        pub mod RW {
355            #[doc = "Shifter pin output disabled"]
356            pub const PINCFG_0: u32 = 0;
357            #[doc = "Shifter pin open drain or bidirectional output enable"]
358            pub const PINCFG_1: u32 = 0x01;
359            #[doc = "Shifter pin bidirectional output data"]
360            pub const PINCFG_2: u32 = 0x02;
361            #[doc = "Shifter pin output"]
362            pub const PINCFG_3: u32 = 0x03;
363        }
364    }
365    #[doc = "Timer Polarity"]
366    pub mod TIMPOL {
367        pub const offset: u32 = 23;
368        pub const mask: u32 = 0x01 << offset;
369        pub mod R {}
370        pub mod W {}
371        pub mod RW {
372            #[doc = "Shift on posedge of Shift clock"]
373            pub const TIMPOL_0: u32 = 0;
374            #[doc = "Shift on negedge of Shift clock"]
375            pub const TIMPOL_1: u32 = 0x01;
376        }
377    }
378    #[doc = "Timer Select"]
379    pub mod TIMSEL {
380        pub const offset: u32 = 24;
381        pub const mask: u32 = 0x07 << offset;
382        pub mod R {}
383        pub mod W {}
384        pub mod RW {}
385    }
386}
387#[doc = "Shifter Configuration N Register"]
388pub mod SHIFTCFG {
389    #[doc = "Shifter Start bit"]
390    pub mod SSTART {
391        pub const offset: u32 = 0;
392        pub const mask: u32 = 0x03 << offset;
393        pub mod R {}
394        pub mod W {}
395        pub mod RW {
396            #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable"]
397            pub const SSTART_0: u32 = 0;
398            #[doc = "Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift"]
399            pub const SSTART_1: u32 = 0x01;
400            #[doc = "Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0"]
401            pub const SSTART_2: u32 = 0x02;
402            #[doc = "Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1"]
403            pub const SSTART_3: u32 = 0x03;
404        }
405    }
406    #[doc = "Shifter Stop bit"]
407    pub mod SSTOP {
408        pub const offset: u32 = 4;
409        pub const mask: u32 = 0x03 << offset;
410        pub mod R {}
411        pub mod W {}
412        pub mod RW {
413            #[doc = "Stop bit disabled for transmitter/receiver/match store"]
414            pub const SSTOP_0: u32 = 0;
415            #[doc = "Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0"]
416            pub const SSTOP_2: u32 = 0x02;
417            #[doc = "Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1"]
418            pub const SSTOP_3: u32 = 0x03;
419        }
420    }
421    #[doc = "Input Source"]
422    pub mod INSRC {
423        pub const offset: u32 = 8;
424        pub const mask: u32 = 0x01 << offset;
425        pub mod R {}
426        pub mod W {}
427        pub mod RW {
428            #[doc = "Pin"]
429            pub const INSRC_0: u32 = 0;
430            #[doc = "Shifter N+1 Output"]
431            pub const INSRC_1: u32 = 0x01;
432        }
433    }
434    #[doc = "Parallel Width"]
435    pub mod PWIDTH {
436        pub const offset: u32 = 16;
437        pub const mask: u32 = 0x1f << offset;
438        pub mod R {}
439        pub mod W {}
440        pub mod RW {}
441    }
442}
443#[doc = "Shifter Buffer N Register"]
444pub mod SHIFTBUF {
445    #[doc = "Shift Buffer"]
446    pub mod SHIFTBUF {
447        pub const offset: u32 = 0;
448        pub const mask: u32 = 0xffff_ffff << offset;
449        pub mod R {}
450        pub mod W {}
451        pub mod RW {}
452    }
453}
454#[doc = "Shifter Buffer N Bit Swapped Register"]
455pub mod SHIFTBUFBIS {
456    #[doc = "Shift Buffer"]
457    pub mod SHIFTBUFBIS {
458        pub const offset: u32 = 0;
459        pub const mask: u32 = 0xffff_ffff << offset;
460        pub mod R {}
461        pub mod W {}
462        pub mod RW {}
463    }
464}
465#[doc = "Shifter Buffer N Byte Swapped Register"]
466pub mod SHIFTBUFBYS {
467    #[doc = "Shift Buffer"]
468    pub mod SHIFTBUFBYS {
469        pub const offset: u32 = 0;
470        pub const mask: u32 = 0xffff_ffff << offset;
471        pub mod R {}
472        pub mod W {}
473        pub mod RW {}
474    }
475}
476#[doc = "Shifter Buffer N Bit Byte Swapped Register"]
477pub mod SHIFTBUFBBS {
478    #[doc = "Shift Buffer"]
479    pub mod SHIFTBUFBBS {
480        pub const offset: u32 = 0;
481        pub const mask: u32 = 0xffff_ffff << offset;
482        pub mod R {}
483        pub mod W {}
484        pub mod RW {}
485    }
486}
487#[doc = "Timer Control N Register"]
488pub mod TIMCTL {
489    #[doc = "Timer Mode"]
490    pub mod TIMOD {
491        pub const offset: u32 = 0;
492        pub const mask: u32 = 0x03 << offset;
493        pub mod R {}
494        pub mod W {}
495        pub mod RW {
496            #[doc = "Timer Disabled."]
497            pub const TIMOD_0: u32 = 0;
498            #[doc = "Dual 8-bit counters baud mode."]
499            pub const TIMOD_1: u32 = 0x01;
500            #[doc = "Dual 8-bit counters PWM high mode."]
501            pub const TIMOD_2: u32 = 0x02;
502            #[doc = "Single 16-bit counter mode."]
503            pub const TIMOD_3: u32 = 0x03;
504        }
505    }
506    #[doc = "Timer Pin Polarity"]
507    pub mod PINPOL {
508        pub const offset: u32 = 7;
509        pub const mask: u32 = 0x01 << offset;
510        pub mod R {}
511        pub mod W {}
512        pub mod RW {
513            #[doc = "Pin is active high"]
514            pub const PINPOL_0: u32 = 0;
515            #[doc = "Pin is active low"]
516            pub const PINPOL_1: u32 = 0x01;
517        }
518    }
519    #[doc = "Timer Pin Select"]
520    pub mod PINSEL {
521        pub const offset: u32 = 8;
522        pub const mask: u32 = 0x1f << offset;
523        pub mod R {}
524        pub mod W {}
525        pub mod RW {}
526    }
527    #[doc = "Timer Pin Configuration"]
528    pub mod PINCFG {
529        pub const offset: u32 = 16;
530        pub const mask: u32 = 0x03 << offset;
531        pub mod R {}
532        pub mod W {}
533        pub mod RW {
534            #[doc = "Timer pin output disabled"]
535            pub const PINCFG_0: u32 = 0;
536            #[doc = "Timer pin open drain or bidirectional output enable"]
537            pub const PINCFG_1: u32 = 0x01;
538            #[doc = "Timer pin bidirectional output data"]
539            pub const PINCFG_2: u32 = 0x02;
540            #[doc = "Timer pin output"]
541            pub const PINCFG_3: u32 = 0x03;
542        }
543    }
544    #[doc = "Trigger Source"]
545    pub mod TRGSRC {
546        pub const offset: u32 = 22;
547        pub const mask: u32 = 0x01 << offset;
548        pub mod R {}
549        pub mod W {}
550        pub mod RW {
551            #[doc = "External trigger selected"]
552            pub const TRGSRC_0: u32 = 0;
553            #[doc = "Internal trigger selected"]
554            pub const TRGSRC_1: u32 = 0x01;
555        }
556    }
557    #[doc = "Trigger Polarity"]
558    pub mod TRGPOL {
559        pub const offset: u32 = 23;
560        pub const mask: u32 = 0x01 << offset;
561        pub mod R {}
562        pub mod W {}
563        pub mod RW {
564            #[doc = "Trigger active high"]
565            pub const TRGPOL_0: u32 = 0;
566            #[doc = "Trigger active low"]
567            pub const TRGPOL_1: u32 = 0x01;
568        }
569    }
570    #[doc = "Trigger Select"]
571    pub mod TRGSEL {
572        pub const offset: u32 = 24;
573        pub const mask: u32 = 0x3f << offset;
574        pub mod R {}
575        pub mod W {}
576        pub mod RW {}
577    }
578}
579#[doc = "Timer Configuration N Register"]
580pub mod TIMCFG {
581    #[doc = "Timer Start Bit"]
582    pub mod TSTART {
583        pub const offset: u32 = 1;
584        pub const mask: u32 = 0x01 << offset;
585        pub mod R {}
586        pub mod W {}
587        pub mod RW {
588            #[doc = "Start bit disabled"]
589            pub const TSTART_0: u32 = 0;
590            #[doc = "Start bit enabled"]
591            pub const TSTART_1: u32 = 0x01;
592        }
593    }
594    #[doc = "Timer Stop Bit"]
595    pub mod TSTOP {
596        pub const offset: u32 = 4;
597        pub const mask: u32 = 0x03 << offset;
598        pub mod R {}
599        pub mod W {}
600        pub mod RW {
601            #[doc = "Stop bit disabled"]
602            pub const TSTOP_0: u32 = 0;
603            #[doc = "Stop bit is enabled on timer compare"]
604            pub const TSTOP_1: u32 = 0x01;
605            #[doc = "Stop bit is enabled on timer disable"]
606            pub const TSTOP_2: u32 = 0x02;
607            #[doc = "Stop bit is enabled on timer compare and timer disable"]
608            pub const TSTOP_3: u32 = 0x03;
609        }
610    }
611    #[doc = "Timer Enable"]
612    pub mod TIMENA {
613        pub const offset: u32 = 8;
614        pub const mask: u32 = 0x07 << offset;
615        pub mod R {}
616        pub mod W {}
617        pub mod RW {
618            #[doc = "Timer always enabled"]
619            pub const TIMENA_0: u32 = 0;
620            #[doc = "Timer enabled on Timer N-1 enable"]
621            pub const TIMENA_1: u32 = 0x01;
622            #[doc = "Timer enabled on Trigger high"]
623            pub const TIMENA_2: u32 = 0x02;
624            #[doc = "Timer enabled on Trigger high and Pin high"]
625            pub const TIMENA_3: u32 = 0x03;
626            #[doc = "Timer enabled on Pin rising edge"]
627            pub const TIMENA_4: u32 = 0x04;
628            #[doc = "Timer enabled on Pin rising edge and Trigger high"]
629            pub const TIMENA_5: u32 = 0x05;
630            #[doc = "Timer enabled on Trigger rising edge"]
631            pub const TIMENA_6: u32 = 0x06;
632            #[doc = "Timer enabled on Trigger rising or falling edge"]
633            pub const TIMENA_7: u32 = 0x07;
634        }
635    }
636    #[doc = "Timer Disable"]
637    pub mod TIMDIS {
638        pub const offset: u32 = 12;
639        pub const mask: u32 = 0x07 << offset;
640        pub mod R {}
641        pub mod W {}
642        pub mod RW {
643            #[doc = "Timer never disabled"]
644            pub const TIMDIS_0: u32 = 0;
645            #[doc = "Timer disabled on Timer N-1 disable"]
646            pub const TIMDIS_1: u32 = 0x01;
647            #[doc = "Timer disabled on Timer compare (upper 8-bits match and decrement)"]
648            pub const TIMDIS_2: u32 = 0x02;
649            #[doc = "Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low"]
650            pub const TIMDIS_3: u32 = 0x03;
651            #[doc = "Timer disabled on Pin rising or falling edge"]
652            pub const TIMDIS_4: u32 = 0x04;
653            #[doc = "Timer disabled on Pin rising or falling edge provided Trigger is high"]
654            pub const TIMDIS_5: u32 = 0x05;
655            #[doc = "Timer disabled on Trigger falling edge"]
656            pub const TIMDIS_6: u32 = 0x06;
657        }
658    }
659    #[doc = "Timer Reset"]
660    pub mod TIMRST {
661        pub const offset: u32 = 16;
662        pub const mask: u32 = 0x07 << offset;
663        pub mod R {}
664        pub mod W {}
665        pub mod RW {
666            #[doc = "Timer never reset"]
667            pub const TIMRST_0: u32 = 0;
668            #[doc = "Timer reset on Timer Pin equal to Timer Output"]
669            pub const TIMRST_2: u32 = 0x02;
670            #[doc = "Timer reset on Timer Trigger equal to Timer Output"]
671            pub const TIMRST_3: u32 = 0x03;
672            #[doc = "Timer reset on Timer Pin rising edge"]
673            pub const TIMRST_4: u32 = 0x04;
674            #[doc = "Timer reset on Trigger rising edge"]
675            pub const TIMRST_6: u32 = 0x06;
676            #[doc = "Timer reset on Trigger rising or falling edge"]
677            pub const TIMRST_7: u32 = 0x07;
678        }
679    }
680    #[doc = "Timer Decrement"]
681    pub mod TIMDEC {
682        pub const offset: u32 = 20;
683        pub const mask: u32 = 0x03 << offset;
684        pub mod R {}
685        pub mod W {}
686        pub mod RW {
687            #[doc = "Decrement counter on FlexIO clock, Shift clock equals Timer output."]
688            pub const TIMDEC_0: u32 = 0;
689            #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Timer output."]
690            pub const TIMDEC_1: u32 = 0x01;
691            #[doc = "Decrement counter on Pin input (both edges), Shift clock equals Pin input."]
692            pub const TIMDEC_2: u32 = 0x02;
693            #[doc = "Decrement counter on Trigger input (both edges), Shift clock equals Trigger input."]
694            pub const TIMDEC_3: u32 = 0x03;
695        }
696    }
697    #[doc = "Timer Output"]
698    pub mod TIMOUT {
699        pub const offset: u32 = 24;
700        pub const mask: u32 = 0x03 << offset;
701        pub mod R {}
702        pub mod W {}
703        pub mod RW {
704            #[doc = "Timer output is logic one when enabled and is not affected by timer reset"]
705            pub const TIMOUT_0: u32 = 0;
706            #[doc = "Timer output is logic zero when enabled and is not affected by timer reset"]
707            pub const TIMOUT_1: u32 = 0x01;
708            #[doc = "Timer output is logic one when enabled and on timer reset"]
709            pub const TIMOUT_2: u32 = 0x02;
710            #[doc = "Timer output is logic zero when enabled and on timer reset"]
711            pub const TIMOUT_3: u32 = 0x03;
712        }
713    }
714}
715#[doc = "Timer Compare N Register"]
716pub mod TIMCMP {
717    #[doc = "Timer Compare Value"]
718    pub mod CMP {
719        pub const offset: u32 = 0;
720        pub const mask: u32 = 0xffff << offset;
721        pub mod R {}
722        pub mod W {}
723        pub mod RW {}
724    }
725}
726#[doc = "Shifter Buffer N Nibble Byte Swapped Register"]
727pub mod SHIFTBUFNBS {
728    #[doc = "Shift Buffer"]
729    pub mod SHIFTBUFNBS {
730        pub const offset: u32 = 0;
731        pub const mask: u32 = 0xffff_ffff << offset;
732        pub mod R {}
733        pub mod W {}
734        pub mod RW {}
735    }
736}
737#[doc = "Shifter Buffer N Half Word Swapped Register"]
738pub mod SHIFTBUFHWS {
739    #[doc = "Shift Buffer"]
740    pub mod SHIFTBUFHWS {
741        pub const offset: u32 = 0;
742        pub const mask: u32 = 0xffff_ffff << offset;
743        pub mod R {}
744        pub mod W {}
745        pub mod RW {}
746    }
747}
748#[doc = "Shifter Buffer N Nibble Swapped Register"]
749pub mod SHIFTBUFNIS {
750    #[doc = "Shift Buffer"]
751    pub mod SHIFTBUFNIS {
752        pub const offset: u32 = 0;
753        pub const mask: u32 = 0xffff_ffff << offset;
754        pub mod R {}
755        pub mod W {}
756        pub mod RW {}
757    }
758}
imxrt_ral/blocks/imxrt1011/flexio.rs

imxrt_ral/blocks/imxrt1011/
flexio.rs
