rp2040_pac/clocks/
wake_en1.rs

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1#[doc = "Register `WAKE_EN1` reader"]
2pub type R = crate::R<WAKE_EN1_SPEC>;
3#[doc = "Register `WAKE_EN1` writer"]
4pub type W = crate::W<WAKE_EN1_SPEC>;
5#[doc = "Field `clk_sys_sram4` reader - "]
6pub type CLK_SYS_SRAM4_R = crate::BitReader;
7#[doc = "Field `clk_sys_sram4` writer - "]
8pub type CLK_SYS_SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `clk_sys_sram5` reader - "]
10pub type CLK_SYS_SRAM5_R = crate::BitReader;
11#[doc = "Field `clk_sys_sram5` writer - "]
12pub type CLK_SYS_SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `clk_sys_syscfg` reader - "]
14pub type CLK_SYS_SYSCFG_R = crate::BitReader;
15#[doc = "Field `clk_sys_syscfg` writer - "]
16pub type CLK_SYS_SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `clk_sys_sysinfo` reader - "]
18pub type CLK_SYS_SYSINFO_R = crate::BitReader;
19#[doc = "Field `clk_sys_sysinfo` writer - "]
20pub type CLK_SYS_SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `clk_sys_tbman` reader - "]
22pub type CLK_SYS_TBMAN_R = crate::BitReader;
23#[doc = "Field `clk_sys_tbman` writer - "]
24pub type CLK_SYS_TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `clk_sys_timer` reader - "]
26pub type CLK_SYS_TIMER_R = crate::BitReader;
27#[doc = "Field `clk_sys_timer` writer - "]
28pub type CLK_SYS_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `clk_peri_uart0` reader - "]
30pub type CLK_PERI_UART0_R = crate::BitReader;
31#[doc = "Field `clk_peri_uart0` writer - "]
32pub type CLK_PERI_UART0_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `clk_sys_uart0` reader - "]
34pub type CLK_SYS_UART0_R = crate::BitReader;
35#[doc = "Field `clk_sys_uart0` writer - "]
36pub type CLK_SYS_UART0_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `clk_peri_uart1` reader - "]
38pub type CLK_PERI_UART1_R = crate::BitReader;
39#[doc = "Field `clk_peri_uart1` writer - "]
40pub type CLK_PERI_UART1_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `clk_sys_uart1` reader - "]
42pub type CLK_SYS_UART1_R = crate::BitReader;
43#[doc = "Field `clk_sys_uart1` writer - "]
44pub type CLK_SYS_UART1_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `clk_sys_usbctrl` reader - "]
46pub type CLK_SYS_USBCTRL_R = crate::BitReader;
47#[doc = "Field `clk_sys_usbctrl` writer - "]
48pub type CLK_SYS_USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `clk_usb_usbctrl` reader - "]
50pub type CLK_USB_USBCTRL_R = crate::BitReader;
51#[doc = "Field `clk_usb_usbctrl` writer - "]
52pub type CLK_USB_USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `clk_sys_watchdog` reader - "]
54pub type CLK_SYS_WATCHDOG_R = crate::BitReader;
55#[doc = "Field `clk_sys_watchdog` writer - "]
56pub type CLK_SYS_WATCHDOG_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `clk_sys_xip` reader - "]
58pub type CLK_SYS_XIP_R = crate::BitReader;
59#[doc = "Field `clk_sys_xip` writer - "]
60pub type CLK_SYS_XIP_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `clk_sys_xosc` reader - "]
62pub type CLK_SYS_XOSC_R = crate::BitReader;
63#[doc = "Field `clk_sys_xosc` writer - "]
64pub type CLK_SYS_XOSC_W<'a, REG> = crate::BitWriter<'a, REG>;
65impl R {
66    #[doc = "Bit 0"]
67    #[inline(always)]
68    pub fn clk_sys_sram4(&self) -> CLK_SYS_SRAM4_R {
69        CLK_SYS_SRAM4_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1"]
72    #[inline(always)]
73    pub fn clk_sys_sram5(&self) -> CLK_SYS_SRAM5_R {
74        CLK_SYS_SRAM5_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2"]
77    #[inline(always)]
78    pub fn clk_sys_syscfg(&self) -> CLK_SYS_SYSCFG_R {
79        CLK_SYS_SYSCFG_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3"]
82    #[inline(always)]
83    pub fn clk_sys_sysinfo(&self) -> CLK_SYS_SYSINFO_R {
84        CLK_SYS_SYSINFO_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4"]
87    #[inline(always)]
88    pub fn clk_sys_tbman(&self) -> CLK_SYS_TBMAN_R {
89        CLK_SYS_TBMAN_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5"]
92    #[inline(always)]
93    pub fn clk_sys_timer(&self) -> CLK_SYS_TIMER_R {
94        CLK_SYS_TIMER_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 6"]
97    #[inline(always)]
98    pub fn clk_peri_uart0(&self) -> CLK_PERI_UART0_R {
99        CLK_PERI_UART0_R::new(((self.bits >> 6) & 1) != 0)
100    }
101    #[doc = "Bit 7"]
102    #[inline(always)]
103    pub fn clk_sys_uart0(&self) -> CLK_SYS_UART0_R {
104        CLK_SYS_UART0_R::new(((self.bits >> 7) & 1) != 0)
105    }
106    #[doc = "Bit 8"]
107    #[inline(always)]
108    pub fn clk_peri_uart1(&self) -> CLK_PERI_UART1_R {
109        CLK_PERI_UART1_R::new(((self.bits >> 8) & 1) != 0)
110    }
111    #[doc = "Bit 9"]
112    #[inline(always)]
113    pub fn clk_sys_uart1(&self) -> CLK_SYS_UART1_R {
114        CLK_SYS_UART1_R::new(((self.bits >> 9) & 1) != 0)
115    }
116    #[doc = "Bit 10"]
117    #[inline(always)]
118    pub fn clk_sys_usbctrl(&self) -> CLK_SYS_USBCTRL_R {
119        CLK_SYS_USBCTRL_R::new(((self.bits >> 10) & 1) != 0)
120    }
121    #[doc = "Bit 11"]
122    #[inline(always)]
123    pub fn clk_usb_usbctrl(&self) -> CLK_USB_USBCTRL_R {
124        CLK_USB_USBCTRL_R::new(((self.bits >> 11) & 1) != 0)
125    }
126    #[doc = "Bit 12"]
127    #[inline(always)]
128    pub fn clk_sys_watchdog(&self) -> CLK_SYS_WATCHDOG_R {
129        CLK_SYS_WATCHDOG_R::new(((self.bits >> 12) & 1) != 0)
130    }
131    #[doc = "Bit 13"]
132    #[inline(always)]
133    pub fn clk_sys_xip(&self) -> CLK_SYS_XIP_R {
134        CLK_SYS_XIP_R::new(((self.bits >> 13) & 1) != 0)
135    }
136    #[doc = "Bit 14"]
137    #[inline(always)]
138    pub fn clk_sys_xosc(&self) -> CLK_SYS_XOSC_R {
139        CLK_SYS_XOSC_R::new(((self.bits >> 14) & 1) != 0)
140    }
141}
142impl W {
143    #[doc = "Bit 0"]
144    #[inline(always)]
145    #[must_use]
146    pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W<WAKE_EN1_SPEC> {
147        CLK_SYS_SRAM4_W::new(self, 0)
148    }
149    #[doc = "Bit 1"]
150    #[inline(always)]
151    #[must_use]
152    pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W<WAKE_EN1_SPEC> {
153        CLK_SYS_SRAM5_W::new(self, 1)
154    }
155    #[doc = "Bit 2"]
156    #[inline(always)]
157    #[must_use]
158    pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W<WAKE_EN1_SPEC> {
159        CLK_SYS_SYSCFG_W::new(self, 2)
160    }
161    #[doc = "Bit 3"]
162    #[inline(always)]
163    #[must_use]
164    pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W<WAKE_EN1_SPEC> {
165        CLK_SYS_SYSINFO_W::new(self, 3)
166    }
167    #[doc = "Bit 4"]
168    #[inline(always)]
169    #[must_use]
170    pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W<WAKE_EN1_SPEC> {
171        CLK_SYS_TBMAN_W::new(self, 4)
172    }
173    #[doc = "Bit 5"]
174    #[inline(always)]
175    #[must_use]
176    pub fn clk_sys_timer(&mut self) -> CLK_SYS_TIMER_W<WAKE_EN1_SPEC> {
177        CLK_SYS_TIMER_W::new(self, 5)
178    }
179    #[doc = "Bit 6"]
180    #[inline(always)]
181    #[must_use]
182    pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W<WAKE_EN1_SPEC> {
183        CLK_PERI_UART0_W::new(self, 6)
184    }
185    #[doc = "Bit 7"]
186    #[inline(always)]
187    #[must_use]
188    pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W<WAKE_EN1_SPEC> {
189        CLK_SYS_UART0_W::new(self, 7)
190    }
191    #[doc = "Bit 8"]
192    #[inline(always)]
193    #[must_use]
194    pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W<WAKE_EN1_SPEC> {
195        CLK_PERI_UART1_W::new(self, 8)
196    }
197    #[doc = "Bit 9"]
198    #[inline(always)]
199    #[must_use]
200    pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W<WAKE_EN1_SPEC> {
201        CLK_SYS_UART1_W::new(self, 9)
202    }
203    #[doc = "Bit 10"]
204    #[inline(always)]
205    #[must_use]
206    pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W<WAKE_EN1_SPEC> {
207        CLK_SYS_USBCTRL_W::new(self, 10)
208    }
209    #[doc = "Bit 11"]
210    #[inline(always)]
211    #[must_use]
212    pub fn clk_usb_usbctrl(&mut self) -> CLK_USB_USBCTRL_W<WAKE_EN1_SPEC> {
213        CLK_USB_USBCTRL_W::new(self, 11)
214    }
215    #[doc = "Bit 12"]
216    #[inline(always)]
217    #[must_use]
218    pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W<WAKE_EN1_SPEC> {
219        CLK_SYS_WATCHDOG_W::new(self, 12)
220    }
221    #[doc = "Bit 13"]
222    #[inline(always)]
223    #[must_use]
224    pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W<WAKE_EN1_SPEC> {
225        CLK_SYS_XIP_W::new(self, 13)
226    }
227    #[doc = "Bit 14"]
228    #[inline(always)]
229    #[must_use]
230    pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W<WAKE_EN1_SPEC> {
231        CLK_SYS_XOSC_W::new(self, 14)
232    }
233    #[doc = r" Writes raw bits to the register."]
234    #[doc = r""]
235    #[doc = r" # Safety"]
236    #[doc = r""]
237    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
238    #[inline(always)]
239    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
240        self.bits = bits;
241        self
242    }
243}
244#[doc = "enable clock in wake mode  
245
246You can [`read`](crate::generic::Reg::read) this register and get [`wake_en1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
247pub struct WAKE_EN1_SPEC;
248impl crate::RegisterSpec for WAKE_EN1_SPEC {
249    type Ux = u32;
250}
251#[doc = "`read()` method returns [`wake_en1::R`](R) reader structure"]
252impl crate::Readable for WAKE_EN1_SPEC {}
253#[doc = "`write(|w| ..)` method takes [`wake_en1::W`](W) writer structure"]
254impl crate::Writable for WAKE_EN1_SPEC {
255    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
256    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
257}
258#[doc = "`reset()` method sets WAKE_EN1 to value 0x7fff"]
259impl crate::Resettable for WAKE_EN1_SPEC {
260    const RESET_VALUE: u32 = 0x7fff;
261}
rp2040_pac/clocks/wake_en1.rs

rp2040_pac/clocks/
wake_en1.rs
