rp2040_pac/pio0/sm/
sm_pinctrl.rs

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1#[doc = "Register `SM_PINCTRL` reader"]
2pub type R = crate::R<SM_PINCTRL_SPEC>;
3#[doc = "Register `SM_PINCTRL` writer"]
4pub type W = crate::W<SM_PINCTRL_SPEC>;
5#[doc = "Field `OUT_BASE` reader - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
6pub type OUT_BASE_R = crate::FieldReader;
7#[doc = "Field `OUT_BASE` writer - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
8pub type OUT_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `SET_BASE` reader - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
10pub type SET_BASE_R = crate::FieldReader;
11#[doc = "Field `SET_BASE` writer - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
12pub type SET_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `SIDESET_BASE` reader - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
14pub type SIDESET_BASE_R = crate::FieldReader;
15#[doc = "Field `SIDESET_BASE` writer - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
16pub type SIDESET_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Field `IN_BASE` reader - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
18pub type IN_BASE_R = crate::FieldReader;
19#[doc = "Field `IN_BASE` writer - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
20pub type IN_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
21#[doc = "Field `OUT_COUNT` reader - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
22pub type OUT_COUNT_R = crate::FieldReader;
23#[doc = "Field `OUT_COUNT` writer - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
24pub type OUT_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
25#[doc = "Field `SET_COUNT` reader - The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
26pub type SET_COUNT_R = crate::FieldReader;
27#[doc = "Field `SET_COUNT` writer - The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
28pub type SET_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29#[doc = "Field `SIDESET_COUNT` reader - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
30pub type SIDESET_COUNT_R = crate::FieldReader;
31#[doc = "Field `SIDESET_COUNT` writer - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
32pub type SIDESET_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33impl R {
34    #[doc = "Bits 0:4 - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
35    #[inline(always)]
36    pub fn out_base(&self) -> OUT_BASE_R {
37        OUT_BASE_R::new((self.bits & 0x1f) as u8)
38    }
39    #[doc = "Bits 5:9 - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
40    #[inline(always)]
41    pub fn set_base(&self) -> SET_BASE_R {
42        SET_BASE_R::new(((self.bits >> 5) & 0x1f) as u8)
43    }
44    #[doc = "Bits 10:14 - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
45    #[inline(always)]
46    pub fn sideset_base(&self) -> SIDESET_BASE_R {
47        SIDESET_BASE_R::new(((self.bits >> 10) & 0x1f) as u8)
48    }
49    #[doc = "Bits 15:19 - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
50    #[inline(always)]
51    pub fn in_base(&self) -> IN_BASE_R {
52        IN_BASE_R::new(((self.bits >> 15) & 0x1f) as u8)
53    }
54    #[doc = "Bits 20:25 - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
55    #[inline(always)]
56    pub fn out_count(&self) -> OUT_COUNT_R {
57        OUT_COUNT_R::new(((self.bits >> 20) & 0x3f) as u8)
58    }
59    #[doc = "Bits 26:28 - The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
60    #[inline(always)]
61    pub fn set_count(&self) -> SET_COUNT_R {
62        SET_COUNT_R::new(((self.bits >> 26) & 7) as u8)
63    }
64    #[doc = "Bits 29:31 - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
65    #[inline(always)]
66    pub fn sideset_count(&self) -> SIDESET_COUNT_R {
67        SIDESET_COUNT_R::new(((self.bits >> 29) & 7) as u8)
68    }
69}
70impl W {
71    #[doc = "Bits 0:4 - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
72    #[inline(always)]
73    #[must_use]
74    pub fn out_base(&mut self) -> OUT_BASE_W<SM_PINCTRL_SPEC> {
75        OUT_BASE_W::new(self, 0)
76    }
77    #[doc = "Bits 5:9 - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
78    #[inline(always)]
79    #[must_use]
80    pub fn set_base(&mut self) -> SET_BASE_W<SM_PINCTRL_SPEC> {
81        SET_BASE_W::new(self, 5)
82    }
83    #[doc = "Bits 10:14 - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
84    #[inline(always)]
85    #[must_use]
86    pub fn sideset_base(&mut self) -> SIDESET_BASE_W<SM_PINCTRL_SPEC> {
87        SIDESET_BASE_W::new(self, 10)
88    }
89    #[doc = "Bits 15:19 - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
90    #[inline(always)]
91    #[must_use]
92    pub fn in_base(&mut self) -> IN_BASE_W<SM_PINCTRL_SPEC> {
93        IN_BASE_W::new(self, 15)
94    }
95    #[doc = "Bits 20:25 - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
96    #[inline(always)]
97    #[must_use]
98    pub fn out_count(&mut self) -> OUT_COUNT_W<SM_PINCTRL_SPEC> {
99        OUT_COUNT_W::new(self, 20)
100    }
101    #[doc = "Bits 26:28 - The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
102    #[inline(always)]
103    #[must_use]
104    pub fn set_count(&mut self) -> SET_COUNT_W<SM_PINCTRL_SPEC> {
105        SET_COUNT_W::new(self, 26)
106    }
107    #[doc = "Bits 29:31 - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
108    #[inline(always)]
109    #[must_use]
110    pub fn sideset_count(&mut self) -> SIDESET_COUNT_W<SM_PINCTRL_SPEC> {
111        SIDESET_COUNT_W::new(self, 29)
112    }
113    #[doc = r" Writes raw bits to the register."]
114    #[doc = r""]
115    #[doc = r" # Safety"]
116    #[doc = r""]
117    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
118    #[inline(always)]
119    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
120        self.bits = bits;
121        self
122    }
123}
124#[doc = "State machine pin control  
125
126You can [`read`](crate::generic::Reg::read) this register and get [`sm_pinctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_pinctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
127pub struct SM_PINCTRL_SPEC;
128impl crate::RegisterSpec for SM_PINCTRL_SPEC {
129    type Ux = u32;
130}
131#[doc = "`read()` method returns [`sm_pinctrl::R`](R) reader structure"]
132impl crate::Readable for SM_PINCTRL_SPEC {}
133#[doc = "`write(|w| ..)` method takes [`sm_pinctrl::W`](W) writer structure"]
134impl crate::Writable for SM_PINCTRL_SPEC {
135    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
136    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
137}
138#[doc = "`reset()` method sets SM_PINCTRL to value 0x1400_0000"]
139impl crate::Resettable for SM_PINCTRL_SPEC {
140    const RESET_VALUE: u32 = 0x1400_0000;
141}
rp2040_pac/pio0/sm/sm_pinctrl.rs

rp2040_pac/pio0/sm/
sm_pinctrl.rs
