1#[doc = "Register `IC_ENABLE` reader"]
2pub type R = crate::R<IC_ENABLE_SPEC>;
3#[doc = "Register `IC_ENABLE` writer"]
4pub type W = crate::W<IC_ENABLE_SPEC>;
5#[doc = "Field `ENABLE` reader - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.
6
7 When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
8
9 In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'
10
11 Reset value: 0x0"]
12pub type ENABLE_R = crate::BitReader<ENABLE_A>;
13#[doc = "Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.
14
15 When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
16
17 In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'
18
19 Reset value: 0x0
20
21Value on reset: 0"]
22#[derive(Clone, Copy, Debug, PartialEq, Eq)]
23pub enum ENABLE_A {
24 #[doc = "0: I2C is disabled"]
25 DISABLED = 0,
26 #[doc = "1: I2C is enabled"]
27 ENABLED = 1,
28}
29impl From<ENABLE_A> for bool {
30 #[inline(always)]
31 fn from(variant: ENABLE_A) -> Self {
32 variant as u8 != 0
33 }
34}
35impl ENABLE_R {
36 #[doc = "Get enumerated values variant"]
37 #[inline(always)]
38 pub const fn variant(&self) -> ENABLE_A {
39 match self.bits {
40 false => ENABLE_A::DISABLED,
41 true => ENABLE_A::ENABLED,
42 }
43 }
44 #[doc = "I2C is disabled"]
45 #[inline(always)]
46 pub fn is_disabled(&self) -> bool {
47 *self == ENABLE_A::DISABLED
48 }
49 #[doc = "I2C is enabled"]
50 #[inline(always)]
51 pub fn is_enabled(&self) -> bool {
52 *self == ENABLE_A::ENABLED
53 }
54}
55#[doc = "Field `ENABLE` writer - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.
56
57 When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
58
59 In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'
60
61 Reset value: 0x0"]
62pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ENABLE_A>;
63impl<'a, REG> ENABLE_W<'a, REG>
64where
65 REG: crate::Writable + crate::RegisterSpec,
66{
67 #[doc = "I2C is disabled"]
68 #[inline(always)]
69 pub fn disabled(self) -> &'a mut crate::W<REG> {
70 self.variant(ENABLE_A::DISABLED)
71 }
72 #[doc = "I2C is enabled"]
73 #[inline(always)]
74 pub fn enabled(self) -> &'a mut crate::W<REG> {
75 self.variant(ENABLE_A::ENABLED)
76 }
77}
78#[doc = "Field `ABORT` reader - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
79
80 For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.
81
82 Reset value: 0x0"]
83pub type ABORT_R = crate::BitReader<ABORT_A>;
84#[doc = "When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
85
86 For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.
87
88 Reset value: 0x0
89
90Value on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92pub enum ABORT_A {
93 #[doc = "0: ABORT operation not in progress"]
94 DISABLE = 0,
95 #[doc = "1: ABORT operation in progress"]
96 ENABLED = 1,
97}
98impl From<ABORT_A> for bool {
99 #[inline(always)]
100 fn from(variant: ABORT_A) -> Self {
101 variant as u8 != 0
102 }
103}
104impl ABORT_R {
105 #[doc = "Get enumerated values variant"]
106 #[inline(always)]
107 pub const fn variant(&self) -> ABORT_A {
108 match self.bits {
109 false => ABORT_A::DISABLE,
110 true => ABORT_A::ENABLED,
111 }
112 }
113 #[doc = "ABORT operation not in progress"]
114 #[inline(always)]
115 pub fn is_disable(&self) -> bool {
116 *self == ABORT_A::DISABLE
117 }
118 #[doc = "ABORT operation in progress"]
119 #[inline(always)]
120 pub fn is_enabled(&self) -> bool {
121 *self == ABORT_A::ENABLED
122 }
123}
124#[doc = "Field `ABORT` writer - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
125
126 For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.
127
128 Reset value: 0x0"]
129pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG, ABORT_A>;
130impl<'a, REG> ABORT_W<'a, REG>
131where
132 REG: crate::Writable + crate::RegisterSpec,
133{
134 #[doc = "ABORT operation not in progress"]
135 #[inline(always)]
136 pub fn disable(self) -> &'a mut crate::W<REG> {
137 self.variant(ABORT_A::DISABLE)
138 }
139 #[doc = "ABORT operation in progress"]
140 #[inline(always)]
141 pub fn enabled(self) -> &'a mut crate::W<REG> {
142 self.variant(ABORT_A::ENABLED)
143 }
144}
145#[doc = "Field `TX_CMD_BLOCK` reader - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\]
146== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"]
147pub type TX_CMD_BLOCK_R = crate::BitReader<TX_CMD_BLOCK_A>;
148#[doc = "In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\]
149== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT
150
151Value on reset: 0"]
152#[derive(Clone, Copy, Debug, PartialEq, Eq)]
153pub enum TX_CMD_BLOCK_A {
154 #[doc = "0: Tx Command execution not blocked"]
155 NOT_BLOCKED = 0,
156 #[doc = "1: Tx Command execution blocked"]
157 BLOCKED = 1,
158}
159impl From<TX_CMD_BLOCK_A> for bool {
160 #[inline(always)]
161 fn from(variant: TX_CMD_BLOCK_A) -> Self {
162 variant as u8 != 0
163 }
164}
165impl TX_CMD_BLOCK_R {
166 #[doc = "Get enumerated values variant"]
167 #[inline(always)]
168 pub const fn variant(&self) -> TX_CMD_BLOCK_A {
169 match self.bits {
170 false => TX_CMD_BLOCK_A::NOT_BLOCKED,
171 true => TX_CMD_BLOCK_A::BLOCKED,
172 }
173 }
174 #[doc = "Tx Command execution not blocked"]
175 #[inline(always)]
176 pub fn is_not_blocked(&self) -> bool {
177 *self == TX_CMD_BLOCK_A::NOT_BLOCKED
178 }
179 #[doc = "Tx Command execution blocked"]
180 #[inline(always)]
181 pub fn is_blocked(&self) -> bool {
182 *self == TX_CMD_BLOCK_A::BLOCKED
183 }
184}
185#[doc = "Field `TX_CMD_BLOCK` writer - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\]
186== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"]
187pub type TX_CMD_BLOCK_W<'a, REG> = crate::BitWriter<'a, REG, TX_CMD_BLOCK_A>;
188impl<'a, REG> TX_CMD_BLOCK_W<'a, REG>
189where
190 REG: crate::Writable + crate::RegisterSpec,
191{
192 #[doc = "Tx Command execution not blocked"]
193 #[inline(always)]
194 pub fn not_blocked(self) -> &'a mut crate::W<REG> {
195 self.variant(TX_CMD_BLOCK_A::NOT_BLOCKED)
196 }
197 #[doc = "Tx Command execution blocked"]
198 #[inline(always)]
199 pub fn blocked(self) -> &'a mut crate::W<REG> {
200 self.variant(TX_CMD_BLOCK_A::BLOCKED)
201 }
202}
203impl R {
204 #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.
205
206 When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
207
208 In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'
209
210 Reset value: 0x0"]
211 #[inline(always)]
212 pub fn enable(&self) -> ENABLE_R {
213 ENABLE_R::new((self.bits & 1) != 0)
214 }
215 #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
216
217 For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.
218
219 Reset value: 0x0"]
220 #[inline(always)]
221 pub fn abort(&self) -> ABORT_R {
222 ABORT_R::new(((self.bits >> 1) & 1) != 0)
223 }
224 #[doc = "Bit 2 - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\]
225== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"]
226 #[inline(always)]
227 pub fn tx_cmd_block(&self) -> TX_CMD_BLOCK_R {
228 TX_CMD_BLOCK_R::new(((self.bits >> 2) & 1) != 0)
229 }
230}
231impl W {
232 #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.
233
234 When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
235
236 In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'
237
238 Reset value: 0x0"]
239 #[inline(always)]
240 #[must_use]
241 pub fn enable(&mut self) -> ENABLE_W<IC_ENABLE_SPEC> {
242 ENABLE_W::new(self, 0)
243 }
244 #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
245
246 For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.
247
248 Reset value: 0x0"]
249 #[inline(always)]
250 #[must_use]
251 pub fn abort(&mut self) -> ABORT_W<IC_ENABLE_SPEC> {
252 ABORT_W::new(self, 1)
253 }
254 #[doc = "Bit 2 - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\]
255== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"]
256 #[inline(always)]
257 #[must_use]
258 pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W<IC_ENABLE_SPEC> {
259 TX_CMD_BLOCK_W::new(self, 2)
260 }
261 #[doc = r" Writes raw bits to the register."]
262 #[doc = r""]
263 #[doc = r" # Safety"]
264 #[doc = r""]
265 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
266 #[inline(always)]
267 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
268 self.bits = bits;
269 self
270 }
271}
272#[doc = "I2C Enable Register
273
274You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
275pub struct IC_ENABLE_SPEC;
276impl crate::RegisterSpec for IC_ENABLE_SPEC {
277 type Ux = u32;
278}
279#[doc = "`read()` method returns [`ic_enable::R`](R) reader structure"]
280impl crate::Readable for IC_ENABLE_SPEC {}
281#[doc = "`write(|w| ..)` method takes [`ic_enable::W`](W) writer structure"]
282impl crate::Writable for IC_ENABLE_SPEC {
283 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
284 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
285}
286#[doc = "`reset()` method sets IC_ENABLE to value 0"]
287impl crate::Resettable for IC_ENABLE_SPEC {
288 const RESET_VALUE: u32 = 0;
289}