rp2040_pac/i2c0/
ic_intr_mask.rs

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1#[doc = "Register `IC_INTR_MASK` reader"]
2pub type R = crate::R<IC_INTR_MASK_SPEC>;
3#[doc = "Register `IC_INTR_MASK` writer"]
4pub type W = crate::W<IC_INTR_MASK_SPEC>;
5#[doc = "Field `M_RX_UNDER` reader - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.  
6
7 Reset value: 0x1"]
8pub type M_RX_UNDER_R = crate::BitReader<M_RX_UNDER_A>;
9#[doc = "This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.  
10
11 Reset value: 0x1  
12
13Value on reset: 1"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15pub enum M_RX_UNDER_A {
16    #[doc = "0: RX_UNDER interrupt is masked"]
17    ENABLED = 0,
18    #[doc = "1: RX_UNDER interrupt is unmasked"]
19    DISABLED = 1,
20}
21impl From<M_RX_UNDER_A> for bool {
22    #[inline(always)]
23    fn from(variant: M_RX_UNDER_A) -> Self {
24        variant as u8 != 0
25    }
26}
27impl M_RX_UNDER_R {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> M_RX_UNDER_A {
31        match self.bits {
32            false => M_RX_UNDER_A::ENABLED,
33            true => M_RX_UNDER_A::DISABLED,
34        }
35    }
36    #[doc = "RX_UNDER interrupt is masked"]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == M_RX_UNDER_A::ENABLED
40    }
41    #[doc = "RX_UNDER interrupt is unmasked"]
42    #[inline(always)]
43    pub fn is_disabled(&self) -> bool {
44        *self == M_RX_UNDER_A::DISABLED
45    }
46}
47#[doc = "Field `M_RX_UNDER` writer - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.  
48
49 Reset value: 0x1"]
50pub type M_RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_UNDER_A>;
51impl<'a, REG> M_RX_UNDER_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "RX_UNDER interrupt is masked"]
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(M_RX_UNDER_A::ENABLED)
59    }
60    #[doc = "RX_UNDER interrupt is unmasked"]
61    #[inline(always)]
62    pub fn disabled(self) -> &'a mut crate::W<REG> {
63        self.variant(M_RX_UNDER_A::DISABLED)
64    }
65}
66#[doc = "Field `M_RX_OVER` reader - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.  
67
68 Reset value: 0x1"]
69pub type M_RX_OVER_R = crate::BitReader<M_RX_OVER_A>;
70#[doc = "This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.  
71
72 Reset value: 0x1  
73
74Value on reset: 1"]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum M_RX_OVER_A {
77    #[doc = "0: RX_OVER interrupt is masked"]
78    ENABLED = 0,
79    #[doc = "1: RX_OVER interrupt is unmasked"]
80    DISABLED = 1,
81}
82impl From<M_RX_OVER_A> for bool {
83    #[inline(always)]
84    fn from(variant: M_RX_OVER_A) -> Self {
85        variant as u8 != 0
86    }
87}
88impl M_RX_OVER_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> M_RX_OVER_A {
92        match self.bits {
93            false => M_RX_OVER_A::ENABLED,
94            true => M_RX_OVER_A::DISABLED,
95        }
96    }
97    #[doc = "RX_OVER interrupt is masked"]
98    #[inline(always)]
99    pub fn is_enabled(&self) -> bool {
100        *self == M_RX_OVER_A::ENABLED
101    }
102    #[doc = "RX_OVER interrupt is unmasked"]
103    #[inline(always)]
104    pub fn is_disabled(&self) -> bool {
105        *self == M_RX_OVER_A::DISABLED
106    }
107}
108#[doc = "Field `M_RX_OVER` writer - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.  
109
110 Reset value: 0x1"]
111pub type M_RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_OVER_A>;
112impl<'a, REG> M_RX_OVER_W<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115{
116    #[doc = "RX_OVER interrupt is masked"]
117    #[inline(always)]
118    pub fn enabled(self) -> &'a mut crate::W<REG> {
119        self.variant(M_RX_OVER_A::ENABLED)
120    }
121    #[doc = "RX_OVER interrupt is unmasked"]
122    #[inline(always)]
123    pub fn disabled(self) -> &'a mut crate::W<REG> {
124        self.variant(M_RX_OVER_A::DISABLED)
125    }
126}
127#[doc = "Field `M_RX_FULL` reader - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.  
128
129 Reset value: 0x1"]
130pub type M_RX_FULL_R = crate::BitReader<M_RX_FULL_A>;
131#[doc = "This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.  
132
133 Reset value: 0x1  
134
135Value on reset: 1"]
136#[derive(Clone, Copy, Debug, PartialEq, Eq)]
137pub enum M_RX_FULL_A {
138    #[doc = "0: RX_FULL interrupt is masked"]
139    ENABLED = 0,
140    #[doc = "1: RX_FULL interrupt is unmasked"]
141    DISABLED = 1,
142}
143impl From<M_RX_FULL_A> for bool {
144    #[inline(always)]
145    fn from(variant: M_RX_FULL_A) -> Self {
146        variant as u8 != 0
147    }
148}
149impl M_RX_FULL_R {
150    #[doc = "Get enumerated values variant"]
151    #[inline(always)]
152    pub const fn variant(&self) -> M_RX_FULL_A {
153        match self.bits {
154            false => M_RX_FULL_A::ENABLED,
155            true => M_RX_FULL_A::DISABLED,
156        }
157    }
158    #[doc = "RX_FULL interrupt is masked"]
159    #[inline(always)]
160    pub fn is_enabled(&self) -> bool {
161        *self == M_RX_FULL_A::ENABLED
162    }
163    #[doc = "RX_FULL interrupt is unmasked"]
164    #[inline(always)]
165    pub fn is_disabled(&self) -> bool {
166        *self == M_RX_FULL_A::DISABLED
167    }
168}
169#[doc = "Field `M_RX_FULL` writer - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.  
170
171 Reset value: 0x1"]
172pub type M_RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_FULL_A>;
173impl<'a, REG> M_RX_FULL_W<'a, REG>
174where
175    REG: crate::Writable + crate::RegisterSpec,
176{
177    #[doc = "RX_FULL interrupt is masked"]
178    #[inline(always)]
179    pub fn enabled(self) -> &'a mut crate::W<REG> {
180        self.variant(M_RX_FULL_A::ENABLED)
181    }
182    #[doc = "RX_FULL interrupt is unmasked"]
183    #[inline(always)]
184    pub fn disabled(self) -> &'a mut crate::W<REG> {
185        self.variant(M_RX_FULL_A::DISABLED)
186    }
187}
188#[doc = "Field `M_TX_OVER` reader - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.  
189
190 Reset value: 0x1"]
191pub type M_TX_OVER_R = crate::BitReader<M_TX_OVER_A>;
192#[doc = "This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.  
193
194 Reset value: 0x1  
195
196Value on reset: 1"]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum M_TX_OVER_A {
199    #[doc = "0: TX_OVER interrupt is masked"]
200    ENABLED = 0,
201    #[doc = "1: TX_OVER interrupt is unmasked"]
202    DISABLED = 1,
203}
204impl From<M_TX_OVER_A> for bool {
205    #[inline(always)]
206    fn from(variant: M_TX_OVER_A) -> Self {
207        variant as u8 != 0
208    }
209}
210impl M_TX_OVER_R {
211    #[doc = "Get enumerated values variant"]
212    #[inline(always)]
213    pub const fn variant(&self) -> M_TX_OVER_A {
214        match self.bits {
215            false => M_TX_OVER_A::ENABLED,
216            true => M_TX_OVER_A::DISABLED,
217        }
218    }
219    #[doc = "TX_OVER interrupt is masked"]
220    #[inline(always)]
221    pub fn is_enabled(&self) -> bool {
222        *self == M_TX_OVER_A::ENABLED
223    }
224    #[doc = "TX_OVER interrupt is unmasked"]
225    #[inline(always)]
226    pub fn is_disabled(&self) -> bool {
227        *self == M_TX_OVER_A::DISABLED
228    }
229}
230#[doc = "Field `M_TX_OVER` writer - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.  
231
232 Reset value: 0x1"]
233pub type M_TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_OVER_A>;
234impl<'a, REG> M_TX_OVER_W<'a, REG>
235where
236    REG: crate::Writable + crate::RegisterSpec,
237{
238    #[doc = "TX_OVER interrupt is masked"]
239    #[inline(always)]
240    pub fn enabled(self) -> &'a mut crate::W<REG> {
241        self.variant(M_TX_OVER_A::ENABLED)
242    }
243    #[doc = "TX_OVER interrupt is unmasked"]
244    #[inline(always)]
245    pub fn disabled(self) -> &'a mut crate::W<REG> {
246        self.variant(M_TX_OVER_A::DISABLED)
247    }
248}
249#[doc = "Field `M_TX_EMPTY` reader - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.  
250
251 Reset value: 0x1"]
252pub type M_TX_EMPTY_R = crate::BitReader<M_TX_EMPTY_A>;
253#[doc = "This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.  
254
255 Reset value: 0x1  
256
257Value on reset: 1"]
258#[derive(Clone, Copy, Debug, PartialEq, Eq)]
259pub enum M_TX_EMPTY_A {
260    #[doc = "0: TX_EMPTY interrupt is masked"]
261    ENABLED = 0,
262    #[doc = "1: TX_EMPTY interrupt is unmasked"]
263    DISABLED = 1,
264}
265impl From<M_TX_EMPTY_A> for bool {
266    #[inline(always)]
267    fn from(variant: M_TX_EMPTY_A) -> Self {
268        variant as u8 != 0
269    }
270}
271impl M_TX_EMPTY_R {
272    #[doc = "Get enumerated values variant"]
273    #[inline(always)]
274    pub const fn variant(&self) -> M_TX_EMPTY_A {
275        match self.bits {
276            false => M_TX_EMPTY_A::ENABLED,
277            true => M_TX_EMPTY_A::DISABLED,
278        }
279    }
280    #[doc = "TX_EMPTY interrupt is masked"]
281    #[inline(always)]
282    pub fn is_enabled(&self) -> bool {
283        *self == M_TX_EMPTY_A::ENABLED
284    }
285    #[doc = "TX_EMPTY interrupt is unmasked"]
286    #[inline(always)]
287    pub fn is_disabled(&self) -> bool {
288        *self == M_TX_EMPTY_A::DISABLED
289    }
290}
291#[doc = "Field `M_TX_EMPTY` writer - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.  
292
293 Reset value: 0x1"]
294pub type M_TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_EMPTY_A>;
295impl<'a, REG> M_TX_EMPTY_W<'a, REG>
296where
297    REG: crate::Writable + crate::RegisterSpec,
298{
299    #[doc = "TX_EMPTY interrupt is masked"]
300    #[inline(always)]
301    pub fn enabled(self) -> &'a mut crate::W<REG> {
302        self.variant(M_TX_EMPTY_A::ENABLED)
303    }
304    #[doc = "TX_EMPTY interrupt is unmasked"]
305    #[inline(always)]
306    pub fn disabled(self) -> &'a mut crate::W<REG> {
307        self.variant(M_TX_EMPTY_A::DISABLED)
308    }
309}
310#[doc = "Field `M_RD_REQ` reader - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.  
311
312 Reset value: 0x1"]
313pub type M_RD_REQ_R = crate::BitReader<M_RD_REQ_A>;
314#[doc = "This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.  
315
316 Reset value: 0x1  
317
318Value on reset: 1"]
319#[derive(Clone, Copy, Debug, PartialEq, Eq)]
320pub enum M_RD_REQ_A {
321    #[doc = "0: RD_REQ interrupt is masked"]
322    ENABLED = 0,
323    #[doc = "1: RD_REQ interrupt is unmasked"]
324    DISABLED = 1,
325}
326impl From<M_RD_REQ_A> for bool {
327    #[inline(always)]
328    fn from(variant: M_RD_REQ_A) -> Self {
329        variant as u8 != 0
330    }
331}
332impl M_RD_REQ_R {
333    #[doc = "Get enumerated values variant"]
334    #[inline(always)]
335    pub const fn variant(&self) -> M_RD_REQ_A {
336        match self.bits {
337            false => M_RD_REQ_A::ENABLED,
338            true => M_RD_REQ_A::DISABLED,
339        }
340    }
341    #[doc = "RD_REQ interrupt is masked"]
342    #[inline(always)]
343    pub fn is_enabled(&self) -> bool {
344        *self == M_RD_REQ_A::ENABLED
345    }
346    #[doc = "RD_REQ interrupt is unmasked"]
347    #[inline(always)]
348    pub fn is_disabled(&self) -> bool {
349        *self == M_RD_REQ_A::DISABLED
350    }
351}
352#[doc = "Field `M_RD_REQ` writer - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.  
353
354 Reset value: 0x1"]
355pub type M_RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG, M_RD_REQ_A>;
356impl<'a, REG> M_RD_REQ_W<'a, REG>
357where
358    REG: crate::Writable + crate::RegisterSpec,
359{
360    #[doc = "RD_REQ interrupt is masked"]
361    #[inline(always)]
362    pub fn enabled(self) -> &'a mut crate::W<REG> {
363        self.variant(M_RD_REQ_A::ENABLED)
364    }
365    #[doc = "RD_REQ interrupt is unmasked"]
366    #[inline(always)]
367    pub fn disabled(self) -> &'a mut crate::W<REG> {
368        self.variant(M_RD_REQ_A::DISABLED)
369    }
370}
371#[doc = "Field `M_TX_ABRT` reader - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.  
372
373 Reset value: 0x1"]
374pub type M_TX_ABRT_R = crate::BitReader<M_TX_ABRT_A>;
375#[doc = "This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.  
376
377 Reset value: 0x1  
378
379Value on reset: 1"]
380#[derive(Clone, Copy, Debug, PartialEq, Eq)]
381pub enum M_TX_ABRT_A {
382    #[doc = "0: TX_ABORT interrupt is masked"]
383    ENABLED = 0,
384    #[doc = "1: TX_ABORT interrupt is unmasked"]
385    DISABLED = 1,
386}
387impl From<M_TX_ABRT_A> for bool {
388    #[inline(always)]
389    fn from(variant: M_TX_ABRT_A) -> Self {
390        variant as u8 != 0
391    }
392}
393impl M_TX_ABRT_R {
394    #[doc = "Get enumerated values variant"]
395    #[inline(always)]
396    pub const fn variant(&self) -> M_TX_ABRT_A {
397        match self.bits {
398            false => M_TX_ABRT_A::ENABLED,
399            true => M_TX_ABRT_A::DISABLED,
400        }
401    }
402    #[doc = "TX_ABORT interrupt is masked"]
403    #[inline(always)]
404    pub fn is_enabled(&self) -> bool {
405        *self == M_TX_ABRT_A::ENABLED
406    }
407    #[doc = "TX_ABORT interrupt is unmasked"]
408    #[inline(always)]
409    pub fn is_disabled(&self) -> bool {
410        *self == M_TX_ABRT_A::DISABLED
411    }
412}
413#[doc = "Field `M_TX_ABRT` writer - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.  
414
415 Reset value: 0x1"]
416pub type M_TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_ABRT_A>;
417impl<'a, REG> M_TX_ABRT_W<'a, REG>
418where
419    REG: crate::Writable + crate::RegisterSpec,
420{
421    #[doc = "TX_ABORT interrupt is masked"]
422    #[inline(always)]
423    pub fn enabled(self) -> &'a mut crate::W<REG> {
424        self.variant(M_TX_ABRT_A::ENABLED)
425    }
426    #[doc = "TX_ABORT interrupt is unmasked"]
427    #[inline(always)]
428    pub fn disabled(self) -> &'a mut crate::W<REG> {
429        self.variant(M_TX_ABRT_A::DISABLED)
430    }
431}
432#[doc = "Field `M_RX_DONE` reader - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.  
433
434 Reset value: 0x1"]
435pub type M_RX_DONE_R = crate::BitReader<M_RX_DONE_A>;
436#[doc = "This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.  
437
438 Reset value: 0x1  
439
440Value on reset: 1"]
441#[derive(Clone, Copy, Debug, PartialEq, Eq)]
442pub enum M_RX_DONE_A {
443    #[doc = "0: RX_DONE interrupt is masked"]
444    ENABLED = 0,
445    #[doc = "1: RX_DONE interrupt is unmasked"]
446    DISABLED = 1,
447}
448impl From<M_RX_DONE_A> for bool {
449    #[inline(always)]
450    fn from(variant: M_RX_DONE_A) -> Self {
451        variant as u8 != 0
452    }
453}
454impl M_RX_DONE_R {
455    #[doc = "Get enumerated values variant"]
456    #[inline(always)]
457    pub const fn variant(&self) -> M_RX_DONE_A {
458        match self.bits {
459            false => M_RX_DONE_A::ENABLED,
460            true => M_RX_DONE_A::DISABLED,
461        }
462    }
463    #[doc = "RX_DONE interrupt is masked"]
464    #[inline(always)]
465    pub fn is_enabled(&self) -> bool {
466        *self == M_RX_DONE_A::ENABLED
467    }
468    #[doc = "RX_DONE interrupt is unmasked"]
469    #[inline(always)]
470    pub fn is_disabled(&self) -> bool {
471        *self == M_RX_DONE_A::DISABLED
472    }
473}
474#[doc = "Field `M_RX_DONE` writer - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.  
475
476 Reset value: 0x1"]
477pub type M_RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_DONE_A>;
478impl<'a, REG> M_RX_DONE_W<'a, REG>
479where
480    REG: crate::Writable + crate::RegisterSpec,
481{
482    #[doc = "RX_DONE interrupt is masked"]
483    #[inline(always)]
484    pub fn enabled(self) -> &'a mut crate::W<REG> {
485        self.variant(M_RX_DONE_A::ENABLED)
486    }
487    #[doc = "RX_DONE interrupt is unmasked"]
488    #[inline(always)]
489    pub fn disabled(self) -> &'a mut crate::W<REG> {
490        self.variant(M_RX_DONE_A::DISABLED)
491    }
492}
493#[doc = "Field `M_ACTIVITY` reader - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.  
494
495 Reset value: 0x0"]
496pub type M_ACTIVITY_R = crate::BitReader<M_ACTIVITY_A>;
497#[doc = "This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.  
498
499 Reset value: 0x0  
500
501Value on reset: 0"]
502#[derive(Clone, Copy, Debug, PartialEq, Eq)]
503pub enum M_ACTIVITY_A {
504    #[doc = "0: ACTIVITY interrupt is masked"]
505    ENABLED = 0,
506    #[doc = "1: ACTIVITY interrupt is unmasked"]
507    DISABLED = 1,
508}
509impl From<M_ACTIVITY_A> for bool {
510    #[inline(always)]
511    fn from(variant: M_ACTIVITY_A) -> Self {
512        variant as u8 != 0
513    }
514}
515impl M_ACTIVITY_R {
516    #[doc = "Get enumerated values variant"]
517    #[inline(always)]
518    pub const fn variant(&self) -> M_ACTIVITY_A {
519        match self.bits {
520            false => M_ACTIVITY_A::ENABLED,
521            true => M_ACTIVITY_A::DISABLED,
522        }
523    }
524    #[doc = "ACTIVITY interrupt is masked"]
525    #[inline(always)]
526    pub fn is_enabled(&self) -> bool {
527        *self == M_ACTIVITY_A::ENABLED
528    }
529    #[doc = "ACTIVITY interrupt is unmasked"]
530    #[inline(always)]
531    pub fn is_disabled(&self) -> bool {
532        *self == M_ACTIVITY_A::DISABLED
533    }
534}
535#[doc = "Field `M_ACTIVITY` writer - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.  
536
537 Reset value: 0x0"]
538pub type M_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG, M_ACTIVITY_A>;
539impl<'a, REG> M_ACTIVITY_W<'a, REG>
540where
541    REG: crate::Writable + crate::RegisterSpec,
542{
543    #[doc = "ACTIVITY interrupt is masked"]
544    #[inline(always)]
545    pub fn enabled(self) -> &'a mut crate::W<REG> {
546        self.variant(M_ACTIVITY_A::ENABLED)
547    }
548    #[doc = "ACTIVITY interrupt is unmasked"]
549    #[inline(always)]
550    pub fn disabled(self) -> &'a mut crate::W<REG> {
551        self.variant(M_ACTIVITY_A::DISABLED)
552    }
553}
554#[doc = "Field `M_STOP_DET` reader - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.  
555
556 Reset value: 0x0"]
557pub type M_STOP_DET_R = crate::BitReader<M_STOP_DET_A>;
558#[doc = "This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.  
559
560 Reset value: 0x0  
561
562Value on reset: 0"]
563#[derive(Clone, Copy, Debug, PartialEq, Eq)]
564pub enum M_STOP_DET_A {
565    #[doc = "0: STOP_DET interrupt is masked"]
566    ENABLED = 0,
567    #[doc = "1: STOP_DET interrupt is unmasked"]
568    DISABLED = 1,
569}
570impl From<M_STOP_DET_A> for bool {
571    #[inline(always)]
572    fn from(variant: M_STOP_DET_A) -> Self {
573        variant as u8 != 0
574    }
575}
576impl M_STOP_DET_R {
577    #[doc = "Get enumerated values variant"]
578    #[inline(always)]
579    pub const fn variant(&self) -> M_STOP_DET_A {
580        match self.bits {
581            false => M_STOP_DET_A::ENABLED,
582            true => M_STOP_DET_A::DISABLED,
583        }
584    }
585    #[doc = "STOP_DET interrupt is masked"]
586    #[inline(always)]
587    pub fn is_enabled(&self) -> bool {
588        *self == M_STOP_DET_A::ENABLED
589    }
590    #[doc = "STOP_DET interrupt is unmasked"]
591    #[inline(always)]
592    pub fn is_disabled(&self) -> bool {
593        *self == M_STOP_DET_A::DISABLED
594    }
595}
596#[doc = "Field `M_STOP_DET` writer - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.  
597
598 Reset value: 0x0"]
599pub type M_STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_STOP_DET_A>;
600impl<'a, REG> M_STOP_DET_W<'a, REG>
601where
602    REG: crate::Writable + crate::RegisterSpec,
603{
604    #[doc = "STOP_DET interrupt is masked"]
605    #[inline(always)]
606    pub fn enabled(self) -> &'a mut crate::W<REG> {
607        self.variant(M_STOP_DET_A::ENABLED)
608    }
609    #[doc = "STOP_DET interrupt is unmasked"]
610    #[inline(always)]
611    pub fn disabled(self) -> &'a mut crate::W<REG> {
612        self.variant(M_STOP_DET_A::DISABLED)
613    }
614}
615#[doc = "Field `M_START_DET` reader - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.  
616
617 Reset value: 0x0"]
618pub type M_START_DET_R = crate::BitReader<M_START_DET_A>;
619#[doc = "This bit masks the R_START_DET interrupt in IC_INTR_STAT register.  
620
621 Reset value: 0x0  
622
623Value on reset: 0"]
624#[derive(Clone, Copy, Debug, PartialEq, Eq)]
625pub enum M_START_DET_A {
626    #[doc = "0: START_DET interrupt is masked"]
627    ENABLED = 0,
628    #[doc = "1: START_DET interrupt is unmasked"]
629    DISABLED = 1,
630}
631impl From<M_START_DET_A> for bool {
632    #[inline(always)]
633    fn from(variant: M_START_DET_A) -> Self {
634        variant as u8 != 0
635    }
636}
637impl M_START_DET_R {
638    #[doc = "Get enumerated values variant"]
639    #[inline(always)]
640    pub const fn variant(&self) -> M_START_DET_A {
641        match self.bits {
642            false => M_START_DET_A::ENABLED,
643            true => M_START_DET_A::DISABLED,
644        }
645    }
646    #[doc = "START_DET interrupt is masked"]
647    #[inline(always)]
648    pub fn is_enabled(&self) -> bool {
649        *self == M_START_DET_A::ENABLED
650    }
651    #[doc = "START_DET interrupt is unmasked"]
652    #[inline(always)]
653    pub fn is_disabled(&self) -> bool {
654        *self == M_START_DET_A::DISABLED
655    }
656}
657#[doc = "Field `M_START_DET` writer - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.  
658
659 Reset value: 0x0"]
660pub type M_START_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_START_DET_A>;
661impl<'a, REG> M_START_DET_W<'a, REG>
662where
663    REG: crate::Writable + crate::RegisterSpec,
664{
665    #[doc = "START_DET interrupt is masked"]
666    #[inline(always)]
667    pub fn enabled(self) -> &'a mut crate::W<REG> {
668        self.variant(M_START_DET_A::ENABLED)
669    }
670    #[doc = "START_DET interrupt is unmasked"]
671    #[inline(always)]
672    pub fn disabled(self) -> &'a mut crate::W<REG> {
673        self.variant(M_START_DET_A::DISABLED)
674    }
675}
676#[doc = "Field `M_GEN_CALL` reader - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.  
677
678 Reset value: 0x1"]
679pub type M_GEN_CALL_R = crate::BitReader<M_GEN_CALL_A>;
680#[doc = "This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.  
681
682 Reset value: 0x1  
683
684Value on reset: 1"]
685#[derive(Clone, Copy, Debug, PartialEq, Eq)]
686pub enum M_GEN_CALL_A {
687    #[doc = "0: GEN_CALL interrupt is masked"]
688    ENABLED = 0,
689    #[doc = "1: GEN_CALL interrupt is unmasked"]
690    DISABLED = 1,
691}
692impl From<M_GEN_CALL_A> for bool {
693    #[inline(always)]
694    fn from(variant: M_GEN_CALL_A) -> Self {
695        variant as u8 != 0
696    }
697}
698impl M_GEN_CALL_R {
699    #[doc = "Get enumerated values variant"]
700    #[inline(always)]
701    pub const fn variant(&self) -> M_GEN_CALL_A {
702        match self.bits {
703            false => M_GEN_CALL_A::ENABLED,
704            true => M_GEN_CALL_A::DISABLED,
705        }
706    }
707    #[doc = "GEN_CALL interrupt is masked"]
708    #[inline(always)]
709    pub fn is_enabled(&self) -> bool {
710        *self == M_GEN_CALL_A::ENABLED
711    }
712    #[doc = "GEN_CALL interrupt is unmasked"]
713    #[inline(always)]
714    pub fn is_disabled(&self) -> bool {
715        *self == M_GEN_CALL_A::DISABLED
716    }
717}
718#[doc = "Field `M_GEN_CALL` writer - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.  
719
720 Reset value: 0x1"]
721pub type M_GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG, M_GEN_CALL_A>;
722impl<'a, REG> M_GEN_CALL_W<'a, REG>
723where
724    REG: crate::Writable + crate::RegisterSpec,
725{
726    #[doc = "GEN_CALL interrupt is masked"]
727    #[inline(always)]
728    pub fn enabled(self) -> &'a mut crate::W<REG> {
729        self.variant(M_GEN_CALL_A::ENABLED)
730    }
731    #[doc = "GEN_CALL interrupt is unmasked"]
732    #[inline(always)]
733    pub fn disabled(self) -> &'a mut crate::W<REG> {
734        self.variant(M_GEN_CALL_A::DISABLED)
735    }
736}
737#[doc = "Field `M_RESTART_DET` reader - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.  
738
739 Reset value: 0x0"]
740pub type M_RESTART_DET_R = crate::BitReader<M_RESTART_DET_A>;
741#[doc = "This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.  
742
743 Reset value: 0x0  
744
745Value on reset: 0"]
746#[derive(Clone, Copy, Debug, PartialEq, Eq)]
747pub enum M_RESTART_DET_A {
748    #[doc = "0: RESTART_DET interrupt is masked"]
749    ENABLED = 0,
750    #[doc = "1: RESTART_DET interrupt is unmasked"]
751    DISABLED = 1,
752}
753impl From<M_RESTART_DET_A> for bool {
754    #[inline(always)]
755    fn from(variant: M_RESTART_DET_A) -> Self {
756        variant as u8 != 0
757    }
758}
759impl M_RESTART_DET_R {
760    #[doc = "Get enumerated values variant"]
761    #[inline(always)]
762    pub const fn variant(&self) -> M_RESTART_DET_A {
763        match self.bits {
764            false => M_RESTART_DET_A::ENABLED,
765            true => M_RESTART_DET_A::DISABLED,
766        }
767    }
768    #[doc = "RESTART_DET interrupt is masked"]
769    #[inline(always)]
770    pub fn is_enabled(&self) -> bool {
771        *self == M_RESTART_DET_A::ENABLED
772    }
773    #[doc = "RESTART_DET interrupt is unmasked"]
774    #[inline(always)]
775    pub fn is_disabled(&self) -> bool {
776        *self == M_RESTART_DET_A::DISABLED
777    }
778}
779#[doc = "Field `M_RESTART_DET` writer - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.  
780
781 Reset value: 0x0"]
782pub type M_RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_RESTART_DET_A>;
783impl<'a, REG> M_RESTART_DET_W<'a, REG>
784where
785    REG: crate::Writable + crate::RegisterSpec,
786{
787    #[doc = "RESTART_DET interrupt is masked"]
788    #[inline(always)]
789    pub fn enabled(self) -> &'a mut crate::W<REG> {
790        self.variant(M_RESTART_DET_A::ENABLED)
791    }
792    #[doc = "RESTART_DET interrupt is unmasked"]
793    #[inline(always)]
794    pub fn disabled(self) -> &'a mut crate::W<REG> {
795        self.variant(M_RESTART_DET_A::DISABLED)
796    }
797}
798impl R {
799    #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.  
800
801 Reset value: 0x1"]
802    #[inline(always)]
803    pub fn m_rx_under(&self) -> M_RX_UNDER_R {
804        M_RX_UNDER_R::new((self.bits & 1) != 0)
805    }
806    #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.  
807
808 Reset value: 0x1"]
809    #[inline(always)]
810    pub fn m_rx_over(&self) -> M_RX_OVER_R {
811        M_RX_OVER_R::new(((self.bits >> 1) & 1) != 0)
812    }
813    #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.  
814
815 Reset value: 0x1"]
816    #[inline(always)]
817    pub fn m_rx_full(&self) -> M_RX_FULL_R {
818        M_RX_FULL_R::new(((self.bits >> 2) & 1) != 0)
819    }
820    #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.  
821
822 Reset value: 0x1"]
823    #[inline(always)]
824    pub fn m_tx_over(&self) -> M_TX_OVER_R {
825        M_TX_OVER_R::new(((self.bits >> 3) & 1) != 0)
826    }
827    #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.  
828
829 Reset value: 0x1"]
830    #[inline(always)]
831    pub fn m_tx_empty(&self) -> M_TX_EMPTY_R {
832        M_TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
833    }
834    #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.  
835
836 Reset value: 0x1"]
837    #[inline(always)]
838    pub fn m_rd_req(&self) -> M_RD_REQ_R {
839        M_RD_REQ_R::new(((self.bits >> 5) & 1) != 0)
840    }
841    #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.  
842
843 Reset value: 0x1"]
844    #[inline(always)]
845    pub fn m_tx_abrt(&self) -> M_TX_ABRT_R {
846        M_TX_ABRT_R::new(((self.bits >> 6) & 1) != 0)
847    }
848    #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.  
849
850 Reset value: 0x1"]
851    #[inline(always)]
852    pub fn m_rx_done(&self) -> M_RX_DONE_R {
853        M_RX_DONE_R::new(((self.bits >> 7) & 1) != 0)
854    }
855    #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.  
856
857 Reset value: 0x0"]
858    #[inline(always)]
859    pub fn m_activity(&self) -> M_ACTIVITY_R {
860        M_ACTIVITY_R::new(((self.bits >> 8) & 1) != 0)
861    }
862    #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.  
863
864 Reset value: 0x0"]
865    #[inline(always)]
866    pub fn m_stop_det(&self) -> M_STOP_DET_R {
867        M_STOP_DET_R::new(((self.bits >> 9) & 1) != 0)
868    }
869    #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.  
870
871 Reset value: 0x0"]
872    #[inline(always)]
873    pub fn m_start_det(&self) -> M_START_DET_R {
874        M_START_DET_R::new(((self.bits >> 10) & 1) != 0)
875    }
876    #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.  
877
878 Reset value: 0x1"]
879    #[inline(always)]
880    pub fn m_gen_call(&self) -> M_GEN_CALL_R {
881        M_GEN_CALL_R::new(((self.bits >> 11) & 1) != 0)
882    }
883    #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.  
884
885 Reset value: 0x0"]
886    #[inline(always)]
887    pub fn m_restart_det(&self) -> M_RESTART_DET_R {
888        M_RESTART_DET_R::new(((self.bits >> 12) & 1) != 0)
889    }
890}
891impl W {
892    #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.  
893
894 Reset value: 0x1"]
895    #[inline(always)]
896    #[must_use]
897    pub fn m_rx_under(&mut self) -> M_RX_UNDER_W<IC_INTR_MASK_SPEC> {
898        M_RX_UNDER_W::new(self, 0)
899    }
900    #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.  
901
902 Reset value: 0x1"]
903    #[inline(always)]
904    #[must_use]
905    pub fn m_rx_over(&mut self) -> M_RX_OVER_W<IC_INTR_MASK_SPEC> {
906        M_RX_OVER_W::new(self, 1)
907    }
908    #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.  
909
910 Reset value: 0x1"]
911    #[inline(always)]
912    #[must_use]
913    pub fn m_rx_full(&mut self) -> M_RX_FULL_W<IC_INTR_MASK_SPEC> {
914        M_RX_FULL_W::new(self, 2)
915    }
916    #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.  
917
918 Reset value: 0x1"]
919    #[inline(always)]
920    #[must_use]
921    pub fn m_tx_over(&mut self) -> M_TX_OVER_W<IC_INTR_MASK_SPEC> {
922        M_TX_OVER_W::new(self, 3)
923    }
924    #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.  
925
926 Reset value: 0x1"]
927    #[inline(always)]
928    #[must_use]
929    pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W<IC_INTR_MASK_SPEC> {
930        M_TX_EMPTY_W::new(self, 4)
931    }
932    #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.  
933
934 Reset value: 0x1"]
935    #[inline(always)]
936    #[must_use]
937    pub fn m_rd_req(&mut self) -> M_RD_REQ_W<IC_INTR_MASK_SPEC> {
938        M_RD_REQ_W::new(self, 5)
939    }
940    #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.  
941
942 Reset value: 0x1"]
943    #[inline(always)]
944    #[must_use]
945    pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W<IC_INTR_MASK_SPEC> {
946        M_TX_ABRT_W::new(self, 6)
947    }
948    #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.  
949
950 Reset value: 0x1"]
951    #[inline(always)]
952    #[must_use]
953    pub fn m_rx_done(&mut self) -> M_RX_DONE_W<IC_INTR_MASK_SPEC> {
954        M_RX_DONE_W::new(self, 7)
955    }
956    #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.  
957
958 Reset value: 0x0"]
959    #[inline(always)]
960    #[must_use]
961    pub fn m_activity(&mut self) -> M_ACTIVITY_W<IC_INTR_MASK_SPEC> {
962        M_ACTIVITY_W::new(self, 8)
963    }
964    #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.  
965
966 Reset value: 0x0"]
967    #[inline(always)]
968    #[must_use]
969    pub fn m_stop_det(&mut self) -> M_STOP_DET_W<IC_INTR_MASK_SPEC> {
970        M_STOP_DET_W::new(self, 9)
971    }
972    #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.  
973
974 Reset value: 0x0"]
975    #[inline(always)]
976    #[must_use]
977    pub fn m_start_det(&mut self) -> M_START_DET_W<IC_INTR_MASK_SPEC> {
978        M_START_DET_W::new(self, 10)
979    }
980    #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.  
981
982 Reset value: 0x1"]
983    #[inline(always)]
984    #[must_use]
985    pub fn m_gen_call(&mut self) -> M_GEN_CALL_W<IC_INTR_MASK_SPEC> {
986        M_GEN_CALL_W::new(self, 11)
987    }
988    #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.  
989
990 Reset value: 0x0"]
991    #[inline(always)]
992    #[must_use]
993    pub fn m_restart_det(&mut self) -> M_RESTART_DET_W<IC_INTR_MASK_SPEC> {
994        M_RESTART_DET_W::new(self, 12)
995    }
996    #[doc = r" Writes raw bits to the register."]
997    #[doc = r""]
998    #[doc = r" # Safety"]
999    #[doc = r""]
1000    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1001    #[inline(always)]
1002    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1003        self.bits = bits;
1004        self
1005    }
1006}
1007#[doc = "I2C Interrupt Mask Register.  
1008
1009 These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.  
1010
1011You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_mask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1012pub struct IC_INTR_MASK_SPEC;
1013impl crate::RegisterSpec for IC_INTR_MASK_SPEC {
1014    type Ux = u32;
1015}
1016#[doc = "`read()` method returns [`ic_intr_mask::R`](R) reader structure"]
1017impl crate::Readable for IC_INTR_MASK_SPEC {}
1018#[doc = "`write(|w| ..)` method takes [`ic_intr_mask::W`](W) writer structure"]
1019impl crate::Writable for IC_INTR_MASK_SPEC {
1020    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1021    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1022}
1023#[doc = "`reset()` method sets IC_INTR_MASK to value 0x08ff"]
1024impl crate::Resettable for IC_INTR_MASK_SPEC {
1025    const RESET_VALUE: u32 = 0x08ff;
1026}
rp2040_pac/i2c0/ic_intr_mask.rs

rp2040_pac/i2c0/
ic_intr_mask.rs
