imxrt_ral/blocks/imxrt1011/
adc.rs
1#[doc = "Analog-to-Digital Converter"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Control register for hardware triggers"]
5 pub HC0: crate::RWRegister<u32>,
6 #[doc = "Control register for hardware triggers"]
7 pub HC: [crate::RWRegister<u32>; 7usize],
8 #[doc = "Status register for HW triggers"]
9 pub HS: crate::RORegister<u32>,
10 #[doc = "Data result register for HW triggers"]
11 pub R0: crate::RORegister<u32>,
12 #[doc = "Data result register for HW triggers"]
13 pub R: [crate::RORegister<u32>; 7usize],
14 #[doc = "Configuration register"]
15 pub CFG: crate::RWRegister<u32>,
16 #[doc = "General control register"]
17 pub GC: crate::RWRegister<u32>,
18 #[doc = "General status register"]
19 pub GS: crate::RWRegister<u32>,
20 #[doc = "Compare value register"]
21 pub CV: crate::RWRegister<u32>,
22 #[doc = "Offset correction value register"]
23 pub OFS: crate::RWRegister<u32>,
24 #[doc = "Calibration value register"]
25 pub CAL: crate::RWRegister<u32>,
26}
27#[doc = "Control register for hardware triggers"]
28pub mod HC0 {
29 #[doc = "Input Channel Select"]
30 pub mod ADCH {
31 pub const offset: u32 = 0;
32 pub const mask: u32 = 0x1f << offset;
33 pub mod R {}
34 pub mod W {}
35 pub mod RW {
36 #[doc = "External channel selection from ADC_ETC"]
37 pub const ADCH_16: u32 = 0x10;
38 #[doc = "VREFSH = internal channel, for ADC self-test, hard connected to VRH internally"]
39 pub const ADCH_25: u32 = 0x19;
40 #[doc = "Conversion Disabled. Hardware Triggers will not initiate any conversion."]
41 pub const ADCH_31: u32 = 0x1f;
42 }
43 }
44 #[doc = "Conversion Complete Interrupt Enable/Disable Control"]
45 pub mod AIEN {
46 pub const offset: u32 = 7;
47 pub const mask: u32 = 0x01 << offset;
48 pub mod R {}
49 pub mod W {}
50 pub mod RW {
51 #[doc = "Conversion complete interrupt disabled"]
52 pub const AIEN_0: u32 = 0;
53 #[doc = "Conversion complete interrupt enabled"]
54 pub const AIEN_1: u32 = 0x01;
55 }
56 }
57}
58#[doc = "Control register for hardware triggers"]
59pub mod HC {
60 #[doc = "Input Channel Select"]
61 pub mod ADCH {
62 pub const offset: u32 = 0;
63 pub const mask: u32 = 0x1f << offset;
64 pub mod R {}
65 pub mod W {}
66 pub mod RW {
67 #[doc = "External channel selection from ADC_ETC"]
68 pub const ADCH_16: u32 = 0x10;
69 #[doc = "VREFSH = internal channel, for ADC self-test, hard connected to VRH internally"]
70 pub const ADCH_25: u32 = 0x19;
71 #[doc = "Conversion Disabled. Hardware Triggers will not initiate any conversion."]
72 pub const ADCH_31: u32 = 0x1f;
73 }
74 }
75 #[doc = "Conversion Complete Interrupt Enable/Disable Control"]
76 pub mod AIEN {
77 pub const offset: u32 = 7;
78 pub const mask: u32 = 0x01 << offset;
79 pub mod R {}
80 pub mod W {}
81 pub mod RW {
82 #[doc = "Conversion complete interrupt disabled"]
83 pub const AIEN_0: u32 = 0;
84 #[doc = "Conversion complete interrupt enabled"]
85 pub const AIEN_1: u32 = 0x01;
86 }
87 }
88}
89#[doc = "Status register for HW triggers"]
90pub mod HS {
91 #[doc = "Conversion Complete Flag"]
92 pub mod COCO0 {
93 pub const offset: u32 = 0;
94 pub const mask: u32 = 0x01 << offset;
95 pub mod R {}
96 pub mod W {}
97 pub mod RW {}
98 }
99}
100#[doc = "Data result register for HW triggers"]
101pub mod R0 {
102 #[doc = "Data (result of an ADC conversion)"]
103 pub mod CDATA {
104 pub const offset: u32 = 0;
105 pub const mask: u32 = 0x0fff << offset;
106 pub mod R {}
107 pub mod W {}
108 pub mod RW {}
109 }
110}
111#[doc = "Data result register for HW triggers"]
112pub mod R {
113 #[doc = "Data (result of an ADC conversion)"]
114 pub mod CDATA {
115 pub const offset: u32 = 0;
116 pub const mask: u32 = 0x0fff << offset;
117 pub mod R {}
118 pub mod W {}
119 pub mod RW {}
120 }
121}
122#[doc = "Configuration register"]
123pub mod CFG {
124 #[doc = "Input Clock Select"]
125 pub mod ADICLK {
126 pub const offset: u32 = 0;
127 pub const mask: u32 = 0x03 << offset;
128 pub mod R {}
129 pub mod W {}
130 pub mod RW {
131 #[doc = "IPG clock"]
132 pub const ADICLK_0: u32 = 0;
133 #[doc = "IPG clock divided by 2"]
134 pub const ADICLK_1: u32 = 0x01;
135 #[doc = "Alternate clock (ALTCLK)"]
136 pub const ADICLK_2: u32 = 0x02;
137 #[doc = "Asynchronous clock (ADACK)"]
138 pub const ADICLK_3: u32 = 0x03;
139 }
140 }
141 #[doc = "Conversion Mode Selection"]
142 pub mod MODE {
143 pub const offset: u32 = 2;
144 pub const mask: u32 = 0x03 << offset;
145 pub mod R {}
146 pub mod W {}
147 pub mod RW {
148 #[doc = "8-bit conversion"]
149 pub const MODE_0: u32 = 0;
150 #[doc = "10-bit conversion"]
151 pub const MODE_1: u32 = 0x01;
152 #[doc = "12-bit conversion"]
153 pub const MODE_2: u32 = 0x02;
154 }
155 }
156 #[doc = "Long Sample Time Configuration"]
157 pub mod ADLSMP {
158 pub const offset: u32 = 4;
159 pub const mask: u32 = 0x01 << offset;
160 pub mod R {}
161 pub mod W {}
162 pub mod RW {
163 #[doc = "Short sample mode."]
164 pub const ADLSMP_0: u32 = 0;
165 #[doc = "Long sample mode."]
166 pub const ADLSMP_1: u32 = 0x01;
167 }
168 }
169 #[doc = "Clock Divide Select"]
170 pub mod ADIV {
171 pub const offset: u32 = 5;
172 pub const mask: u32 = 0x03 << offset;
173 pub mod R {}
174 pub mod W {}
175 pub mod RW {
176 #[doc = "Input clock"]
177 pub const ADIV_0: u32 = 0;
178 #[doc = "Input clock / 2"]
179 pub const ADIV_1: u32 = 0x01;
180 #[doc = "Input clock / 4"]
181 pub const ADIV_2: u32 = 0x02;
182 #[doc = "Input clock / 8"]
183 pub const ADIV_3: u32 = 0x03;
184 }
185 }
186 #[doc = "Low-Power Configuration"]
187 pub mod ADLPC {
188 pub const offset: u32 = 7;
189 pub const mask: u32 = 0x01 << offset;
190 pub mod R {}
191 pub mod W {}
192 pub mod RW {
193 #[doc = "ADC hard block not in low power mode."]
194 pub const ADLPC_0: u32 = 0;
195 #[doc = "ADC hard block in low power mode."]
196 pub const ADLPC_1: u32 = 0x01;
197 }
198 }
199 #[doc = "Defines the sample time duration"]
200 pub mod ADSTS {
201 pub const offset: u32 = 8;
202 pub const mask: u32 = 0x03 << offset;
203 pub mod R {}
204 pub mod W {}
205 pub mod RW {
206 #[doc = "Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b"]
207 pub const ADSTS_0: u32 = 0;
208 #[doc = "Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b"]
209 pub const ADSTS_1: u32 = 0x01;
210 #[doc = "Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b"]
211 pub const ADSTS_2: u32 = 0x02;
212 #[doc = "Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b"]
213 pub const ADSTS_3: u32 = 0x03;
214 }
215 }
216 #[doc = "High Speed Configuration"]
217 pub mod ADHSC {
218 pub const offset: u32 = 10;
219 pub const mask: u32 = 0x01 << offset;
220 pub mod R {}
221 pub mod W {}
222 pub mod RW {
223 #[doc = "Normal conversion selected."]
224 pub const ADHSC_0: u32 = 0;
225 #[doc = "High speed conversion selected."]
226 pub const ADHSC_1: u32 = 0x01;
227 }
228 }
229 #[doc = "Voltage Reference Selection"]
230 pub mod REFSEL {
231 pub const offset: u32 = 11;
232 pub const mask: u32 = 0x03 << offset;
233 pub mod R {}
234 pub mod W {}
235 pub mod RW {
236 #[doc = "Selects VREFH/VREFL as reference voltage."]
237 pub const REFSEL_0: u32 = 0;
238 }
239 }
240 #[doc = "Conversion Trigger Select"]
241 pub mod ADTRG {
242 pub const offset: u32 = 13;
243 pub const mask: u32 = 0x01 << offset;
244 pub mod R {}
245 pub mod W {}
246 pub mod RW {
247 #[doc = "Software trigger selected"]
248 pub const ADTRG_0: u32 = 0;
249 #[doc = "Hardware trigger selected"]
250 pub const ADTRG_1: u32 = 0x01;
251 }
252 }
253 #[doc = "Hardware Average select"]
254 pub mod AVGS {
255 pub const offset: u32 = 14;
256 pub const mask: u32 = 0x03 << offset;
257 pub mod R {}
258 pub mod W {}
259 pub mod RW {
260 #[doc = "4 samples averaged"]
261 pub const AVGS_0: u32 = 0;
262 #[doc = "8 samples averaged"]
263 pub const AVGS_1: u32 = 0x01;
264 #[doc = "16 samples averaged"]
265 pub const AVGS_2: u32 = 0x02;
266 #[doc = "32 samples averaged"]
267 pub const AVGS_3: u32 = 0x03;
268 }
269 }
270 #[doc = "Data Overwrite Enable"]
271 pub mod OVWREN {
272 pub const offset: u32 = 16;
273 pub const mask: u32 = 0x01 << offset;
274 pub mod R {}
275 pub mod W {}
276 pub mod RW {
277 #[doc = "Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data."]
278 pub const OVWREN_0: u32 = 0;
279 #[doc = "Enable the overwriting."]
280 pub const OVWREN_1: u32 = 0x01;
281 }
282 }
283}
284#[doc = "General control register"]
285pub mod GC {
286 #[doc = "Asynchronous clock output enable"]
287 pub mod ADACKEN {
288 pub const offset: u32 = 0;
289 pub const mask: u32 = 0x01 << offset;
290 pub mod R {}
291 pub mod W {}
292 pub mod RW {
293 #[doc = "Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active."]
294 pub const ADACKEN_0: u32 = 0;
295 #[doc = "Asynchronous clock and clock output enabled regardless of the state of the ADC"]
296 pub const ADACKEN_1: u32 = 0x01;
297 }
298 }
299 #[doc = "DMA Enable"]
300 pub mod DMAEN {
301 pub const offset: u32 = 1;
302 pub const mask: u32 = 0x01 << offset;
303 pub mod R {}
304 pub mod W {}
305 pub mod RW {
306 #[doc = "DMA disabled (default)"]
307 pub const DMAEN_0: u32 = 0;
308 #[doc = "DMA enabled"]
309 pub const DMAEN_1: u32 = 0x01;
310 }
311 }
312 #[doc = "Compare Function Range Enable"]
313 pub mod ACREN {
314 pub const offset: u32 = 2;
315 pub const mask: u32 = 0x01 << offset;
316 pub mod R {}
317 pub mod W {}
318 pub mod RW {
319 #[doc = "Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared."]
320 pub const ACREN_0: u32 = 0;
321 #[doc = "Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared."]
322 pub const ACREN_1: u32 = 0x01;
323 }
324 }
325 #[doc = "Compare Function Greater Than Enable"]
326 pub mod ACFGT {
327 pub const offset: u32 = 3;
328 pub const mask: u32 = 0x01 << offset;
329 pub mod R {}
330 pub mod W {}
331 pub mod RW {
332 #[doc = "Configures \"Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive\" functionality based on the values placed in the ADC_CV register."]
333 pub const ACFGT_0: u32 = 0;
334 #[doc = "Configures \"Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive\" functionality based on the values placed in the ADC_CV registers."]
335 pub const ACFGT_1: u32 = 0x01;
336 }
337 }
338 #[doc = "Compare Function Enable"]
339 pub mod ACFE {
340 pub const offset: u32 = 4;
341 pub const mask: u32 = 0x01 << offset;
342 pub mod R {}
343 pub mod W {}
344 pub mod RW {
345 #[doc = "Compare function disabled"]
346 pub const ACFE_0: u32 = 0;
347 #[doc = "Compare function enabled"]
348 pub const ACFE_1: u32 = 0x01;
349 }
350 }
351 #[doc = "Hardware average enable"]
352 pub mod AVGE {
353 pub const offset: u32 = 5;
354 pub const mask: u32 = 0x01 << offset;
355 pub mod R {}
356 pub mod W {}
357 pub mod RW {
358 #[doc = "Hardware average function disabled"]
359 pub const AVGE_0: u32 = 0;
360 #[doc = "Hardware average function enabled"]
361 pub const AVGE_1: u32 = 0x01;
362 }
363 }
364 #[doc = "Continuous Conversion Enable"]
365 pub mod ADCO {
366 pub const offset: u32 = 6;
367 pub const mask: u32 = 0x01 << offset;
368 pub mod R {}
369 pub mod W {}
370 pub mod RW {
371 #[doc = "One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
372 pub const ADCO_0: u32 = 0;
373 #[doc = "Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
374 pub const ADCO_1: u32 = 0x01;
375 }
376 }
377 #[doc = "Calibration"]
378 pub mod CAL {
379 pub const offset: u32 = 7;
380 pub const mask: u32 = 0x01 << offset;
381 pub mod R {}
382 pub mod W {}
383 pub mod RW {}
384 }
385}
386#[doc = "General status register"]
387pub mod GS {
388 #[doc = "Conversion Active"]
389 pub mod ADACT {
390 pub const offset: u32 = 0;
391 pub const mask: u32 = 0x01 << offset;
392 pub mod R {}
393 pub mod W {}
394 pub mod RW {
395 #[doc = "Conversion not in progress."]
396 pub const ADACT_0: u32 = 0;
397 #[doc = "Conversion in progress."]
398 pub const ADACT_1: u32 = 0x01;
399 }
400 }
401 #[doc = "Calibration Failed Flag"]
402 pub mod CALF {
403 pub const offset: u32 = 1;
404 pub const mask: u32 = 0x01 << offset;
405 pub mod R {}
406 pub mod W {}
407 pub mod RW {
408 #[doc = "Calibration completed normally."]
409 pub const CALF_0: u32 = 0;
410 #[doc = "Calibration failed. ADC accuracy specifications are not guaranteed."]
411 pub const CALF_1: u32 = 0x01;
412 }
413 }
414 #[doc = "Asynchronous wakeup interrupt status"]
415 pub mod AWKST {
416 pub const offset: u32 = 2;
417 pub const mask: u32 = 0x01 << offset;
418 pub mod R {}
419 pub mod W {}
420 pub mod RW {
421 #[doc = "No asynchronous interrupt."]
422 pub const AWKST_0: u32 = 0;
423 #[doc = "Asynchronous wake up interrupt occurred in stop mode."]
424 pub const AWKST_1: u32 = 0x01;
425 }
426 }
427}
428#[doc = "Compare value register"]
429pub mod CV {
430 #[doc = "Compare Value 1"]
431 pub mod CV1 {
432 pub const offset: u32 = 0;
433 pub const mask: u32 = 0x0fff << offset;
434 pub mod R {}
435 pub mod W {}
436 pub mod RW {}
437 }
438 #[doc = "Compare Value 2"]
439 pub mod CV2 {
440 pub const offset: u32 = 16;
441 pub const mask: u32 = 0x0fff << offset;
442 pub mod R {}
443 pub mod W {}
444 pub mod RW {}
445 }
446}
447#[doc = "Offset correction value register"]
448pub mod OFS {
449 #[doc = "Offset value"]
450 pub mod OFS {
451 pub const offset: u32 = 0;
452 pub const mask: u32 = 0x0fff << offset;
453 pub mod R {}
454 pub mod W {}
455 pub mod RW {}
456 }
457 #[doc = "Sign bit"]
458 pub mod SIGN {
459 pub const offset: u32 = 12;
460 pub const mask: u32 = 0x01 << offset;
461 pub mod R {}
462 pub mod W {}
463 pub mod RW {
464 #[doc = "The offset value is added with the raw result"]
465 pub const SIGN_0: u32 = 0;
466 #[doc = "The offset value is subtracted from the raw converted value"]
467 pub const SIGN_1: u32 = 0x01;
468 }
469 }
470}
471#[doc = "Calibration value register"]
472pub mod CAL {
473 #[doc = "Calibration Result Value"]
474 pub mod CAL_CODE {
475 pub const offset: u32 = 0;
476 pub const mask: u32 = 0x0f << offset;
477 pub mod R {}
478 pub mod W {}
479 pub mod RW {}
480 }
481}