1#[doc = "Register `GPIO_HI_OE` reader"]
2pub type R = crate::R<GPIO_HI_OE_SPEC>;
3#[doc = "Register `GPIO_HI_OE` writer"]
4pub type W = crate::W<GPIO_HI_OE_SPEC>;
5#[doc = "Field `GPIO_HI_OE` reader - Set output enable (1/0 -> output/input) for QSPI IO0...5.
6 Reading back gives the last value written.
7 If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),
8 the result is as though the write from core 0 took place first,
9 and the write from core 1 was then applied to that intermediate result."]
10pub type GPIO_HI_OE_R = crate::FieldReader;
11#[doc = "Field `GPIO_HI_OE` writer - Set output enable (1/0 -> output/input) for QSPI IO0...5.
12 Reading back gives the last value written.
13 If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),
14 the result is as though the write from core 0 took place first,
15 and the write from core 1 was then applied to that intermediate result."]
16pub type GPIO_HI_OE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17impl R {
18#[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5.
19 Reading back gives the last value written.
20 If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),
21 the result is as though the write from core 0 took place first,
22 and the write from core 1 was then applied to that intermediate result."]
23 #[inline(always)]
24pub fn gpio_hi_oe(&self) -> GPIO_HI_OE_R {
25 GPIO_HI_OE_R::new((self.bits & 0x3f) as u8)
26 }
27}
28impl W {
29#[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5.
30 Reading back gives the last value written.
31 If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),
32 the result is as though the write from core 0 took place first,
33 and the write from core 1 was then applied to that intermediate result."]
34 #[inline(always)]
35 #[must_use]
36pub fn gpio_hi_oe(&mut self) -> GPIO_HI_OE_W<GPIO_HI_OE_SPEC> {
37 GPIO_HI_OE_W::new(self, 0)
38 }
39#[doc = r" Writes raw bits to the register."]
40 #[doc = r""]
41 #[doc = r" # Safety"]
42 #[doc = r""]
43 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
44 #[inline(always)]
45pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
46self.bits = bits;
47self
48}
49}
50#[doc = "QSPI output enable
5152You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
53pub struct GPIO_HI_OE_SPEC;
54impl crate::RegisterSpec for GPIO_HI_OE_SPEC {
55type Ux = u32;
56}
57#[doc = "`read()` method returns [`gpio_hi_oe::R`](R) reader structure"]
58impl crate::Readable for GPIO_HI_OE_SPEC {}
59#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe::W`](W) writer structure"]
60impl crate::Writable for GPIO_HI_OE_SPEC {
61const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63}
64#[doc = "`reset()` method sets GPIO_HI_OE to value 0"]
65impl crate::Resettable for GPIO_HI_OE_SPEC {
66const RESET_VALUE: u32 = 0;
67}