rp2040_pac/adc/
div.rs

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1#[doc = "Register `DIV` reader"]
2pub type R = crate::R<DIV_SPEC>;
3#[doc = "Register `DIV` writer"]
4pub type W = crate::W<DIV_SPEC>;
5#[doc = "Field `FRAC` reader - Fractional part of clock divisor. First-order delta-sigma."]
6pub type FRAC_R = crate::FieldReader;
7#[doc = "Field `FRAC` writer - Fractional part of clock divisor. First-order delta-sigma."]
8pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `INT` reader - Integer part of clock divisor."]
10pub type INT_R = crate::FieldReader<u16>;
11#[doc = "Field `INT` writer - Integer part of clock divisor."]
12pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."]
15    #[inline(always)]
16    pub fn frac(&self) -> FRAC_R {
17        FRAC_R::new((self.bits & 0xff) as u8)
18    }
19    #[doc = "Bits 8:23 - Integer part of clock divisor."]
20    #[inline(always)]
21    pub fn int(&self) -> INT_R {
22        INT_R::new(((self.bits >> 8) & 0xffff) as u16)
23    }
24}
25impl W {
26    #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."]
27    #[inline(always)]
28    #[must_use]
29    pub fn frac(&mut self) -> FRAC_W<DIV_SPEC> {
30        FRAC_W::new(self, 0)
31    }
32    #[doc = "Bits 8:23 - Integer part of clock divisor."]
33    #[inline(always)]
34    #[must_use]
35    pub fn int(&mut self) -> INT_W<DIV_SPEC> {
36        INT_W::new(self, 8)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions  
50 at regular intervals rather than back-to-back.  
51 The divider is reset when either of these fields are written.  
52 Total period is 1 + INT + FRAC / 256  
53
54You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct DIV_SPEC;
56impl crate::RegisterSpec for DIV_SPEC {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`div::R`](R) reader structure"]
60impl crate::Readable for DIV_SPEC {}
61#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"]
62impl crate::Writable for DIV_SPEC {
63    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
64    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65}
66#[doc = "`reset()` method sets DIV to value 0"]
67impl crate::Resettable for DIV_SPEC {
68    const RESET_VALUE: u32 = 0;
69}
rp2040_pac/adc/div.rs

rp2040_pac/adc/
div.rs
