imxrt_ral/blocks/imxrt1011/
usbphy.rs

Help
1#[doc = "USBPHY Register Reference Index"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "USB PHY Power-Down Register"]
5    pub PWD: crate::RWRegister<u32>,
6    #[doc = "USB PHY Power-Down Register"]
7    pub PWD_SET: crate::RWRegister<u32>,
8    #[doc = "USB PHY Power-Down Register"]
9    pub PWD_CLR: crate::RWRegister<u32>,
10    #[doc = "USB PHY Power-Down Register"]
11    pub PWD_TOG: crate::RWRegister<u32>,
12    #[doc = "USB PHY Transmitter Control Register"]
13    pub TX: crate::RWRegister<u32>,
14    #[doc = "USB PHY Transmitter Control Register"]
15    pub TX_SET: crate::RWRegister<u32>,
16    #[doc = "USB PHY Transmitter Control Register"]
17    pub TX_CLR: crate::RWRegister<u32>,
18    #[doc = "USB PHY Transmitter Control Register"]
19    pub TX_TOG: crate::RWRegister<u32>,
20    #[doc = "USB PHY Receiver Control Register"]
21    pub RX: crate::RWRegister<u32>,
22    #[doc = "USB PHY Receiver Control Register"]
23    pub RX_SET: crate::RWRegister<u32>,
24    #[doc = "USB PHY Receiver Control Register"]
25    pub RX_CLR: crate::RWRegister<u32>,
26    #[doc = "USB PHY Receiver Control Register"]
27    pub RX_TOG: crate::RWRegister<u32>,
28    #[doc = "USB PHY General Control Register"]
29    pub CTRL: crate::RWRegister<u32>,
30    #[doc = "USB PHY General Control Register"]
31    pub CTRL_SET: crate::RWRegister<u32>,
32    #[doc = "USB PHY General Control Register"]
33    pub CTRL_CLR: crate::RWRegister<u32>,
34    #[doc = "USB PHY General Control Register"]
35    pub CTRL_TOG: crate::RWRegister<u32>,
36    #[doc = "USB PHY Status Register"]
37    pub STATUS: crate::RWRegister<u32>,
38    _reserved0: [u8; 0x0c],
39    #[doc = "USB PHY Debug Register"]
40    pub DEBUG: crate::RWRegister<u32>,
41    #[doc = "USB PHY Debug Register"]
42    pub DEBUG_SET: crate::RWRegister<u32>,
43    #[doc = "USB PHY Debug Register"]
44    pub DEBUG_CLR: crate::RWRegister<u32>,
45    #[doc = "USB PHY Debug Register"]
46    pub DEBUG_TOG: crate::RWRegister<u32>,
47    #[doc = "UTMI Debug Status Register 0"]
48    pub DEBUG0_STATUS: crate::RORegister<u32>,
49    _reserved1: [u8; 0x0c],
50    #[doc = "UTMI Debug Status Register 1"]
51    pub DEBUG1: crate::RWRegister<u32>,
52    #[doc = "UTMI Debug Status Register 1"]
53    pub DEBUG1_SET: crate::RWRegister<u32>,
54    #[doc = "UTMI Debug Status Register 1"]
55    pub DEBUG1_CLR: crate::RWRegister<u32>,
56    #[doc = "UTMI Debug Status Register 1"]
57    pub DEBUG1_TOG: crate::RWRegister<u32>,
58    #[doc = "UTMI RTL Version"]
59    pub VERSION: crate::RORegister<u32>,
60}
61#[doc = "USB PHY Power-Down Register"]
62pub mod PWD {
63    #[doc = "Reserved."]
64    pub mod RSVD0 {
65        pub const offset: u32 = 0;
66        pub const mask: u32 = 0x03ff << offset;
67        pub mod R {}
68        pub mod W {}
69        pub mod RW {}
70    }
71    #[doc = "0 = Normal operation"]
72    pub mod TXPWDFS {
73        pub const offset: u32 = 10;
74        pub const mask: u32 = 0x01 << offset;
75        pub mod R {}
76        pub mod W {}
77        pub mod RW {}
78    }
79    #[doc = "0 = Normal operation"]
80    pub mod TXPWDIBIAS {
81        pub const offset: u32 = 11;
82        pub const mask: u32 = 0x01 << offset;
83        pub mod R {}
84        pub mod W {}
85        pub mod RW {}
86    }
87    #[doc = "0 = Normal operation"]
88    pub mod TXPWDV2I {
89        pub const offset: u32 = 12;
90        pub const mask: u32 = 0x01 << offset;
91        pub mod R {}
92        pub mod W {}
93        pub mod RW {}
94    }
95    #[doc = "Reserved."]
96    pub mod RSVD1 {
97        pub const offset: u32 = 13;
98        pub const mask: u32 = 0x0f << offset;
99        pub mod R {}
100        pub mod W {}
101        pub mod RW {}
102    }
103    #[doc = "0 = Normal operation"]
104    pub mod RXPWDENV {
105        pub const offset: u32 = 17;
106        pub const mask: u32 = 0x01 << offset;
107        pub mod R {}
108        pub mod W {}
109        pub mod RW {}
110    }
111    #[doc = "0 = Normal operation"]
112    pub mod RXPWD1PT1 {
113        pub const offset: u32 = 18;
114        pub const mask: u32 = 0x01 << offset;
115        pub mod R {}
116        pub mod W {}
117        pub mod RW {}
118    }
119    #[doc = "0 = Normal operation"]
120    pub mod RXPWDDIFF {
121        pub const offset: u32 = 19;
122        pub const mask: u32 = 0x01 << offset;
123        pub mod R {}
124        pub mod W {}
125        pub mod RW {}
126    }
127    #[doc = "0 = Normal operation"]
128    pub mod RXPWDRX {
129        pub const offset: u32 = 20;
130        pub const mask: u32 = 0x01 << offset;
131        pub mod R {}
132        pub mod W {}
133        pub mod RW {}
134    }
135    #[doc = "Reserved."]
136    pub mod RSVD2 {
137        pub const offset: u32 = 21;
138        pub const mask: u32 = 0x07ff << offset;
139        pub mod R {}
140        pub mod W {}
141        pub mod RW {}
142    }
143}
144#[doc = "USB PHY Power-Down Register"]
145pub mod PWD_SET {
146    #[doc = "Reserved."]
147    pub mod RSVD0 {
148        pub const offset: u32 = 0;
149        pub const mask: u32 = 0x03ff << offset;
150        pub mod R {}
151        pub mod W {}
152        pub mod RW {}
153    }
154    #[doc = "0 = Normal operation"]
155    pub mod TXPWDFS {
156        pub const offset: u32 = 10;
157        pub const mask: u32 = 0x01 << offset;
158        pub mod R {}
159        pub mod W {}
160        pub mod RW {}
161    }
162    #[doc = "0 = Normal operation"]
163    pub mod TXPWDIBIAS {
164        pub const offset: u32 = 11;
165        pub const mask: u32 = 0x01 << offset;
166        pub mod R {}
167        pub mod W {}
168        pub mod RW {}
169    }
170    #[doc = "0 = Normal operation"]
171    pub mod TXPWDV2I {
172        pub const offset: u32 = 12;
173        pub const mask: u32 = 0x01 << offset;
174        pub mod R {}
175        pub mod W {}
176        pub mod RW {}
177    }
178    #[doc = "Reserved."]
179    pub mod RSVD1 {
180        pub const offset: u32 = 13;
181        pub const mask: u32 = 0x0f << offset;
182        pub mod R {}
183        pub mod W {}
184        pub mod RW {}
185    }
186    #[doc = "0 = Normal operation"]
187    pub mod RXPWDENV {
188        pub const offset: u32 = 17;
189        pub const mask: u32 = 0x01 << offset;
190        pub mod R {}
191        pub mod W {}
192        pub mod RW {}
193    }
194    #[doc = "0 = Normal operation"]
195    pub mod RXPWD1PT1 {
196        pub const offset: u32 = 18;
197        pub const mask: u32 = 0x01 << offset;
198        pub mod R {}
199        pub mod W {}
200        pub mod RW {}
201    }
202    #[doc = "0 = Normal operation"]
203    pub mod RXPWDDIFF {
204        pub const offset: u32 = 19;
205        pub const mask: u32 = 0x01 << offset;
206        pub mod R {}
207        pub mod W {}
208        pub mod RW {}
209    }
210    #[doc = "0 = Normal operation"]
211    pub mod RXPWDRX {
212        pub const offset: u32 = 20;
213        pub const mask: u32 = 0x01 << offset;
214        pub mod R {}
215        pub mod W {}
216        pub mod RW {}
217    }
218    #[doc = "Reserved."]
219    pub mod RSVD2 {
220        pub const offset: u32 = 21;
221        pub const mask: u32 = 0x07ff << offset;
222        pub mod R {}
223        pub mod W {}
224        pub mod RW {}
225    }
226}
227#[doc = "USB PHY Power-Down Register"]
228pub mod PWD_CLR {
229    #[doc = "Reserved."]
230    pub mod RSVD0 {
231        pub const offset: u32 = 0;
232        pub const mask: u32 = 0x03ff << offset;
233        pub mod R {}
234        pub mod W {}
235        pub mod RW {}
236    }
237    #[doc = "0 = Normal operation"]
238    pub mod TXPWDFS {
239        pub const offset: u32 = 10;
240        pub const mask: u32 = 0x01 << offset;
241        pub mod R {}
242        pub mod W {}
243        pub mod RW {}
244    }
245    #[doc = "0 = Normal operation"]
246    pub mod TXPWDIBIAS {
247        pub const offset: u32 = 11;
248        pub const mask: u32 = 0x01 << offset;
249        pub mod R {}
250        pub mod W {}
251        pub mod RW {}
252    }
253    #[doc = "0 = Normal operation"]
254    pub mod TXPWDV2I {
255        pub const offset: u32 = 12;
256        pub const mask: u32 = 0x01 << offset;
257        pub mod R {}
258        pub mod W {}
259        pub mod RW {}
260    }
261    #[doc = "Reserved."]
262    pub mod RSVD1 {
263        pub const offset: u32 = 13;
264        pub const mask: u32 = 0x0f << offset;
265        pub mod R {}
266        pub mod W {}
267        pub mod RW {}
268    }
269    #[doc = "0 = Normal operation"]
270    pub mod RXPWDENV {
271        pub const offset: u32 = 17;
272        pub const mask: u32 = 0x01 << offset;
273        pub mod R {}
274        pub mod W {}
275        pub mod RW {}
276    }
277    #[doc = "0 = Normal operation"]
278    pub mod RXPWD1PT1 {
279        pub const offset: u32 = 18;
280        pub const mask: u32 = 0x01 << offset;
281        pub mod R {}
282        pub mod W {}
283        pub mod RW {}
284    }
285    #[doc = "0 = Normal operation"]
286    pub mod RXPWDDIFF {
287        pub const offset: u32 = 19;
288        pub const mask: u32 = 0x01 << offset;
289        pub mod R {}
290        pub mod W {}
291        pub mod RW {}
292    }
293    #[doc = "0 = Normal operation"]
294    pub mod RXPWDRX {
295        pub const offset: u32 = 20;
296        pub const mask: u32 = 0x01 << offset;
297        pub mod R {}
298        pub mod W {}
299        pub mod RW {}
300    }
301    #[doc = "Reserved."]
302    pub mod RSVD2 {
303        pub const offset: u32 = 21;
304        pub const mask: u32 = 0x07ff << offset;
305        pub mod R {}
306        pub mod W {}
307        pub mod RW {}
308    }
309}
310#[doc = "USB PHY Power-Down Register"]
311pub mod PWD_TOG {
312    #[doc = "Reserved."]
313    pub mod RSVD0 {
314        pub const offset: u32 = 0;
315        pub const mask: u32 = 0x03ff << offset;
316        pub mod R {}
317        pub mod W {}
318        pub mod RW {}
319    }
320    #[doc = "0 = Normal operation"]
321    pub mod TXPWDFS {
322        pub const offset: u32 = 10;
323        pub const mask: u32 = 0x01 << offset;
324        pub mod R {}
325        pub mod W {}
326        pub mod RW {}
327    }
328    #[doc = "0 = Normal operation"]
329    pub mod TXPWDIBIAS {
330        pub const offset: u32 = 11;
331        pub const mask: u32 = 0x01 << offset;
332        pub mod R {}
333        pub mod W {}
334        pub mod RW {}
335    }
336    #[doc = "0 = Normal operation"]
337    pub mod TXPWDV2I {
338        pub const offset: u32 = 12;
339        pub const mask: u32 = 0x01 << offset;
340        pub mod R {}
341        pub mod W {}
342        pub mod RW {}
343    }
344    #[doc = "Reserved."]
345    pub mod RSVD1 {
346        pub const offset: u32 = 13;
347        pub const mask: u32 = 0x0f << offset;
348        pub mod R {}
349        pub mod W {}
350        pub mod RW {}
351    }
352    #[doc = "0 = Normal operation"]
353    pub mod RXPWDENV {
354        pub const offset: u32 = 17;
355        pub const mask: u32 = 0x01 << offset;
356        pub mod R {}
357        pub mod W {}
358        pub mod RW {}
359    }
360    #[doc = "0 = Normal operation"]
361    pub mod RXPWD1PT1 {
362        pub const offset: u32 = 18;
363        pub const mask: u32 = 0x01 << offset;
364        pub mod R {}
365        pub mod W {}
366        pub mod RW {}
367    }
368    #[doc = "0 = Normal operation"]
369    pub mod RXPWDDIFF {
370        pub const offset: u32 = 19;
371        pub const mask: u32 = 0x01 << offset;
372        pub mod R {}
373        pub mod W {}
374        pub mod RW {}
375    }
376    #[doc = "0 = Normal operation"]
377    pub mod RXPWDRX {
378        pub const offset: u32 = 20;
379        pub const mask: u32 = 0x01 << offset;
380        pub mod R {}
381        pub mod W {}
382        pub mod RW {}
383    }
384    #[doc = "Reserved."]
385    pub mod RSVD2 {
386        pub const offset: u32 = 21;
387        pub const mask: u32 = 0x07ff << offset;
388        pub mod R {}
389        pub mod W {}
390        pub mod RW {}
391    }
392}
393#[doc = "USB PHY Transmitter Control Register"]
394pub mod TX {
395    #[doc = "Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%"]
396    pub mod D_CAL {
397        pub const offset: u32 = 0;
398        pub const mask: u32 = 0x0f << offset;
399        pub mod R {}
400        pub mod W {}
401        pub mod RW {}
402    }
403    #[doc = "Reserved. Note: This bit should remain clear."]
404    pub mod RSVD0 {
405        pub const offset: u32 = 4;
406        pub const mask: u32 = 0x0f << offset;
407        pub mod R {}
408        pub mod W {}
409        pub mod RW {}
410    }
411    #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"]
412    pub mod TXCAL45DN {
413        pub const offset: u32 = 8;
414        pub const mask: u32 = 0x0f << offset;
415        pub mod R {}
416        pub mod W {}
417        pub mod RW {}
418    }
419    #[doc = "Reserved. Note: This bit should remain clear."]
420    pub mod RSVD1 {
421        pub const offset: u32 = 12;
422        pub const mask: u32 = 0x0f << offset;
423        pub mod R {}
424        pub mod W {}
425        pub mod RW {}
426    }
427    #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"]
428    pub mod TXCAL45DP {
429        pub const offset: u32 = 16;
430        pub const mask: u32 = 0x0f << offset;
431        pub mod R {}
432        pub mod W {}
433        pub mod RW {}
434    }
435    #[doc = "Reserved."]
436    pub mod RSVD2 {
437        pub const offset: u32 = 20;
438        pub const mask: u32 = 0x3f << offset;
439        pub mod R {}
440        pub mod W {}
441        pub mod RW {}
442    }
443    #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"]
444    pub mod USBPHY_TX_EDGECTRL {
445        pub const offset: u32 = 26;
446        pub const mask: u32 = 0x07 << offset;
447        pub mod R {}
448        pub mod W {}
449        pub mod RW {}
450    }
451    #[doc = "Reserved."]
452    pub mod RSVD5 {
453        pub const offset: u32 = 29;
454        pub const mask: u32 = 0x07 << offset;
455        pub mod R {}
456        pub mod W {}
457        pub mod RW {}
458    }
459}
460#[doc = "USB PHY Transmitter Control Register"]
461pub mod TX_SET {
462    #[doc = "Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%"]
463    pub mod D_CAL {
464        pub const offset: u32 = 0;
465        pub const mask: u32 = 0x0f << offset;
466        pub mod R {}
467        pub mod W {}
468        pub mod RW {}
469    }
470    #[doc = "Reserved. Note: This bit should remain clear."]
471    pub mod RSVD0 {
472        pub const offset: u32 = 4;
473        pub const mask: u32 = 0x0f << offset;
474        pub mod R {}
475        pub mod W {}
476        pub mod RW {}
477    }
478    #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"]
479    pub mod TXCAL45DN {
480        pub const offset: u32 = 8;
481        pub const mask: u32 = 0x0f << offset;
482        pub mod R {}
483        pub mod W {}
484        pub mod RW {}
485    }
486    #[doc = "Reserved. Note: This bit should remain clear."]
487    pub mod RSVD1 {
488        pub const offset: u32 = 12;
489        pub const mask: u32 = 0x0f << offset;
490        pub mod R {}
491        pub mod W {}
492        pub mod RW {}
493    }
494    #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"]
495    pub mod TXCAL45DP {
496        pub const offset: u32 = 16;
497        pub const mask: u32 = 0x0f << offset;
498        pub mod R {}
499        pub mod W {}
500        pub mod RW {}
501    }
502    #[doc = "Reserved."]
503    pub mod RSVD2 {
504        pub const offset: u32 = 20;
505        pub const mask: u32 = 0x3f << offset;
506        pub mod R {}
507        pub mod W {}
508        pub mod RW {}
509    }
510    #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"]
511    pub mod USBPHY_TX_EDGECTRL {
512        pub const offset: u32 = 26;
513        pub const mask: u32 = 0x07 << offset;
514        pub mod R {}
515        pub mod W {}
516        pub mod RW {}
517    }
518    #[doc = "Reserved."]
519    pub mod RSVD5 {
520        pub const offset: u32 = 29;
521        pub const mask: u32 = 0x07 << offset;
522        pub mod R {}
523        pub mod W {}
524        pub mod RW {}
525    }
526}
527#[doc = "USB PHY Transmitter Control Register"]
528pub mod TX_CLR {
529    #[doc = "Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%"]
530    pub mod D_CAL {
531        pub const offset: u32 = 0;
532        pub const mask: u32 = 0x0f << offset;
533        pub mod R {}
534        pub mod W {}
535        pub mod RW {}
536    }
537    #[doc = "Reserved. Note: This bit should remain clear."]
538    pub mod RSVD0 {
539        pub const offset: u32 = 4;
540        pub const mask: u32 = 0x0f << offset;
541        pub mod R {}
542        pub mod W {}
543        pub mod RW {}
544    }
545    #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"]
546    pub mod TXCAL45DN {
547        pub const offset: u32 = 8;
548        pub const mask: u32 = 0x0f << offset;
549        pub mod R {}
550        pub mod W {}
551        pub mod RW {}
552    }
553    #[doc = "Reserved. Note: This bit should remain clear."]
554    pub mod RSVD1 {
555        pub const offset: u32 = 12;
556        pub const mask: u32 = 0x0f << offset;
557        pub mod R {}
558        pub mod W {}
559        pub mod RW {}
560    }
561    #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"]
562    pub mod TXCAL45DP {
563        pub const offset: u32 = 16;
564        pub const mask: u32 = 0x0f << offset;
565        pub mod R {}
566        pub mod W {}
567        pub mod RW {}
568    }
569    #[doc = "Reserved."]
570    pub mod RSVD2 {
571        pub const offset: u32 = 20;
572        pub const mask: u32 = 0x3f << offset;
573        pub mod R {}
574        pub mod W {}
575        pub mod RW {}
576    }
577    #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"]
578    pub mod USBPHY_TX_EDGECTRL {
579        pub const offset: u32 = 26;
580        pub const mask: u32 = 0x07 << offset;
581        pub mod R {}
582        pub mod W {}
583        pub mod RW {}
584    }
585    #[doc = "Reserved."]
586    pub mod RSVD5 {
587        pub const offset: u32 = 29;
588        pub const mask: u32 = 0x07 << offset;
589        pub mod R {}
590        pub mod W {}
591        pub mod RW {}
592    }
593}
594#[doc = "USB PHY Transmitter Control Register"]
595pub mod TX_TOG {
596    #[doc = "Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%"]
597    pub mod D_CAL {
598        pub const offset: u32 = 0;
599        pub const mask: u32 = 0x0f << offset;
600        pub mod R {}
601        pub mod W {}
602        pub mod RW {}
603    }
604    #[doc = "Reserved. Note: This bit should remain clear."]
605    pub mod RSVD0 {
606        pub const offset: u32 = 4;
607        pub const mask: u32 = 0x0f << offset;
608        pub mod R {}
609        pub mod W {}
610        pub mod RW {}
611    }
612    #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"]
613    pub mod TXCAL45DN {
614        pub const offset: u32 = 8;
615        pub const mask: u32 = 0x0f << offset;
616        pub mod R {}
617        pub mod W {}
618        pub mod RW {}
619    }
620    #[doc = "Reserved. Note: This bit should remain clear."]
621    pub mod RSVD1 {
622        pub const offset: u32 = 12;
623        pub const mask: u32 = 0x0f << offset;
624        pub mod R {}
625        pub mod W {}
626        pub mod RW {}
627    }
628    #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"]
629    pub mod TXCAL45DP {
630        pub const offset: u32 = 16;
631        pub const mask: u32 = 0x0f << offset;
632        pub mod R {}
633        pub mod W {}
634        pub mod RW {}
635    }
636    #[doc = "Reserved."]
637    pub mod RSVD2 {
638        pub const offset: u32 = 20;
639        pub const mask: u32 = 0x3f << offset;
640        pub mod R {}
641        pub mod W {}
642        pub mod RW {}
643    }
644    #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"]
645    pub mod USBPHY_TX_EDGECTRL {
646        pub const offset: u32 = 26;
647        pub const mask: u32 = 0x07 << offset;
648        pub mod R {}
649        pub mod W {}
650        pub mod RW {}
651    }
652    #[doc = "Reserved."]
653    pub mod RSVD5 {
654        pub const offset: u32 = 29;
655        pub const mask: u32 = 0x07 << offset;
656        pub mod R {}
657        pub mod W {}
658        pub mod RW {}
659    }
660}
661#[doc = "USB PHY Receiver Control Register"]
662pub mod RX {
663    #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"]
664    pub mod ENVADJ {
665        pub const offset: u32 = 0;
666        pub const mask: u32 = 0x07 << offset;
667        pub mod R {}
668        pub mod W {}
669        pub mod RW {}
670    }
671    #[doc = "Reserved."]
672    pub mod RSVD0 {
673        pub const offset: u32 = 3;
674        pub const mask: u32 = 0x01 << offset;
675        pub mod R {}
676        pub mod W {}
677        pub mod RW {}
678    }
679    #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"]
680    pub mod DISCONADJ {
681        pub const offset: u32 = 4;
682        pub const mask: u32 = 0x07 << offset;
683        pub mod R {}
684        pub mod W {}
685        pub mod RW {}
686    }
687    #[doc = "Reserved."]
688    pub mod RSVD1 {
689        pub const offset: u32 = 7;
690        pub const mask: u32 = 0x7fff << offset;
691        pub mod R {}
692        pub mod W {}
693        pub mod RW {}
694    }
695    #[doc = "0 = Normal operation"]
696    pub mod RXDBYPASS {
697        pub const offset: u32 = 22;
698        pub const mask: u32 = 0x01 << offset;
699        pub mod R {}
700        pub mod W {}
701        pub mod RW {}
702    }
703    #[doc = "Reserved."]
704    pub mod RSVD2 {
705        pub const offset: u32 = 23;
706        pub const mask: u32 = 0x01ff << offset;
707        pub mod R {}
708        pub mod W {}
709        pub mod RW {}
710    }
711}
712#[doc = "USB PHY Receiver Control Register"]
713pub mod RX_SET {
714    #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"]
715    pub mod ENVADJ {
716        pub const offset: u32 = 0;
717        pub const mask: u32 = 0x07 << offset;
718        pub mod R {}
719        pub mod W {}
720        pub mod RW {}
721    }
722    #[doc = "Reserved."]
723    pub mod RSVD0 {
724        pub const offset: u32 = 3;
725        pub const mask: u32 = 0x01 << offset;
726        pub mod R {}
727        pub mod W {}
728        pub mod RW {}
729    }
730    #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"]
731    pub mod DISCONADJ {
732        pub const offset: u32 = 4;
733        pub const mask: u32 = 0x07 << offset;
734        pub mod R {}
735        pub mod W {}
736        pub mod RW {}
737    }
738    #[doc = "Reserved."]
739    pub mod RSVD1 {
740        pub const offset: u32 = 7;
741        pub const mask: u32 = 0x7fff << offset;
742        pub mod R {}
743        pub mod W {}
744        pub mod RW {}
745    }
746    #[doc = "0 = Normal operation"]
747    pub mod RXDBYPASS {
748        pub const offset: u32 = 22;
749        pub const mask: u32 = 0x01 << offset;
750        pub mod R {}
751        pub mod W {}
752        pub mod RW {}
753    }
754    #[doc = "Reserved."]
755    pub mod RSVD2 {
756        pub const offset: u32 = 23;
757        pub const mask: u32 = 0x01ff << offset;
758        pub mod R {}
759        pub mod W {}
760        pub mod RW {}
761    }
762}
763#[doc = "USB PHY Receiver Control Register"]
764pub mod RX_CLR {
765    #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"]
766    pub mod ENVADJ {
767        pub const offset: u32 = 0;
768        pub const mask: u32 = 0x07 << offset;
769        pub mod R {}
770        pub mod W {}
771        pub mod RW {}
772    }
773    #[doc = "Reserved."]
774    pub mod RSVD0 {
775        pub const offset: u32 = 3;
776        pub const mask: u32 = 0x01 << offset;
777        pub mod R {}
778        pub mod W {}
779        pub mod RW {}
780    }
781    #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"]
782    pub mod DISCONADJ {
783        pub const offset: u32 = 4;
784        pub const mask: u32 = 0x07 << offset;
785        pub mod R {}
786        pub mod W {}
787        pub mod RW {}
788    }
789    #[doc = "Reserved."]
790    pub mod RSVD1 {
791        pub const offset: u32 = 7;
792        pub const mask: u32 = 0x7fff << offset;
793        pub mod R {}
794        pub mod W {}
795        pub mod RW {}
796    }
797    #[doc = "0 = Normal operation"]
798    pub mod RXDBYPASS {
799        pub const offset: u32 = 22;
800        pub const mask: u32 = 0x01 << offset;
801        pub mod R {}
802        pub mod W {}
803        pub mod RW {}
804    }
805    #[doc = "Reserved."]
806    pub mod RSVD2 {
807        pub const offset: u32 = 23;
808        pub const mask: u32 = 0x01ff << offset;
809        pub mod R {}
810        pub mod W {}
811        pub mod RW {}
812    }
813}
814#[doc = "USB PHY Receiver Control Register"]
815pub mod RX_TOG {
816    #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"]
817    pub mod ENVADJ {
818        pub const offset: u32 = 0;
819        pub const mask: u32 = 0x07 << offset;
820        pub mod R {}
821        pub mod W {}
822        pub mod RW {}
823    }
824    #[doc = "Reserved."]
825    pub mod RSVD0 {
826        pub const offset: u32 = 3;
827        pub const mask: u32 = 0x01 << offset;
828        pub mod R {}
829        pub mod W {}
830        pub mod RW {}
831    }
832    #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"]
833    pub mod DISCONADJ {
834        pub const offset: u32 = 4;
835        pub const mask: u32 = 0x07 << offset;
836        pub mod R {}
837        pub mod W {}
838        pub mod RW {}
839    }
840    #[doc = "Reserved."]
841    pub mod RSVD1 {
842        pub const offset: u32 = 7;
843        pub const mask: u32 = 0x7fff << offset;
844        pub mod R {}
845        pub mod W {}
846        pub mod RW {}
847    }
848    #[doc = "0 = Normal operation"]
849    pub mod RXDBYPASS {
850        pub const offset: u32 = 22;
851        pub const mask: u32 = 0x01 << offset;
852        pub mod R {}
853        pub mod W {}
854        pub mod RW {}
855    }
856    #[doc = "Reserved."]
857    pub mod RSVD2 {
858        pub const offset: u32 = 23;
859        pub const mask: u32 = 0x01ff << offset;
860        pub mod R {}
861        pub mod W {}
862        pub mod RW {}
863    }
864}
865#[doc = "USB PHY General Control Register"]
866pub mod CTRL {
867    #[doc = "Enable OTG_ID_CHG_IRQ."]
868    pub mod ENOTG_ID_CHG_IRQ {
869        pub const offset: u32 = 0;
870        pub const mask: u32 = 0x01 << offset;
871        pub mod R {}
872        pub mod W {}
873        pub mod RW {}
874    }
875    #[doc = "For host mode, enables high-speed disconnect detector"]
876    pub mod ENHOSTDISCONDETECT {
877        pub const offset: u32 = 1;
878        pub const mask: u32 = 0x01 << offset;
879        pub mod R {}
880        pub mod W {}
881        pub mod RW {}
882    }
883    #[doc = "Enables interrupt for detection of disconnection to Device when in high-speed host mode"]
884    pub mod ENIRQHOSTDISCON {
885        pub const offset: u32 = 2;
886        pub const mask: u32 = 0x01 << offset;
887        pub mod R {}
888        pub mod W {}
889        pub mod RW {}
890    }
891    #[doc = "Indicates that the device has disconnected in high-speed mode"]
892    pub mod HOSTDISCONDETECT_IRQ {
893        pub const offset: u32 = 3;
894        pub const mask: u32 = 0x01 << offset;
895        pub mod R {}
896        pub mod W {}
897        pub mod RW {}
898    }
899    #[doc = "For device mode, enables 200-KOhm pullups for detecting connectivity to the host."]
900    pub mod ENDEVPLUGINDETECT {
901        pub const offset: u32 = 4;
902        pub const mask: u32 = 0x01 << offset;
903        pub mod R {}
904        pub mod W {}
905        pub mod RW {}
906    }
907    #[doc = "For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in"]
908    pub mod DEVPLUGIN_POLARITY {
909        pub const offset: u32 = 5;
910        pub const mask: u32 = 0x01 << offset;
911        pub mod R {}
912        pub mod W {}
913        pub mod RW {}
914    }
915    #[doc = "OTG ID change interrupt. Indicates the value of ID pin changed."]
916    pub mod OTG_ID_CHG_IRQ {
917        pub const offset: u32 = 6;
918        pub const mask: u32 = 0x01 << offset;
919        pub mod R {}
920        pub mod W {}
921        pub mod RW {}
922    }
923    #[doc = "Enables circuit to detect resistance of MiniAB ID pin."]
924    pub mod ENOTGIDDETECT {
925        pub const offset: u32 = 7;
926        pub const mask: u32 = 0x01 << offset;
927        pub mod R {}
928        pub mod W {}
929        pub mod RW {}
930    }
931    #[doc = "Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it"]
932    pub mod RESUMEIRQSTICKY {
933        pub const offset: u32 = 8;
934        pub const mask: u32 = 0x01 << offset;
935        pub mod R {}
936        pub mod W {}
937        pub mod RW {}
938    }
939    #[doc = "Enables interrupt for detection of a non-J state on the USB line"]
940    pub mod ENIRQRESUMEDETECT {
941        pub const offset: u32 = 9;
942        pub const mask: u32 = 0x01 << offset;
943        pub mod R {}
944        pub mod W {}
945        pub mod RW {}
946    }
947    #[doc = "Indicates that the host is sending a wake-up after suspend"]
948    pub mod RESUME_IRQ {
949        pub const offset: u32 = 10;
950        pub const mask: u32 = 0x01 << offset;
951        pub mod R {}
952        pub mod W {}
953        pub mod RW {}
954    }
955    #[doc = "Enables interrupt for the detection of connectivity to the USB line."]
956    pub mod ENIRQDEVPLUGIN {
957        pub const offset: u32 = 11;
958        pub const mask: u32 = 0x01 << offset;
959        pub mod R {}
960        pub mod W {}
961        pub mod RW {}
962    }
963    #[doc = "Indicates that the device is connected"]
964    pub mod DEVPLUGIN_IRQ {
965        pub const offset: u32 = 12;
966        pub const mask: u32 = 0x01 << offset;
967        pub mod R {}
968        pub mod W {}
969        pub mod RW {}
970    }
971    #[doc = "Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only."]
972    pub mod DATA_ON_LRADC {
973        pub const offset: u32 = 13;
974        pub const mask: u32 = 0x01 << offset;
975        pub mod R {}
976        pub mod W {}
977        pub mod RW {}
978    }
979    #[doc = "Enables UTMI+ Level2. This should be enabled if needs to support LS device"]
980    pub mod ENUTMILEVEL2 {
981        pub const offset: u32 = 14;
982        pub const mask: u32 = 0x01 << offset;
983        pub mod R {}
984        pub mod W {}
985        pub mod RW {}
986    }
987    #[doc = "Enables UTMI+ Level3"]
988    pub mod ENUTMILEVEL3 {
989        pub const offset: u32 = 15;
990        pub const mask: u32 = 0x01 << offset;
991        pub mod R {}
992        pub mod W {}
993        pub mod RW {}
994    }
995    #[doc = "Enables interrupt for the wakeup events."]
996    pub mod ENIRQWAKEUP {
997        pub const offset: u32 = 16;
998        pub const mask: u32 = 0x01 << offset;
999        pub mod R {}
1000        pub mod W {}
1001        pub mod RW {}
1002    }
1003    #[doc = "Indicates that there is a wakeup event"]
1004    pub mod WAKEUP_IRQ {
1005        pub const offset: u32 = 17;
1006        pub const mask: u32 = 0x01 << offset;
1007        pub mod R {}
1008        pub mod W {}
1009        pub mod RW {}
1010    }
1011    #[doc = "Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended"]
1012    pub mod ENAUTO_PWRON_PLL {
1013        pub const offset: u32 = 18;
1014        pub const mask: u32 = 0x01 << offset;
1015        pub mod R {}
1016        pub mod W {}
1017        pub mod RW {}
1018    }
1019    #[doc = "Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
1020    pub mod ENAUTOCLR_CLKGATE {
1021        pub const offset: u32 = 19;
1022        pub const mask: u32 = 0x01 << offset;
1023        pub mod R {}
1024        pub mod W {}
1025        pub mod RW {}
1026    }
1027    #[doc = "Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended"]
1028    pub mod ENAUTOCLR_PHY_PWD {
1029        pub const offset: u32 = 20;
1030        pub const mask: u32 = 0x01 << offset;
1031        pub mod R {}
1032        pub mod W {}
1033        pub mod RW {}
1034    }
1035    #[doc = "Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended"]
1036    pub mod ENDPDMCHG_WKUP {
1037        pub const offset: u32 = 21;
1038        pub const mask: u32 = 0x01 << offset;
1039        pub mod R {}
1040        pub mod W {}
1041        pub mod RW {}
1042    }
1043    #[doc = "Enables the feature to wakeup USB if ID is toggled when USB is suspended."]
1044    pub mod ENIDCHG_WKUP {
1045        pub const offset: u32 = 22;
1046        pub const mask: u32 = 0x01 << offset;
1047        pub mod R {}
1048        pub mod W {}
1049        pub mod RW {}
1050    }
1051    #[doc = "Enables the feature to wakeup USB if VBUS is toggled when USB is suspended."]
1052    pub mod ENVBUSCHG_WKUP {
1053        pub const offset: u32 = 23;
1054        pub const mask: u32 = 0x01 << offset;
1055        pub mod R {}
1056        pub mod W {}
1057        pub mod RW {}
1058    }
1059    #[doc = "Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
1060    pub mod FSDLL_RST_EN {
1061        pub const offset: u32 = 24;
1062        pub const mask: u32 = 0x01 << offset;
1063        pub mod R {}
1064        pub mod W {}
1065        pub mod RW {}
1066    }
1067    #[doc = "Reserved."]
1068    pub mod RSVD1 {
1069        pub const offset: u32 = 25;
1070        pub const mask: u32 = 0x03 << offset;
1071        pub mod R {}
1072        pub mod W {}
1073        pub mod RW {}
1074    }
1075    #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"]
1076    pub mod OTG_ID_VALUE {
1077        pub const offset: u32 = 27;
1078        pub const mask: u32 = 0x01 << offset;
1079        pub mod R {}
1080        pub mod W {}
1081        pub mod RW {}
1082    }
1083    #[doc = "Forces the next FS packet that is transmitted to have a EOP with LS timing"]
1084    pub mod HOST_FORCE_LS_SE0 {
1085        pub const offset: u32 = 28;
1086        pub const mask: u32 = 0x01 << offset;
1087        pub mod R {}
1088        pub mod W {}
1089        pub mod RW {}
1090    }
1091    #[doc = "Used by the PHY to indicate a powered-down state"]
1092    pub mod UTMI_SUSPENDM {
1093        pub const offset: u32 = 29;
1094        pub const mask: u32 = 0x01 << offset;
1095        pub mod R {}
1096        pub mod W {}
1097        pub mod RW {}
1098    }
1099    #[doc = "Gate UTMI Clocks"]
1100    pub mod CLKGATE {
1101        pub const offset: u32 = 30;
1102        pub const mask: u32 = 0x01 << offset;
1103        pub mod R {}
1104        pub mod W {}
1105        pub mod RW {}
1106    }
1107    #[doc = "Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers"]
1108    pub mod SFTRST {
1109        pub const offset: u32 = 31;
1110        pub const mask: u32 = 0x01 << offset;
1111        pub mod R {}
1112        pub mod W {}
1113        pub mod RW {}
1114    }
1115}
1116#[doc = "USB PHY General Control Register"]
1117pub mod CTRL_SET {
1118    #[doc = "Enable OTG_ID_CHG_IRQ."]
1119    pub mod ENOTG_ID_CHG_IRQ {
1120        pub const offset: u32 = 0;
1121        pub const mask: u32 = 0x01 << offset;
1122        pub mod R {}
1123        pub mod W {}
1124        pub mod RW {}
1125    }
1126    #[doc = "For host mode, enables high-speed disconnect detector"]
1127    pub mod ENHOSTDISCONDETECT {
1128        pub const offset: u32 = 1;
1129        pub const mask: u32 = 0x01 << offset;
1130        pub mod R {}
1131        pub mod W {}
1132        pub mod RW {}
1133    }
1134    #[doc = "Enables interrupt for detection of disconnection to Device when in high-speed host mode"]
1135    pub mod ENIRQHOSTDISCON {
1136        pub const offset: u32 = 2;
1137        pub const mask: u32 = 0x01 << offset;
1138        pub mod R {}
1139        pub mod W {}
1140        pub mod RW {}
1141    }
1142    #[doc = "Indicates that the device has disconnected in high-speed mode"]
1143    pub mod HOSTDISCONDETECT_IRQ {
1144        pub const offset: u32 = 3;
1145        pub const mask: u32 = 0x01 << offset;
1146        pub mod R {}
1147        pub mod W {}
1148        pub mod RW {}
1149    }
1150    #[doc = "For device mode, enables 200-KOhm pullups for detecting connectivity to the host."]
1151    pub mod ENDEVPLUGINDETECT {
1152        pub const offset: u32 = 4;
1153        pub const mask: u32 = 0x01 << offset;
1154        pub mod R {}
1155        pub mod W {}
1156        pub mod RW {}
1157    }
1158    #[doc = "For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in"]
1159    pub mod DEVPLUGIN_POLARITY {
1160        pub const offset: u32 = 5;
1161        pub const mask: u32 = 0x01 << offset;
1162        pub mod R {}
1163        pub mod W {}
1164        pub mod RW {}
1165    }
1166    #[doc = "OTG ID change interrupt. Indicates the value of ID pin changed."]
1167    pub mod OTG_ID_CHG_IRQ {
1168        pub const offset: u32 = 6;
1169        pub const mask: u32 = 0x01 << offset;
1170        pub mod R {}
1171        pub mod W {}
1172        pub mod RW {}
1173    }
1174    #[doc = "Enables circuit to detect resistance of MiniAB ID pin."]
1175    pub mod ENOTGIDDETECT {
1176        pub const offset: u32 = 7;
1177        pub const mask: u32 = 0x01 << offset;
1178        pub mod R {}
1179        pub mod W {}
1180        pub mod RW {}
1181    }
1182    #[doc = "Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it"]
1183    pub mod RESUMEIRQSTICKY {
1184        pub const offset: u32 = 8;
1185        pub const mask: u32 = 0x01 << offset;
1186        pub mod R {}
1187        pub mod W {}
1188        pub mod RW {}
1189    }
1190    #[doc = "Enables interrupt for detection of a non-J state on the USB line"]
1191    pub mod ENIRQRESUMEDETECT {
1192        pub const offset: u32 = 9;
1193        pub const mask: u32 = 0x01 << offset;
1194        pub mod R {}
1195        pub mod W {}
1196        pub mod RW {}
1197    }
1198    #[doc = "Indicates that the host is sending a wake-up after suspend"]
1199    pub mod RESUME_IRQ {
1200        pub const offset: u32 = 10;
1201        pub const mask: u32 = 0x01 << offset;
1202        pub mod R {}
1203        pub mod W {}
1204        pub mod RW {}
1205    }
1206    #[doc = "Enables interrupt for the detection of connectivity to the USB line."]
1207    pub mod ENIRQDEVPLUGIN {
1208        pub const offset: u32 = 11;
1209        pub const mask: u32 = 0x01 << offset;
1210        pub mod R {}
1211        pub mod W {}
1212        pub mod RW {}
1213    }
1214    #[doc = "Indicates that the device is connected"]
1215    pub mod DEVPLUGIN_IRQ {
1216        pub const offset: u32 = 12;
1217        pub const mask: u32 = 0x01 << offset;
1218        pub mod R {}
1219        pub mod W {}
1220        pub mod RW {}
1221    }
1222    #[doc = "Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only."]
1223    pub mod DATA_ON_LRADC {
1224        pub const offset: u32 = 13;
1225        pub const mask: u32 = 0x01 << offset;
1226        pub mod R {}
1227        pub mod W {}
1228        pub mod RW {}
1229    }
1230    #[doc = "Enables UTMI+ Level2. This should be enabled if needs to support LS device"]
1231    pub mod ENUTMILEVEL2 {
1232        pub const offset: u32 = 14;
1233        pub const mask: u32 = 0x01 << offset;
1234        pub mod R {}
1235        pub mod W {}
1236        pub mod RW {}
1237    }
1238    #[doc = "Enables UTMI+ Level3"]
1239    pub mod ENUTMILEVEL3 {
1240        pub const offset: u32 = 15;
1241        pub const mask: u32 = 0x01 << offset;
1242        pub mod R {}
1243        pub mod W {}
1244        pub mod RW {}
1245    }
1246    #[doc = "Enables interrupt for the wakeup events."]
1247    pub mod ENIRQWAKEUP {
1248        pub const offset: u32 = 16;
1249        pub const mask: u32 = 0x01 << offset;
1250        pub mod R {}
1251        pub mod W {}
1252        pub mod RW {}
1253    }
1254    #[doc = "Indicates that there is a wakeup event"]
1255    pub mod WAKEUP_IRQ {
1256        pub const offset: u32 = 17;
1257        pub const mask: u32 = 0x01 << offset;
1258        pub mod R {}
1259        pub mod W {}
1260        pub mod RW {}
1261    }
1262    #[doc = "Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended"]
1263    pub mod ENAUTO_PWRON_PLL {
1264        pub const offset: u32 = 18;
1265        pub const mask: u32 = 0x01 << offset;
1266        pub mod R {}
1267        pub mod W {}
1268        pub mod RW {}
1269    }
1270    #[doc = "Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
1271    pub mod ENAUTOCLR_CLKGATE {
1272        pub const offset: u32 = 19;
1273        pub const mask: u32 = 0x01 << offset;
1274        pub mod R {}
1275        pub mod W {}
1276        pub mod RW {}
1277    }
1278    #[doc = "Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended"]
1279    pub mod ENAUTOCLR_PHY_PWD {
1280        pub const offset: u32 = 20;
1281        pub const mask: u32 = 0x01 << offset;
1282        pub mod R {}
1283        pub mod W {}
1284        pub mod RW {}
1285    }
1286    #[doc = "Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended"]
1287    pub mod ENDPDMCHG_WKUP {
1288        pub const offset: u32 = 21;
1289        pub const mask: u32 = 0x01 << offset;
1290        pub mod R {}
1291        pub mod W {}
1292        pub mod RW {}
1293    }
1294    #[doc = "Enables the feature to wakeup USB if ID is toggled when USB is suspended."]
1295    pub mod ENIDCHG_WKUP {
1296        pub const offset: u32 = 22;
1297        pub const mask: u32 = 0x01 << offset;
1298        pub mod R {}
1299        pub mod W {}
1300        pub mod RW {}
1301    }
1302    #[doc = "Enables the feature to wakeup USB if VBUS is toggled when USB is suspended."]
1303    pub mod ENVBUSCHG_WKUP {
1304        pub const offset: u32 = 23;
1305        pub const mask: u32 = 0x01 << offset;
1306        pub mod R {}
1307        pub mod W {}
1308        pub mod RW {}
1309    }
1310    #[doc = "Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
1311    pub mod FSDLL_RST_EN {
1312        pub const offset: u32 = 24;
1313        pub const mask: u32 = 0x01 << offset;
1314        pub mod R {}
1315        pub mod W {}
1316        pub mod RW {}
1317    }
1318    #[doc = "Reserved."]
1319    pub mod RSVD1 {
1320        pub const offset: u32 = 25;
1321        pub const mask: u32 = 0x03 << offset;
1322        pub mod R {}
1323        pub mod W {}
1324        pub mod RW {}
1325    }
1326    #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"]
1327    pub mod OTG_ID_VALUE {
1328        pub const offset: u32 = 27;
1329        pub const mask: u32 = 0x01 << offset;
1330        pub mod R {}
1331        pub mod W {}
1332        pub mod RW {}
1333    }
1334    #[doc = "Forces the next FS packet that is transmitted to have a EOP with LS timing"]
1335    pub mod HOST_FORCE_LS_SE0 {
1336        pub const offset: u32 = 28;
1337        pub const mask: u32 = 0x01 << offset;
1338        pub mod R {}
1339        pub mod W {}
1340        pub mod RW {}
1341    }
1342    #[doc = "Used by the PHY to indicate a powered-down state"]
1343    pub mod UTMI_SUSPENDM {
1344        pub const offset: u32 = 29;
1345        pub const mask: u32 = 0x01 << offset;
1346        pub mod R {}
1347        pub mod W {}
1348        pub mod RW {}
1349    }
1350    #[doc = "Gate UTMI Clocks"]
1351    pub mod CLKGATE {
1352        pub const offset: u32 = 30;
1353        pub const mask: u32 = 0x01 << offset;
1354        pub mod R {}
1355        pub mod W {}
1356        pub mod RW {}
1357    }
1358    #[doc = "Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers"]
1359    pub mod SFTRST {
1360        pub const offset: u32 = 31;
1361        pub const mask: u32 = 0x01 << offset;
1362        pub mod R {}
1363        pub mod W {}
1364        pub mod RW {}
1365    }
1366}
1367#[doc = "USB PHY General Control Register"]
1368pub mod CTRL_CLR {
1369    #[doc = "Enable OTG_ID_CHG_IRQ."]
1370    pub mod ENOTG_ID_CHG_IRQ {
1371        pub const offset: u32 = 0;
1372        pub const mask: u32 = 0x01 << offset;
1373        pub mod R {}
1374        pub mod W {}
1375        pub mod RW {}
1376    }
1377    #[doc = "For host mode, enables high-speed disconnect detector"]
1378    pub mod ENHOSTDISCONDETECT {
1379        pub const offset: u32 = 1;
1380        pub const mask: u32 = 0x01 << offset;
1381        pub mod R {}
1382        pub mod W {}
1383        pub mod RW {}
1384    }
1385    #[doc = "Enables interrupt for detection of disconnection to Device when in high-speed host mode"]
1386    pub mod ENIRQHOSTDISCON {
1387        pub const offset: u32 = 2;
1388        pub const mask: u32 = 0x01 << offset;
1389        pub mod R {}
1390        pub mod W {}
1391        pub mod RW {}
1392    }
1393    #[doc = "Indicates that the device has disconnected in high-speed mode"]
1394    pub mod HOSTDISCONDETECT_IRQ {
1395        pub const offset: u32 = 3;
1396        pub const mask: u32 = 0x01 << offset;
1397        pub mod R {}
1398        pub mod W {}
1399        pub mod RW {}
1400    }
1401    #[doc = "For device mode, enables 200-KOhm pullups for detecting connectivity to the host."]
1402    pub mod ENDEVPLUGINDETECT {
1403        pub const offset: u32 = 4;
1404        pub const mask: u32 = 0x01 << offset;
1405        pub mod R {}
1406        pub mod W {}
1407        pub mod RW {}
1408    }
1409    #[doc = "For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in"]
1410    pub mod DEVPLUGIN_POLARITY {
1411        pub const offset: u32 = 5;
1412        pub const mask: u32 = 0x01 << offset;
1413        pub mod R {}
1414        pub mod W {}
1415        pub mod RW {}
1416    }
1417    #[doc = "OTG ID change interrupt. Indicates the value of ID pin changed."]
1418    pub mod OTG_ID_CHG_IRQ {
1419        pub const offset: u32 = 6;
1420        pub const mask: u32 = 0x01 << offset;
1421        pub mod R {}
1422        pub mod W {}
1423        pub mod RW {}
1424    }
1425    #[doc = "Enables circuit to detect resistance of MiniAB ID pin."]
1426    pub mod ENOTGIDDETECT {
1427        pub const offset: u32 = 7;
1428        pub const mask: u32 = 0x01 << offset;
1429        pub mod R {}
1430        pub mod W {}
1431        pub mod RW {}
1432    }
1433    #[doc = "Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it"]
1434    pub mod RESUMEIRQSTICKY {
1435        pub const offset: u32 = 8;
1436        pub const mask: u32 = 0x01 << offset;
1437        pub mod R {}
1438        pub mod W {}
1439        pub mod RW {}
1440    }
1441    #[doc = "Enables interrupt for detection of a non-J state on the USB line"]
1442    pub mod ENIRQRESUMEDETECT {
1443        pub const offset: u32 = 9;
1444        pub const mask: u32 = 0x01 << offset;
1445        pub mod R {}
1446        pub mod W {}
1447        pub mod RW {}
1448    }
1449    #[doc = "Indicates that the host is sending a wake-up after suspend"]
1450    pub mod RESUME_IRQ {
1451        pub const offset: u32 = 10;
1452        pub const mask: u32 = 0x01 << offset;
1453        pub mod R {}
1454        pub mod W {}
1455        pub mod RW {}
1456    }
1457    #[doc = "Enables interrupt for the detection of connectivity to the USB line."]
1458    pub mod ENIRQDEVPLUGIN {
1459        pub const offset: u32 = 11;
1460        pub const mask: u32 = 0x01 << offset;
1461        pub mod R {}
1462        pub mod W {}
1463        pub mod RW {}
1464    }
1465    #[doc = "Indicates that the device is connected"]
1466    pub mod DEVPLUGIN_IRQ {
1467        pub const offset: u32 = 12;
1468        pub const mask: u32 = 0x01 << offset;
1469        pub mod R {}
1470        pub mod W {}
1471        pub mod RW {}
1472    }
1473    #[doc = "Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only."]
1474    pub mod DATA_ON_LRADC {
1475        pub const offset: u32 = 13;
1476        pub const mask: u32 = 0x01 << offset;
1477        pub mod R {}
1478        pub mod W {}
1479        pub mod RW {}
1480    }
1481    #[doc = "Enables UTMI+ Level2. This should be enabled if needs to support LS device"]
1482    pub mod ENUTMILEVEL2 {
1483        pub const offset: u32 = 14;
1484        pub const mask: u32 = 0x01 << offset;
1485        pub mod R {}
1486        pub mod W {}
1487        pub mod RW {}
1488    }
1489    #[doc = "Enables UTMI+ Level3"]
1490    pub mod ENUTMILEVEL3 {
1491        pub const offset: u32 = 15;
1492        pub const mask: u32 = 0x01 << offset;
1493        pub mod R {}
1494        pub mod W {}
1495        pub mod RW {}
1496    }
1497    #[doc = "Enables interrupt for the wakeup events."]
1498    pub mod ENIRQWAKEUP {
1499        pub const offset: u32 = 16;
1500        pub const mask: u32 = 0x01 << offset;
1501        pub mod R {}
1502        pub mod W {}
1503        pub mod RW {}
1504    }
1505    #[doc = "Indicates that there is a wakeup event"]
1506    pub mod WAKEUP_IRQ {
1507        pub const offset: u32 = 17;
1508        pub const mask: u32 = 0x01 << offset;
1509        pub mod R {}
1510        pub mod W {}
1511        pub mod RW {}
1512    }
1513    #[doc = "Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended"]
1514    pub mod ENAUTO_PWRON_PLL {
1515        pub const offset: u32 = 18;
1516        pub const mask: u32 = 0x01 << offset;
1517        pub mod R {}
1518        pub mod W {}
1519        pub mod RW {}
1520    }
1521    #[doc = "Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
1522    pub mod ENAUTOCLR_CLKGATE {
1523        pub const offset: u32 = 19;
1524        pub const mask: u32 = 0x01 << offset;
1525        pub mod R {}
1526        pub mod W {}
1527        pub mod RW {}
1528    }
1529    #[doc = "Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended"]
1530    pub mod ENAUTOCLR_PHY_PWD {
1531        pub const offset: u32 = 20;
1532        pub const mask: u32 = 0x01 << offset;
1533        pub mod R {}
1534        pub mod W {}
1535        pub mod RW {}
1536    }
1537    #[doc = "Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended"]
1538    pub mod ENDPDMCHG_WKUP {
1539        pub const offset: u32 = 21;
1540        pub const mask: u32 = 0x01 << offset;
1541        pub mod R {}
1542        pub mod W {}
1543        pub mod RW {}
1544    }
1545    #[doc = "Enables the feature to wakeup USB if ID is toggled when USB is suspended."]
1546    pub mod ENIDCHG_WKUP {
1547        pub const offset: u32 = 22;
1548        pub const mask: u32 = 0x01 << offset;
1549        pub mod R {}
1550        pub mod W {}
1551        pub mod RW {}
1552    }
1553    #[doc = "Enables the feature to wakeup USB if VBUS is toggled when USB is suspended."]
1554    pub mod ENVBUSCHG_WKUP {
1555        pub const offset: u32 = 23;
1556        pub const mask: u32 = 0x01 << offset;
1557        pub mod R {}
1558        pub mod W {}
1559        pub mod RW {}
1560    }
1561    #[doc = "Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
1562    pub mod FSDLL_RST_EN {
1563        pub const offset: u32 = 24;
1564        pub const mask: u32 = 0x01 << offset;
1565        pub mod R {}
1566        pub mod W {}
1567        pub mod RW {}
1568    }
1569    #[doc = "Reserved."]
1570    pub mod RSVD1 {
1571        pub const offset: u32 = 25;
1572        pub const mask: u32 = 0x03 << offset;
1573        pub mod R {}
1574        pub mod W {}
1575        pub mod RW {}
1576    }
1577    #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"]
1578    pub mod OTG_ID_VALUE {
1579        pub const offset: u32 = 27;
1580        pub const mask: u32 = 0x01 << offset;
1581        pub mod R {}
1582        pub mod W {}
1583        pub mod RW {}
1584    }
1585    #[doc = "Forces the next FS packet that is transmitted to have a EOP with LS timing"]
1586    pub mod HOST_FORCE_LS_SE0 {
1587        pub const offset: u32 = 28;
1588        pub const mask: u32 = 0x01 << offset;
1589        pub mod R {}
1590        pub mod W {}
1591        pub mod RW {}
1592    }
1593    #[doc = "Used by the PHY to indicate a powered-down state"]
1594    pub mod UTMI_SUSPENDM {
1595        pub const offset: u32 = 29;
1596        pub const mask: u32 = 0x01 << offset;
1597        pub mod R {}
1598        pub mod W {}
1599        pub mod RW {}
1600    }
1601    #[doc = "Gate UTMI Clocks"]
1602    pub mod CLKGATE {
1603        pub const offset: u32 = 30;
1604        pub const mask: u32 = 0x01 << offset;
1605        pub mod R {}
1606        pub mod W {}
1607        pub mod RW {}
1608    }
1609    #[doc = "Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers"]
1610    pub mod SFTRST {
1611        pub const offset: u32 = 31;
1612        pub const mask: u32 = 0x01 << offset;
1613        pub mod R {}
1614        pub mod W {}
1615        pub mod RW {}
1616    }
1617}
1618#[doc = "USB PHY General Control Register"]
1619pub mod CTRL_TOG {
1620    #[doc = "Enable OTG_ID_CHG_IRQ."]
1621    pub mod ENOTG_ID_CHG_IRQ {
1622        pub const offset: u32 = 0;
1623        pub const mask: u32 = 0x01 << offset;
1624        pub mod R {}
1625        pub mod W {}
1626        pub mod RW {}
1627    }
1628    #[doc = "For host mode, enables high-speed disconnect detector"]
1629    pub mod ENHOSTDISCONDETECT {
1630        pub const offset: u32 = 1;
1631        pub const mask: u32 = 0x01 << offset;
1632        pub mod R {}
1633        pub mod W {}
1634        pub mod RW {}
1635    }
1636    #[doc = "Enables interrupt for detection of disconnection to Device when in high-speed host mode"]
1637    pub mod ENIRQHOSTDISCON {
1638        pub const offset: u32 = 2;
1639        pub const mask: u32 = 0x01 << offset;
1640        pub mod R {}
1641        pub mod W {}
1642        pub mod RW {}
1643    }
1644    #[doc = "Indicates that the device has disconnected in high-speed mode"]
1645    pub mod HOSTDISCONDETECT_IRQ {
1646        pub const offset: u32 = 3;
1647        pub const mask: u32 = 0x01 << offset;
1648        pub mod R {}
1649        pub mod W {}
1650        pub mod RW {}
1651    }
1652    #[doc = "For device mode, enables 200-KOhm pullups for detecting connectivity to the host."]
1653    pub mod ENDEVPLUGINDETECT {
1654        pub const offset: u32 = 4;
1655        pub const mask: u32 = 0x01 << offset;
1656        pub mod R {}
1657        pub mod W {}
1658        pub mod RW {}
1659    }
1660    #[doc = "For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in"]
1661    pub mod DEVPLUGIN_POLARITY {
1662        pub const offset: u32 = 5;
1663        pub const mask: u32 = 0x01 << offset;
1664        pub mod R {}
1665        pub mod W {}
1666        pub mod RW {}
1667    }
1668    #[doc = "OTG ID change interrupt. Indicates the value of ID pin changed."]
1669    pub mod OTG_ID_CHG_IRQ {
1670        pub const offset: u32 = 6;
1671        pub const mask: u32 = 0x01 << offset;
1672        pub mod R {}
1673        pub mod W {}
1674        pub mod RW {}
1675    }
1676    #[doc = "Enables circuit to detect resistance of MiniAB ID pin."]
1677    pub mod ENOTGIDDETECT {
1678        pub const offset: u32 = 7;
1679        pub const mask: u32 = 0x01 << offset;
1680        pub mod R {}
1681        pub mod W {}
1682        pub mod RW {}
1683    }
1684    #[doc = "Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it"]
1685    pub mod RESUMEIRQSTICKY {
1686        pub const offset: u32 = 8;
1687        pub const mask: u32 = 0x01 << offset;
1688        pub mod R {}
1689        pub mod W {}
1690        pub mod RW {}
1691    }
1692    #[doc = "Enables interrupt for detection of a non-J state on the USB line"]
1693    pub mod ENIRQRESUMEDETECT {
1694        pub const offset: u32 = 9;
1695        pub const mask: u32 = 0x01 << offset;
1696        pub mod R {}
1697        pub mod W {}
1698        pub mod RW {}
1699    }
1700    #[doc = "Indicates that the host is sending a wake-up after suspend"]
1701    pub mod RESUME_IRQ {
1702        pub const offset: u32 = 10;
1703        pub const mask: u32 = 0x01 << offset;
1704        pub mod R {}
1705        pub mod W {}
1706        pub mod RW {}
1707    }
1708    #[doc = "Enables interrupt for the detection of connectivity to the USB line."]
1709    pub mod ENIRQDEVPLUGIN {
1710        pub const offset: u32 = 11;
1711        pub const mask: u32 = 0x01 << offset;
1712        pub mod R {}
1713        pub mod W {}
1714        pub mod RW {}
1715    }
1716    #[doc = "Indicates that the device is connected"]
1717    pub mod DEVPLUGIN_IRQ {
1718        pub const offset: u32 = 12;
1719        pub const mask: u32 = 0x01 << offset;
1720        pub mod R {}
1721        pub mod W {}
1722        pub mod RW {}
1723    }
1724    #[doc = "Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only."]
1725    pub mod DATA_ON_LRADC {
1726        pub const offset: u32 = 13;
1727        pub const mask: u32 = 0x01 << offset;
1728        pub mod R {}
1729        pub mod W {}
1730        pub mod RW {}
1731    }
1732    #[doc = "Enables UTMI+ Level2. This should be enabled if needs to support LS device"]
1733    pub mod ENUTMILEVEL2 {
1734        pub const offset: u32 = 14;
1735        pub const mask: u32 = 0x01 << offset;
1736        pub mod R {}
1737        pub mod W {}
1738        pub mod RW {}
1739    }
1740    #[doc = "Enables UTMI+ Level3"]
1741    pub mod ENUTMILEVEL3 {
1742        pub const offset: u32 = 15;
1743        pub const mask: u32 = 0x01 << offset;
1744        pub mod R {}
1745        pub mod W {}
1746        pub mod RW {}
1747    }
1748    #[doc = "Enables interrupt for the wakeup events."]
1749    pub mod ENIRQWAKEUP {
1750        pub const offset: u32 = 16;
1751        pub const mask: u32 = 0x01 << offset;
1752        pub mod R {}
1753        pub mod W {}
1754        pub mod RW {}
1755    }
1756    #[doc = "Indicates that there is a wakeup event"]
1757    pub mod WAKEUP_IRQ {
1758        pub const offset: u32 = 17;
1759        pub const mask: u32 = 0x01 << offset;
1760        pub mod R {}
1761        pub mod W {}
1762        pub mod RW {}
1763    }
1764    #[doc = "Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended"]
1765    pub mod ENAUTO_PWRON_PLL {
1766        pub const offset: u32 = 18;
1767        pub const mask: u32 = 0x01 << offset;
1768        pub mod R {}
1769        pub mod W {}
1770        pub mod RW {}
1771    }
1772    #[doc = "Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
1773    pub mod ENAUTOCLR_CLKGATE {
1774        pub const offset: u32 = 19;
1775        pub const mask: u32 = 0x01 << offset;
1776        pub mod R {}
1777        pub mod W {}
1778        pub mod RW {}
1779    }
1780    #[doc = "Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended"]
1781    pub mod ENAUTOCLR_PHY_PWD {
1782        pub const offset: u32 = 20;
1783        pub const mask: u32 = 0x01 << offset;
1784        pub mod R {}
1785        pub mod W {}
1786        pub mod RW {}
1787    }
1788    #[doc = "Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended"]
1789    pub mod ENDPDMCHG_WKUP {
1790        pub const offset: u32 = 21;
1791        pub const mask: u32 = 0x01 << offset;
1792        pub mod R {}
1793        pub mod W {}
1794        pub mod RW {}
1795    }
1796    #[doc = "Enables the feature to wakeup USB if ID is toggled when USB is suspended."]
1797    pub mod ENIDCHG_WKUP {
1798        pub const offset: u32 = 22;
1799        pub const mask: u32 = 0x01 << offset;
1800        pub mod R {}
1801        pub mod W {}
1802        pub mod RW {}
1803    }
1804    #[doc = "Enables the feature to wakeup USB if VBUS is toggled when USB is suspended."]
1805    pub mod ENVBUSCHG_WKUP {
1806        pub const offset: u32 = 23;
1807        pub const mask: u32 = 0x01 << offset;
1808        pub mod R {}
1809        pub mod W {}
1810        pub mod RW {}
1811    }
1812    #[doc = "Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
1813    pub mod FSDLL_RST_EN {
1814        pub const offset: u32 = 24;
1815        pub const mask: u32 = 0x01 << offset;
1816        pub mod R {}
1817        pub mod W {}
1818        pub mod RW {}
1819    }
1820    #[doc = "Reserved."]
1821    pub mod RSVD1 {
1822        pub const offset: u32 = 25;
1823        pub const mask: u32 = 0x03 << offset;
1824        pub mod R {}
1825        pub mod W {}
1826        pub mod RW {}
1827    }
1828    #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"]
1829    pub mod OTG_ID_VALUE {
1830        pub const offset: u32 = 27;
1831        pub const mask: u32 = 0x01 << offset;
1832        pub mod R {}
1833        pub mod W {}
1834        pub mod RW {}
1835    }
1836    #[doc = "Forces the next FS packet that is transmitted to have a EOP with LS timing"]
1837    pub mod HOST_FORCE_LS_SE0 {
1838        pub const offset: u32 = 28;
1839        pub const mask: u32 = 0x01 << offset;
1840        pub mod R {}
1841        pub mod W {}
1842        pub mod RW {}
1843    }
1844    #[doc = "Used by the PHY to indicate a powered-down state"]
1845    pub mod UTMI_SUSPENDM {
1846        pub const offset: u32 = 29;
1847        pub const mask: u32 = 0x01 << offset;
1848        pub mod R {}
1849        pub mod W {}
1850        pub mod RW {}
1851    }
1852    #[doc = "Gate UTMI Clocks"]
1853    pub mod CLKGATE {
1854        pub const offset: u32 = 30;
1855        pub const mask: u32 = 0x01 << offset;
1856        pub mod R {}
1857        pub mod W {}
1858        pub mod RW {}
1859    }
1860    #[doc = "Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers"]
1861    pub mod SFTRST {
1862        pub const offset: u32 = 31;
1863        pub const mask: u32 = 0x01 << offset;
1864        pub mod R {}
1865        pub mod W {}
1866        pub mod RW {}
1867    }
1868}
1869#[doc = "USB PHY Status Register"]
1870pub mod STATUS {
1871    #[doc = "Reserved."]
1872    pub mod RSVD0 {
1873        pub const offset: u32 = 0;
1874        pub const mask: u32 = 0x07 << offset;
1875        pub mod R {}
1876        pub mod W {}
1877        pub mod RW {}
1878    }
1879    #[doc = "Indicates that the device has disconnected while in high-speed host mode."]
1880    pub mod HOSTDISCONDETECT_STATUS {
1881        pub const offset: u32 = 3;
1882        pub const mask: u32 = 0x01 << offset;
1883        pub mod R {}
1884        pub mod W {}
1885        pub mod RW {}
1886    }
1887    #[doc = "Reserved."]
1888    pub mod RSVD1 {
1889        pub const offset: u32 = 4;
1890        pub const mask: u32 = 0x03 << offset;
1891        pub mod R {}
1892        pub mod W {}
1893        pub mod RW {}
1894    }
1895    #[doc = "Indicates that the device has been connected on the USB_DP and USB_DM lines."]
1896    pub mod DEVPLUGIN_STATUS {
1897        pub const offset: u32 = 6;
1898        pub const mask: u32 = 0x01 << offset;
1899        pub mod R {}
1900        pub mod W {}
1901        pub mod RW {}
1902    }
1903    #[doc = "Reserved."]
1904    pub mod RSVD2 {
1905        pub const offset: u32 = 7;
1906        pub const mask: u32 = 0x01 << offset;
1907        pub mod R {}
1908        pub mod W {}
1909        pub mod RW {}
1910    }
1911    #[doc = "Indicates the results of ID pin on MiniAB plug"]
1912    pub mod OTGID_STATUS {
1913        pub const offset: u32 = 8;
1914        pub const mask: u32 = 0x01 << offset;
1915        pub mod R {}
1916        pub mod W {}
1917        pub mod RW {}
1918    }
1919    #[doc = "Reserved."]
1920    pub mod RSVD3 {
1921        pub const offset: u32 = 9;
1922        pub const mask: u32 = 0x01 << offset;
1923        pub mod R {}
1924        pub mod W {}
1925        pub mod RW {}
1926    }
1927    #[doc = "Indicates that the host is sending a wake-up after suspend and has triggered an interrupt."]
1928    pub mod RESUME_STATUS {
1929        pub const offset: u32 = 10;
1930        pub const mask: u32 = 0x01 << offset;
1931        pub mod R {}
1932        pub mod W {}
1933        pub mod RW {}
1934    }
1935    #[doc = "Reserved."]
1936    pub mod RSVD4 {
1937        pub const offset: u32 = 11;
1938        pub const mask: u32 = 0x001f_ffff << offset;
1939        pub mod R {}
1940        pub mod W {}
1941        pub mod RW {}
1942    }
1943}
1944#[doc = "USB PHY Debug Register"]
1945pub mod DEBUG {
1946    #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"]
1947    pub mod OTGIDPIOLOCK {
1948        pub const offset: u32 = 0;
1949        pub const mask: u32 = 0x01 << offset;
1950        pub mod R {}
1951        pub mod W {}
1952        pub mod RW {}
1953    }
1954    #[doc = "Use holding registers to assist in timing for external UTMI interface."]
1955    pub mod DEBUG_INTERFACE_HOLD {
1956        pub const offset: u32 = 1;
1957        pub const mask: u32 = 0x01 << offset;
1958        pub mod R {}
1959        pub mod W {}
1960        pub mod RW {}
1961    }
1962    #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"]
1963    pub mod HSTPULLDOWN {
1964        pub const offset: u32 = 2;
1965        pub const mask: u32 = 0x03 << offset;
1966        pub mod R {}
1967        pub mod W {}
1968        pub mod RW {}
1969    }
1970    #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"]
1971    pub mod ENHSTPULLDOWN {
1972        pub const offset: u32 = 4;
1973        pub const mask: u32 = 0x03 << offset;
1974        pub mod R {}
1975        pub mod W {}
1976        pub mod RW {}
1977    }
1978    #[doc = "Reserved."]
1979    pub mod RSVD0 {
1980        pub const offset: u32 = 6;
1981        pub const mask: u32 = 0x03 << offset;
1982        pub mod R {}
1983        pub mod W {}
1984        pub mod RW {}
1985    }
1986    #[doc = "Delay in between the end of transmit to the beginning of receive"]
1987    pub mod TX2RXCOUNT {
1988        pub const offset: u32 = 8;
1989        pub const mask: u32 = 0x0f << offset;
1990        pub mod R {}
1991        pub mod W {}
1992        pub mod RW {}
1993    }
1994    #[doc = "Set this bit to allow a countdown to transition in between TX and RX."]
1995    pub mod ENTX2RXCOUNT {
1996        pub const offset: u32 = 12;
1997        pub const mask: u32 = 0x01 << offset;
1998        pub mod R {}
1999        pub mod W {}
2000        pub mod RW {}
2001    }
2002    #[doc = "Reserved."]
2003    pub mod RSVD1 {
2004        pub const offset: u32 = 13;
2005        pub const mask: u32 = 0x07 << offset;
2006        pub mod R {}
2007        pub mod W {}
2008        pub mod RW {}
2009    }
2010    #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."]
2011    pub mod SQUELCHRESETCOUNT {
2012        pub const offset: u32 = 16;
2013        pub const mask: u32 = 0x1f << offset;
2014        pub mod R {}
2015        pub mod W {}
2016        pub mod RW {}
2017    }
2018    #[doc = "Reserved."]
2019    pub mod RSVD2 {
2020        pub const offset: u32 = 21;
2021        pub const mask: u32 = 0x07 << offset;
2022        pub mod R {}
2023        pub mod W {}
2024        pub mod RW {}
2025    }
2026    #[doc = "Set bit to allow squelch to reset high-speed receive."]
2027    pub mod ENSQUELCHRESET {
2028        pub const offset: u32 = 24;
2029        pub const mask: u32 = 0x01 << offset;
2030        pub mod R {}
2031        pub mod W {}
2032        pub mod RW {}
2033    }
2034    #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."]
2035    pub mod SQUELCHRESETLENGTH {
2036        pub const offset: u32 = 25;
2037        pub const mask: u32 = 0x0f << offset;
2038        pub mod R {}
2039        pub mod W {}
2040        pub mod RW {}
2041    }
2042    #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
2043    pub mod HOST_RESUME_DEBUG {
2044        pub const offset: u32 = 29;
2045        pub const mask: u32 = 0x01 << offset;
2046        pub mod R {}
2047        pub mod W {}
2048        pub mod RW {}
2049    }
2050    #[doc = "Gate Test Clocks"]
2051    pub mod CLKGATE {
2052        pub const offset: u32 = 30;
2053        pub const mask: u32 = 0x01 << offset;
2054        pub mod R {}
2055        pub mod W {}
2056        pub mod RW {}
2057    }
2058    #[doc = "Reserved."]
2059    pub mod RSVD3 {
2060        pub const offset: u32 = 31;
2061        pub const mask: u32 = 0x01 << offset;
2062        pub mod R {}
2063        pub mod W {}
2064        pub mod RW {}
2065    }
2066}
2067#[doc = "USB PHY Debug Register"]
2068pub mod DEBUG_SET {
2069    #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"]
2070    pub mod OTGIDPIOLOCK {
2071        pub const offset: u32 = 0;
2072        pub const mask: u32 = 0x01 << offset;
2073        pub mod R {}
2074        pub mod W {}
2075        pub mod RW {}
2076    }
2077    #[doc = "Use holding registers to assist in timing for external UTMI interface."]
2078    pub mod DEBUG_INTERFACE_HOLD {
2079        pub const offset: u32 = 1;
2080        pub const mask: u32 = 0x01 << offset;
2081        pub mod R {}
2082        pub mod W {}
2083        pub mod RW {}
2084    }
2085    #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"]
2086    pub mod HSTPULLDOWN {
2087        pub const offset: u32 = 2;
2088        pub const mask: u32 = 0x03 << offset;
2089        pub mod R {}
2090        pub mod W {}
2091        pub mod RW {}
2092    }
2093    #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"]
2094    pub mod ENHSTPULLDOWN {
2095        pub const offset: u32 = 4;
2096        pub const mask: u32 = 0x03 << offset;
2097        pub mod R {}
2098        pub mod W {}
2099        pub mod RW {}
2100    }
2101    #[doc = "Reserved."]
2102    pub mod RSVD0 {
2103        pub const offset: u32 = 6;
2104        pub const mask: u32 = 0x03 << offset;
2105        pub mod R {}
2106        pub mod W {}
2107        pub mod RW {}
2108    }
2109    #[doc = "Delay in between the end of transmit to the beginning of receive"]
2110    pub mod TX2RXCOUNT {
2111        pub const offset: u32 = 8;
2112        pub const mask: u32 = 0x0f << offset;
2113        pub mod R {}
2114        pub mod W {}
2115        pub mod RW {}
2116    }
2117    #[doc = "Set this bit to allow a countdown to transition in between TX and RX."]
2118    pub mod ENTX2RXCOUNT {
2119        pub const offset: u32 = 12;
2120        pub const mask: u32 = 0x01 << offset;
2121        pub mod R {}
2122        pub mod W {}
2123        pub mod RW {}
2124    }
2125    #[doc = "Reserved."]
2126    pub mod RSVD1 {
2127        pub const offset: u32 = 13;
2128        pub const mask: u32 = 0x07 << offset;
2129        pub mod R {}
2130        pub mod W {}
2131        pub mod RW {}
2132    }
2133    #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."]
2134    pub mod SQUELCHRESETCOUNT {
2135        pub const offset: u32 = 16;
2136        pub const mask: u32 = 0x1f << offset;
2137        pub mod R {}
2138        pub mod W {}
2139        pub mod RW {}
2140    }
2141    #[doc = "Reserved."]
2142    pub mod RSVD2 {
2143        pub const offset: u32 = 21;
2144        pub const mask: u32 = 0x07 << offset;
2145        pub mod R {}
2146        pub mod W {}
2147        pub mod RW {}
2148    }
2149    #[doc = "Set bit to allow squelch to reset high-speed receive."]
2150    pub mod ENSQUELCHRESET {
2151        pub const offset: u32 = 24;
2152        pub const mask: u32 = 0x01 << offset;
2153        pub mod R {}
2154        pub mod W {}
2155        pub mod RW {}
2156    }
2157    #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."]
2158    pub mod SQUELCHRESETLENGTH {
2159        pub const offset: u32 = 25;
2160        pub const mask: u32 = 0x0f << offset;
2161        pub mod R {}
2162        pub mod W {}
2163        pub mod RW {}
2164    }
2165    #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
2166    pub mod HOST_RESUME_DEBUG {
2167        pub const offset: u32 = 29;
2168        pub const mask: u32 = 0x01 << offset;
2169        pub mod R {}
2170        pub mod W {}
2171        pub mod RW {}
2172    }
2173    #[doc = "Gate Test Clocks"]
2174    pub mod CLKGATE {
2175        pub const offset: u32 = 30;
2176        pub const mask: u32 = 0x01 << offset;
2177        pub mod R {}
2178        pub mod W {}
2179        pub mod RW {}
2180    }
2181    #[doc = "Reserved."]
2182    pub mod RSVD3 {
2183        pub const offset: u32 = 31;
2184        pub const mask: u32 = 0x01 << offset;
2185        pub mod R {}
2186        pub mod W {}
2187        pub mod RW {}
2188    }
2189}
2190#[doc = "USB PHY Debug Register"]
2191pub mod DEBUG_CLR {
2192    #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"]
2193    pub mod OTGIDPIOLOCK {
2194        pub const offset: u32 = 0;
2195        pub const mask: u32 = 0x01 << offset;
2196        pub mod R {}
2197        pub mod W {}
2198        pub mod RW {}
2199    }
2200    #[doc = "Use holding registers to assist in timing for external UTMI interface."]
2201    pub mod DEBUG_INTERFACE_HOLD {
2202        pub const offset: u32 = 1;
2203        pub const mask: u32 = 0x01 << offset;
2204        pub mod R {}
2205        pub mod W {}
2206        pub mod RW {}
2207    }
2208    #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"]
2209    pub mod HSTPULLDOWN {
2210        pub const offset: u32 = 2;
2211        pub const mask: u32 = 0x03 << offset;
2212        pub mod R {}
2213        pub mod W {}
2214        pub mod RW {}
2215    }
2216    #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"]
2217    pub mod ENHSTPULLDOWN {
2218        pub const offset: u32 = 4;
2219        pub const mask: u32 = 0x03 << offset;
2220        pub mod R {}
2221        pub mod W {}
2222        pub mod RW {}
2223    }
2224    #[doc = "Reserved."]
2225    pub mod RSVD0 {
2226        pub const offset: u32 = 6;
2227        pub const mask: u32 = 0x03 << offset;
2228        pub mod R {}
2229        pub mod W {}
2230        pub mod RW {}
2231    }
2232    #[doc = "Delay in between the end of transmit to the beginning of receive"]
2233    pub mod TX2RXCOUNT {
2234        pub const offset: u32 = 8;
2235        pub const mask: u32 = 0x0f << offset;
2236        pub mod R {}
2237        pub mod W {}
2238        pub mod RW {}
2239    }
2240    #[doc = "Set this bit to allow a countdown to transition in between TX and RX."]
2241    pub mod ENTX2RXCOUNT {
2242        pub const offset: u32 = 12;
2243        pub const mask: u32 = 0x01 << offset;
2244        pub mod R {}
2245        pub mod W {}
2246        pub mod RW {}
2247    }
2248    #[doc = "Reserved."]
2249    pub mod RSVD1 {
2250        pub const offset: u32 = 13;
2251        pub const mask: u32 = 0x07 << offset;
2252        pub mod R {}
2253        pub mod W {}
2254        pub mod RW {}
2255    }
2256    #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."]
2257    pub mod SQUELCHRESETCOUNT {
2258        pub const offset: u32 = 16;
2259        pub const mask: u32 = 0x1f << offset;
2260        pub mod R {}
2261        pub mod W {}
2262        pub mod RW {}
2263    }
2264    #[doc = "Reserved."]
2265    pub mod RSVD2 {
2266        pub const offset: u32 = 21;
2267        pub const mask: u32 = 0x07 << offset;
2268        pub mod R {}
2269        pub mod W {}
2270        pub mod RW {}
2271    }
2272    #[doc = "Set bit to allow squelch to reset high-speed receive."]
2273    pub mod ENSQUELCHRESET {
2274        pub const offset: u32 = 24;
2275        pub const mask: u32 = 0x01 << offset;
2276        pub mod R {}
2277        pub mod W {}
2278        pub mod RW {}
2279    }
2280    #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."]
2281    pub mod SQUELCHRESETLENGTH {
2282        pub const offset: u32 = 25;
2283        pub const mask: u32 = 0x0f << offset;
2284        pub mod R {}
2285        pub mod W {}
2286        pub mod RW {}
2287    }
2288    #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
2289    pub mod HOST_RESUME_DEBUG {
2290        pub const offset: u32 = 29;
2291        pub const mask: u32 = 0x01 << offset;
2292        pub mod R {}
2293        pub mod W {}
2294        pub mod RW {}
2295    }
2296    #[doc = "Gate Test Clocks"]
2297    pub mod CLKGATE {
2298        pub const offset: u32 = 30;
2299        pub const mask: u32 = 0x01 << offset;
2300        pub mod R {}
2301        pub mod W {}
2302        pub mod RW {}
2303    }
2304    #[doc = "Reserved."]
2305    pub mod RSVD3 {
2306        pub const offset: u32 = 31;
2307        pub const mask: u32 = 0x01 << offset;
2308        pub mod R {}
2309        pub mod W {}
2310        pub mod RW {}
2311    }
2312}
2313#[doc = "USB PHY Debug Register"]
2314pub mod DEBUG_TOG {
2315    #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"]
2316    pub mod OTGIDPIOLOCK {
2317        pub const offset: u32 = 0;
2318        pub const mask: u32 = 0x01 << offset;
2319        pub mod R {}
2320        pub mod W {}
2321        pub mod RW {}
2322    }
2323    #[doc = "Use holding registers to assist in timing for external UTMI interface."]
2324    pub mod DEBUG_INTERFACE_HOLD {
2325        pub const offset: u32 = 1;
2326        pub const mask: u32 = 0x01 << offset;
2327        pub mod R {}
2328        pub mod W {}
2329        pub mod RW {}
2330    }
2331    #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"]
2332    pub mod HSTPULLDOWN {
2333        pub const offset: u32 = 2;
2334        pub const mask: u32 = 0x03 << offset;
2335        pub mod R {}
2336        pub mod W {}
2337        pub mod RW {}
2338    }
2339    #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"]
2340    pub mod ENHSTPULLDOWN {
2341        pub const offset: u32 = 4;
2342        pub const mask: u32 = 0x03 << offset;
2343        pub mod R {}
2344        pub mod W {}
2345        pub mod RW {}
2346    }
2347    #[doc = "Reserved."]
2348    pub mod RSVD0 {
2349        pub const offset: u32 = 6;
2350        pub const mask: u32 = 0x03 << offset;
2351        pub mod R {}
2352        pub mod W {}
2353        pub mod RW {}
2354    }
2355    #[doc = "Delay in between the end of transmit to the beginning of receive"]
2356    pub mod TX2RXCOUNT {
2357        pub const offset: u32 = 8;
2358        pub const mask: u32 = 0x0f << offset;
2359        pub mod R {}
2360        pub mod W {}
2361        pub mod RW {}
2362    }
2363    #[doc = "Set this bit to allow a countdown to transition in between TX and RX."]
2364    pub mod ENTX2RXCOUNT {
2365        pub const offset: u32 = 12;
2366        pub const mask: u32 = 0x01 << offset;
2367        pub mod R {}
2368        pub mod W {}
2369        pub mod RW {}
2370    }
2371    #[doc = "Reserved."]
2372    pub mod RSVD1 {
2373        pub const offset: u32 = 13;
2374        pub const mask: u32 = 0x07 << offset;
2375        pub mod R {}
2376        pub mod W {}
2377        pub mod RW {}
2378    }
2379    #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."]
2380    pub mod SQUELCHRESETCOUNT {
2381        pub const offset: u32 = 16;
2382        pub const mask: u32 = 0x1f << offset;
2383        pub mod R {}
2384        pub mod W {}
2385        pub mod RW {}
2386    }
2387    #[doc = "Reserved."]
2388    pub mod RSVD2 {
2389        pub const offset: u32 = 21;
2390        pub const mask: u32 = 0x07 << offset;
2391        pub mod R {}
2392        pub mod W {}
2393        pub mod RW {}
2394    }
2395    #[doc = "Set bit to allow squelch to reset high-speed receive."]
2396    pub mod ENSQUELCHRESET {
2397        pub const offset: u32 = 24;
2398        pub const mask: u32 = 0x01 << offset;
2399        pub mod R {}
2400        pub mod W {}
2401        pub mod RW {}
2402    }
2403    #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."]
2404    pub mod SQUELCHRESETLENGTH {
2405        pub const offset: u32 = 25;
2406        pub const mask: u32 = 0x0f << offset;
2407        pub mod R {}
2408        pub mod W {}
2409        pub mod RW {}
2410    }
2411    #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
2412    pub mod HOST_RESUME_DEBUG {
2413        pub const offset: u32 = 29;
2414        pub const mask: u32 = 0x01 << offset;
2415        pub mod R {}
2416        pub mod W {}
2417        pub mod RW {}
2418    }
2419    #[doc = "Gate Test Clocks"]
2420    pub mod CLKGATE {
2421        pub const offset: u32 = 30;
2422        pub const mask: u32 = 0x01 << offset;
2423        pub mod R {}
2424        pub mod W {}
2425        pub mod RW {}
2426    }
2427    #[doc = "Reserved."]
2428    pub mod RSVD3 {
2429        pub const offset: u32 = 31;
2430        pub const mask: u32 = 0x01 << offset;
2431        pub mod R {}
2432        pub mod W {}
2433        pub mod RW {}
2434    }
2435}
2436#[doc = "UTMI Debug Status Register 0"]
2437pub mod DEBUG0_STATUS {
2438    #[doc = "Running count of the failed pseudo-random generator loopback"]
2439    pub mod LOOP_BACK_FAIL_COUNT {
2440        pub const offset: u32 = 0;
2441        pub const mask: u32 = 0xffff << offset;
2442        pub mod R {}
2443        pub mod W {}
2444        pub mod RW {}
2445    }
2446    #[doc = "Running count of the UTMI_RXERROR."]
2447    pub mod UTMI_RXERROR_FAIL_COUNT {
2448        pub const offset: u32 = 16;
2449        pub const mask: u32 = 0x03ff << offset;
2450        pub mod R {}
2451        pub mod W {}
2452        pub mod RW {}
2453    }
2454    #[doc = "Running count of the squelch reset instead of normal end for HS RX."]
2455    pub mod SQUELCH_COUNT {
2456        pub const offset: u32 = 26;
2457        pub const mask: u32 = 0x3f << offset;
2458        pub mod R {}
2459        pub mod W {}
2460        pub mod RW {}
2461    }
2462}
2463#[doc = "UTMI Debug Status Register 1"]
2464pub mod DEBUG1 {
2465    #[doc = "Reserved. Note: This bit should remain clear."]
2466    pub mod RSVD0 {
2467        pub const offset: u32 = 0;
2468        pub const mask: u32 = 0x1fff << offset;
2469        pub mod R {}
2470        pub mod W {}
2471        pub mod RW {}
2472    }
2473    #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"]
2474    pub mod ENTAILADJVD {
2475        pub const offset: u32 = 13;
2476        pub const mask: u32 = 0x03 << offset;
2477        pub mod R {}
2478        pub mod W {}
2479        pub mod RW {}
2480    }
2481    #[doc = "Reserved."]
2482    pub mod RSVD1 {
2483        pub const offset: u32 = 15;
2484        pub const mask: u32 = 0x0001_ffff << offset;
2485        pub mod R {}
2486        pub mod W {}
2487        pub mod RW {}
2488    }
2489}
2490#[doc = "UTMI Debug Status Register 1"]
2491pub mod DEBUG1_SET {
2492    #[doc = "Reserved. Note: This bit should remain clear."]
2493    pub mod RSVD0 {
2494        pub const offset: u32 = 0;
2495        pub const mask: u32 = 0x1fff << offset;
2496        pub mod R {}
2497        pub mod W {}
2498        pub mod RW {}
2499    }
2500    #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"]
2501    pub mod ENTAILADJVD {
2502        pub const offset: u32 = 13;
2503        pub const mask: u32 = 0x03 << offset;
2504        pub mod R {}
2505        pub mod W {}
2506        pub mod RW {}
2507    }
2508    #[doc = "Reserved."]
2509    pub mod RSVD1 {
2510        pub const offset: u32 = 15;
2511        pub const mask: u32 = 0x0001_ffff << offset;
2512        pub mod R {}
2513        pub mod W {}
2514        pub mod RW {}
2515    }
2516}
2517#[doc = "UTMI Debug Status Register 1"]
2518pub mod DEBUG1_CLR {
2519    #[doc = "Reserved. Note: This bit should remain clear."]
2520    pub mod RSVD0 {
2521        pub const offset: u32 = 0;
2522        pub const mask: u32 = 0x1fff << offset;
2523        pub mod R {}
2524        pub mod W {}
2525        pub mod RW {}
2526    }
2527    #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"]
2528    pub mod ENTAILADJVD {
2529        pub const offset: u32 = 13;
2530        pub const mask: u32 = 0x03 << offset;
2531        pub mod R {}
2532        pub mod W {}
2533        pub mod RW {}
2534    }
2535    #[doc = "Reserved."]
2536    pub mod RSVD1 {
2537        pub const offset: u32 = 15;
2538        pub const mask: u32 = 0x0001_ffff << offset;
2539        pub mod R {}
2540        pub mod W {}
2541        pub mod RW {}
2542    }
2543}
2544#[doc = "UTMI Debug Status Register 1"]
2545pub mod DEBUG1_TOG {
2546    #[doc = "Reserved. Note: This bit should remain clear."]
2547    pub mod RSVD0 {
2548        pub const offset: u32 = 0;
2549        pub const mask: u32 = 0x1fff << offset;
2550        pub mod R {}
2551        pub mod W {}
2552        pub mod RW {}
2553    }
2554    #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"]
2555    pub mod ENTAILADJVD {
2556        pub const offset: u32 = 13;
2557        pub const mask: u32 = 0x03 << offset;
2558        pub mod R {}
2559        pub mod W {}
2560        pub mod RW {}
2561    }
2562    #[doc = "Reserved."]
2563    pub mod RSVD1 {
2564        pub const offset: u32 = 15;
2565        pub const mask: u32 = 0x0001_ffff << offset;
2566        pub mod R {}
2567        pub mod W {}
2568        pub mod RW {}
2569    }
2570}
2571#[doc = "UTMI RTL Version"]
2572pub mod VERSION {
2573    #[doc = "Fixed read-only value reflecting the stepping of the RTL version."]
2574    pub mod STEP {
2575        pub const offset: u32 = 0;
2576        pub const mask: u32 = 0xffff << offset;
2577        pub mod R {}
2578        pub mod W {}
2579        pub mod RW {}
2580    }
2581    #[doc = "Fixed read-only value reflecting the MINOR field of the RTL version."]
2582    pub mod MINOR {
2583        pub const offset: u32 = 16;
2584        pub const mask: u32 = 0xff << offset;
2585        pub mod R {}
2586        pub mod W {}
2587        pub mod RW {}
2588    }
2589    #[doc = "Fixed read-only value reflecting the MAJOR field of the RTL version."]
2590    pub mod MAJOR {
2591        pub const offset: u32 = 24;
2592        pub const mask: u32 = 0xff << offset;
2593        pub mod R {}
2594        pub mod W {}
2595        pub mod RW {}
2596    }
2597}
imxrt_ral/blocks/imxrt1011/usbphy.rs

imxrt_ral/blocks/imxrt1011/
usbphy.rs
