rp2040_pac/dma/
ch8_dbg_tcr.rs

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1#[doc = "Register `CH8_DBG_TCR` reader"]
2pub type R = crate::R<CH8_DBG_TCR_SPEC>;
3impl core::fmt::Debug for R {
4    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5        write!(f, "{}", self.bits())
6    }
7}
8impl core::fmt::Debug for crate::generic::Reg<CH8_DBG_TCR_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        core::fmt::Debug::fmt(&self.read(), f)
11    }
12}
13#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
14
15You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16pub struct CH8_DBG_TCR_SPEC;
17impl crate::RegisterSpec for CH8_DBG_TCR_SPEC {
18    type Ux = u32;
19}
20#[doc = "`read()` method returns [`ch8_dbg_tcr::R`](R) reader structure"]
21impl crate::Readable for CH8_DBG_TCR_SPEC {}
22#[doc = "`reset()` method sets CH8_DBG_TCR to value 0"]
23impl crate::Resettable for CH8_DBG_TCR_SPEC {
24    const RESET_VALUE: u32 = 0;
25}
rp2040_pac/dma/ch8_dbg_tcr.rs

rp2040_pac/dma/
ch8_dbg_tcr.rs
