imxrt_ral/blocks/imxrt1011/
ccm.rs1#[doc = "CCM"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "CCM Control Register"]
5 pub CCR: crate::RWRegister<u32>,
6 _reserved0: [u8; 0x04],
7 #[doc = "CCM Status Register"]
8 pub CSR: crate::RORegister<u32>,
9 #[doc = "CCM Clock Switcher Register"]
10 pub CCSR: crate::RWRegister<u32>,
11 _reserved1: [u8; 0x04],
12 #[doc = "CCM Bus Clock Divider Register"]
13 pub CBCDR: crate::RWRegister<u32>,
14 #[doc = "CCM Bus Clock Multiplexer Register"]
15 pub CBCMR: crate::RWRegister<u32>,
16 #[doc = "CCM Serial Clock Multiplexer Register 1"]
17 pub CSCMR1: crate::RWRegister<u32>,
18 #[doc = "CCM Serial Clock Multiplexer Register 2"]
19 pub CSCMR2: crate::RWRegister<u32>,
20 #[doc = "CCM Serial Clock Divider Register 1"]
21 pub CSCDR1: crate::RWRegister<u32>,
22 #[doc = "CCM Clock Divider Register"]
23 pub CS1CDR: crate::RWRegister<u32>,
24 _reserved2: [u8; 0x04],
25 #[doc = "CCM D1 Clock Divider Register"]
26 pub CDCDR: crate::RWRegister<u32>,
27 _reserved3: [u8; 0x04],
28 #[doc = "CCM Serial Clock Divider Register 2"]
29 pub CSCDR2: crate::RWRegister<u32>,
30 _reserved4: [u8; 0x0c],
31 #[doc = "CCM Divider Handshake In-Process Register"]
32 pub CDHIPR: crate::RORegister<u32>,
33 _reserved5: [u8; 0x08],
34 #[doc = "CCM Low Power Control Register"]
35 pub CLPCR: crate::RWRegister<u32>,
36 #[doc = "CCM Interrupt Status Register"]
37 pub CISR: crate::RWRegister<u32>,
38 #[doc = "CCM Interrupt Mask Register"]
39 pub CIMR: crate::RWRegister<u32>,
40 #[doc = "CCM Clock Output Source Register"]
41 pub CCOSR: crate::RWRegister<u32>,
42 #[doc = "CCM General Purpose Register"]
43 pub CGPR: crate::RWRegister<u32>,
44 #[doc = "CCM Clock Gating Register 0"]
45 pub CCGR0: crate::RWRegister<u32>,
46 #[doc = "CCM Clock Gating Register 1"]
47 pub CCGR1: crate::RWRegister<u32>,
48 #[doc = "CCM Clock Gating Register 2"]
49 pub CCGR2: crate::RWRegister<u32>,
50 #[doc = "CCM Clock Gating Register 3"]
51 pub CCGR3: crate::RWRegister<u32>,
52 #[doc = "CCM Clock Gating Register 4"]
53 pub CCGR4: crate::RWRegister<u32>,
54 #[doc = "CCM Clock Gating Register 5"]
55 pub CCGR5: crate::RWRegister<u32>,
56 #[doc = "CCM Clock Gating Register 6"]
57 pub CCGR6: crate::RWRegister<u32>,
58 _reserved6: [u8; 0x04],
59 #[doc = "CCM Module Enable Overide Register"]
60 pub CMEOR: crate::RWRegister<u32>,
61}
62#[doc = "CCM Control Register"]
63pub mod CCR {
64 #[doc = "Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened."]
65 pub mod OSCNT {
66 pub const offset: u32 = 0;
67 pub const mask: u32 = 0xff << offset;
68 pub mod R {}
69 pub mod W {}
70 pub mod RW {}
71 }
72 #[doc = "On chip oscillator enable bit - this bit value is reflected on the output cosc_en"]
73 pub mod COSC_EN {
74 pub const offset: u32 = 12;
75 pub const mask: u32 = 0x01 << offset;
76 pub mod R {}
77 pub mod W {}
78 pub mod RW {
79 #[doc = "disable on chip oscillator"]
80 pub const COSC_EN_0: u32 = 0;
81 #[doc = "enable on chip oscillator"]
82 pub const COSC_EN_1: u32 = 0x01;
83 }
84 }
85 #[doc = "Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ"]
86 pub mod REG_BYPASS_COUNT {
87 pub const offset: u32 = 21;
88 pub const mask: u32 = 0x3f << offset;
89 pub mod R {}
90 pub mod W {}
91 pub mod RW {
92 #[doc = "no delay"]
93 pub const REG_BYPASS_COUNT_0: u32 = 0;
94 #[doc = "1 CKIL clock period delay"]
95 pub const REG_BYPASS_COUNT_1: u32 = 0x01;
96 #[doc = "63 CKIL clock periods delay"]
97 pub const REG_BYPASS_COUNT_63: u32 = 0x3f;
98 }
99 }
100 #[doc = "Enable for REG_BYPASS_COUNTER"]
101 pub mod RBC_EN {
102 pub const offset: u32 = 27;
103 pub const mask: u32 = 0x01 << offset;
104 pub mod R {}
105 pub mod W {}
106 pub mod RW {
107 #[doc = "REG_BYPASS_COUNTER disabled"]
108 pub const RBC_EN_0: u32 = 0;
109 #[doc = "REG_BYPASS_COUNTER enabled."]
110 pub const RBC_EN_1: u32 = 0x01;
111 }
112 }
113}
114#[doc = "CCM Status Register"]
115pub mod CSR {
116 #[doc = "Status of the value of CCM_REF_EN_B output of ccm"]
117 pub mod REF_EN_B {
118 pub const offset: u32 = 0;
119 pub const mask: u32 = 0x01 << offset;
120 pub mod R {}
121 pub mod W {}
122 pub mod RW {
123 #[doc = "value of CCM_REF_EN_B is '0'"]
124 pub const REF_EN_B_0: u32 = 0;
125 #[doc = "value of CCM_REF_EN_B is '1'"]
126 pub const REF_EN_B_1: u32 = 0x01;
127 }
128 }
129 #[doc = "Status indication of CAMP2."]
130 pub mod CAMP2_READY {
131 pub const offset: u32 = 3;
132 pub const mask: u32 = 0x01 << offset;
133 pub mod R {}
134 pub mod W {}
135 pub mod RW {
136 #[doc = "CAMP2 is not ready."]
137 pub const CAMP2_READY_0: u32 = 0;
138 #[doc = "CAMP2 is ready."]
139 pub const CAMP2_READY_1: u32 = 0x01;
140 }
141 }
142 #[doc = "Status indication of on board oscillator"]
143 pub mod COSC_READY {
144 pub const offset: u32 = 5;
145 pub const mask: u32 = 0x01 << offset;
146 pub mod R {}
147 pub mod W {}
148 pub mod RW {
149 #[doc = "on board oscillator is not ready."]
150 pub const COSC_READY_0: u32 = 0;
151 #[doc = "on board oscillator is ready."]
152 pub const COSC_READY_1: u32 = 0x01;
153 }
154 }
155}
156#[doc = "CCM Clock Switcher Register"]
157pub mod CCSR {
158 #[doc = "Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes."]
159 pub mod PLL3_SW_CLK_SEL {
160 pub const offset: u32 = 0;
161 pub const mask: u32 = 0x01 << offset;
162 pub mod R {}
163 pub mod W {}
164 pub mod RW {
165 #[doc = "pll3_main_clk"]
166 pub const PLL3_SW_CLK_SEL_0: u32 = 0;
167 #[doc = "pll3 bypass clock"]
168 pub const PLL3_SW_CLK_SEL_1: u32 = 0x01;
169 }
170 }
171}
172#[doc = "CCM Bus Clock Divider Register"]
173pub mod CBCDR {
174 #[doc = "Divider for ipg podf."]
175 pub mod IPG_PODF {
176 pub const offset: u32 = 8;
177 pub const mask: u32 = 0x03 << offset;
178 pub mod R {}
179 pub mod W {}
180 pub mod RW {
181 #[doc = "divide by 1"]
182 pub const IPG_PODF_0: u32 = 0;
183 #[doc = "divide by 2"]
184 pub const IPG_PODF_1: u32 = 0x01;
185 #[doc = "divide by 3"]
186 pub const IPG_PODF_2: u32 = 0x02;
187 #[doc = "divide by 4"]
188 pub const IPG_PODF_3: u32 = 0x03;
189 }
190 }
191 #[doc = "Divider for AHB PODF"]
192 pub mod AHB_PODF {
193 pub const offset: u32 = 10;
194 pub const mask: u32 = 0x07 << offset;
195 pub mod R {}
196 pub mod W {}
197 pub mod RW {
198 #[doc = "divide by 1"]
199 pub const AHB_PODF_0: u32 = 0;
200 #[doc = "divide by 2"]
201 pub const AHB_PODF_1: u32 = 0x01;
202 #[doc = "divide by 3"]
203 pub const AHB_PODF_2: u32 = 0x02;
204 #[doc = "divide by 4"]
205 pub const AHB_PODF_3: u32 = 0x03;
206 #[doc = "divide by 5"]
207 pub const AHB_PODF_4: u32 = 0x04;
208 #[doc = "divide by 6"]
209 pub const AHB_PODF_5: u32 = 0x05;
210 #[doc = "divide by 7"]
211 pub const AHB_PODF_6: u32 = 0x06;
212 #[doc = "divide by 8"]
213 pub const AHB_PODF_7: u32 = 0x07;
214 }
215 }
216 #[doc = "Selector for peripheral main clock"]
217 pub mod PERIPH_CLK_SEL {
218 pub const offset: u32 = 25;
219 pub const mask: u32 = 0x01 << offset;
220 pub mod R {}
221 pub mod W {}
222 pub mod RW {
223 #[doc = "derive clock selected by CCM_CBCMR\\[CORE_CLK_PRE_SEL\\]"]
224 pub const PERIPH_CLK_SEL_0: u32 = 0;
225 #[doc = "derive clock selected by CCM_CBCMR\\[PERIPH_CLK2_SEL\\]"]
226 pub const PERIPH_CLK_SEL_1: u32 = 0x01;
227 }
228 }
229}
230#[doc = "CCM Bus Clock Multiplexer Register"]
231pub mod CBCMR {
232 #[doc = "Selector for lpspi clock multiplexer"]
233 pub mod LPSPI_CLK_SEL {
234 pub const offset: u32 = 4;
235 pub const mask: u32 = 0x03 << offset;
236 pub mod R {}
237 pub mod W {}
238 pub mod RW {
239 #[doc = "derive clock from PLL3 PFD1 clk"]
240 pub const LPSPI_CLK_SEL_0: u32 = 0;
241 #[doc = "derive clock from PLL3 PFD0"]
242 pub const LPSPI_CLK_SEL_1: u32 = 0x01;
243 #[doc = "derive clock from PLL2"]
244 pub const LPSPI_CLK_SEL_2: u32 = 0x02;
245 #[doc = "derive clock from PLL2 PFD2"]
246 pub const LPSPI_CLK_SEL_3: u32 = 0x03;
247 }
248 }
249 #[doc = "Selector for peripheral clk2 clock multiplexer"]
250 pub mod PERIPH_CLK2_SEL {
251 pub const offset: u32 = 12;
252 pub const mask: u32 = 0x03 << offset;
253 pub mod R {}
254 pub mod W {}
255 pub mod RW {
256 #[doc = "derive clock from pll3_sw_clk"]
257 pub const PERIPH_CLK2_SEL_0: u32 = 0;
258 #[doc = "derive clock from osc_clk"]
259 pub const PERIPH_CLK2_SEL_1: u32 = 0x01;
260 #[doc = "derive clock from pll2_bypass_clk"]
261 pub const PERIPH_CLK2_SEL_2: u32 = 0x02;
262 }
263 }
264 #[doc = "Selector for Trace clock multiplexer"]
265 pub mod TRACE_CLK_SEL {
266 pub const offset: u32 = 14;
267 pub const mask: u32 = 0x03 << offset;
268 pub mod R {}
269 pub mod W {}
270 pub mod RW {
271 #[doc = "derive clock from PLL2"]
272 pub const TRACE_CLK_SEL_0: u32 = 0;
273 #[doc = "derive clock from PLL2 PFD2"]
274 pub const TRACE_CLK_SEL_1: u32 = 0x01;
275 #[doc = "derive clock from PLL2 PFD0"]
276 pub const TRACE_CLK_SEL_2: u32 = 0x02;
277 #[doc = "derive clock from PLL2 PFD1"]
278 pub const TRACE_CLK_SEL_3: u32 = 0x03;
279 }
280 }
281 #[doc = "Selector for pre_periph clock multiplexer"]
282 pub mod PRE_PERIPH_CLK_SEL {
283 pub const offset: u32 = 18;
284 pub const mask: u32 = 0x03 << offset;
285 pub mod R {}
286 pub mod W {}
287 pub mod RW {
288 #[doc = "derive clock from PLL2"]
289 pub const PRE_PERIPH_CLK_SEL_0: u32 = 0;
290 #[doc = "derive clock from PLL3 PFD3"]
291 pub const PRE_PERIPH_CLK_SEL_1: u32 = 0x01;
292 #[doc = "derive clock from PLL2 PFD3"]
293 pub const PRE_PERIPH_CLK_SEL_2: u32 = 0x02;
294 #[doc = "derive clock from PLL6"]
295 pub const PRE_PERIPH_CLK_SEL_3: u32 = 0x03;
296 }
297 }
298 #[doc = "Divider for LPSPI. Divider should be updated when output clock is gated."]
299 pub mod LPSPI_PODF {
300 pub const offset: u32 = 26;
301 pub const mask: u32 = 0x0f << offset;
302 pub mod R {}
303 pub mod W {}
304 pub mod RW {
305 #[doc = "divide by 1"]
306 pub const LPSPI_PODF_0: u32 = 0;
307 #[doc = "divide by 2"]
308 pub const LPSPI_PODF_1: u32 = 0x01;
309 #[doc = "divide by 3"]
310 pub const LPSPI_PODF_2: u32 = 0x02;
311 #[doc = "divide by 4"]
312 pub const LPSPI_PODF_3: u32 = 0x03;
313 #[doc = "divide by 5"]
314 pub const LPSPI_PODF_4: u32 = 0x04;
315 #[doc = "divide by 6"]
316 pub const LPSPI_PODF_5: u32 = 0x05;
317 #[doc = "divide by 7"]
318 pub const LPSPI_PODF_6: u32 = 0x06;
319 #[doc = "divide by 8"]
320 pub const LPSPI_PODF_7: u32 = 0x07;
321 #[doc = "divide by 9"]
322 pub const LPSPI_PODF_8: u32 = 0x08;
323 #[doc = "divide by 10"]
324 pub const LPSPI_PODF_9: u32 = 0x09;
325 #[doc = "divide by 11"]
326 pub const LPSPI_PODF_10: u32 = 0x0a;
327 #[doc = "divide by 12"]
328 pub const LPSPI_PODF_11: u32 = 0x0b;
329 #[doc = "divide by 13"]
330 pub const LPSPI_PODF_12: u32 = 0x0c;
331 #[doc = "divide by 14"]
332 pub const LPSPI_PODF_13: u32 = 0x0d;
333 #[doc = "divide by 15"]
334 pub const LPSPI_PODF_14: u32 = 0x0e;
335 #[doc = "divide by 16"]
336 pub const LPSPI_PODF_15: u32 = 0x0f;
337 }
338 }
339}
340#[doc = "CCM Serial Clock Multiplexer Register 1"]
341pub mod CSCMR1 {
342 #[doc = "Divider for perclk podf."]
343 pub mod PERCLK_PODF {
344 pub const offset: u32 = 0;
345 pub const mask: u32 = 0x3f << offset;
346 pub mod R {}
347 pub mod W {}
348 pub mod RW {
349 #[doc = "Divide by 1"]
350 pub const DIVIDE_1: u32 = 0;
351 #[doc = "Divide by 2"]
352 pub const DIVIDE_2: u32 = 0x01;
353 #[doc = "Divide by 3"]
354 pub const DIVIDE_3: u32 = 0x02;
355 #[doc = "Divide by 4"]
356 pub const DIVIDE_4: u32 = 0x03;
357 #[doc = "Divide by 5"]
358 pub const DIVIDE_5: u32 = 0x04;
359 #[doc = "Divide by 6"]
360 pub const DIVIDE_6: u32 = 0x05;
361 #[doc = "Divide by 7"]
362 pub const DIVIDE_7: u32 = 0x06;
363 #[doc = "Divide by 8"]
364 pub const DIVIDE_8: u32 = 0x07;
365 #[doc = "Divide by 9"]
366 pub const DIVIDE_9: u32 = 0x08;
367 #[doc = "Divide by 10"]
368 pub const DIVIDE_10: u32 = 0x09;
369 #[doc = "Divide by 11"]
370 pub const DIVIDE_11: u32 = 0x0a;
371 #[doc = "Divide by 12"]
372 pub const DIVIDE_12: u32 = 0x0b;
373 #[doc = "Divide by 13"]
374 pub const DIVIDE_13: u32 = 0x0c;
375 #[doc = "Divide by 14"]
376 pub const DIVIDE_14: u32 = 0x0d;
377 #[doc = "Divide by 15"]
378 pub const DIVIDE_15: u32 = 0x0e;
379 #[doc = "Divide by 16"]
380 pub const DIVIDE_16: u32 = 0x0f;
381 #[doc = "Divide by 17"]
382 pub const DIVIDE_17: u32 = 0x10;
383 #[doc = "Divide by 18"]
384 pub const DIVIDE_18: u32 = 0x11;
385 #[doc = "Divide by 19"]
386 pub const DIVIDE_19: u32 = 0x12;
387 #[doc = "Divide by 20"]
388 pub const DIVIDE_20: u32 = 0x13;
389 #[doc = "Divide by 21"]
390 pub const DIVIDE_21: u32 = 0x14;
391 #[doc = "Divide by 22"]
392 pub const DIVIDE_22: u32 = 0x15;
393 #[doc = "Divide by 23"]
394 pub const DIVIDE_23: u32 = 0x16;
395 #[doc = "Divide by 24"]
396 pub const DIVIDE_24: u32 = 0x17;
397 #[doc = "Divide by 25"]
398 pub const DIVIDE_25: u32 = 0x18;
399 #[doc = "Divide by 26"]
400 pub const DIVIDE_26: u32 = 0x19;
401 #[doc = "Divide by 27"]
402 pub const DIVIDE_27: u32 = 0x1a;
403 #[doc = "Divide by 28"]
404 pub const DIVIDE_28: u32 = 0x1b;
405 #[doc = "Divide by 29"]
406 pub const DIVIDE_29: u32 = 0x1c;
407 #[doc = "Divide by 30"]
408 pub const DIVIDE_30: u32 = 0x1d;
409 #[doc = "Divide by 31"]
410 pub const DIVIDE_31: u32 = 0x1e;
411 #[doc = "Divide by 32"]
412 pub const DIVIDE_32: u32 = 0x1f;
413 #[doc = "Divide by 33"]
414 pub const DIVIDE_33: u32 = 0x20;
415 #[doc = "Divide by 34"]
416 pub const DIVIDE_34: u32 = 0x21;
417 #[doc = "Divide by 35"]
418 pub const DIVIDE_35: u32 = 0x22;
419 #[doc = "Divide by 36"]
420 pub const DIVIDE_36: u32 = 0x23;
421 #[doc = "Divide by 37"]
422 pub const DIVIDE_37: u32 = 0x24;
423 #[doc = "Divide by 38"]
424 pub const DIVIDE_38: u32 = 0x25;
425 #[doc = "Divide by 39"]
426 pub const DIVIDE_39: u32 = 0x26;
427 #[doc = "Divide by 40"]
428 pub const DIVIDE_40: u32 = 0x27;
429 #[doc = "Divide by 41"]
430 pub const DIVIDE_41: u32 = 0x28;
431 #[doc = "Divide by 42"]
432 pub const DIVIDE_42: u32 = 0x29;
433 #[doc = "Divide by 43"]
434 pub const DIVIDE_43: u32 = 0x2a;
435 #[doc = "Divide by 44"]
436 pub const DIVIDE_44: u32 = 0x2b;
437 #[doc = "Divide by 45"]
438 pub const DIVIDE_45: u32 = 0x2c;
439 #[doc = "Divide by 46"]
440 pub const DIVIDE_46: u32 = 0x2d;
441 #[doc = "Divide by 47"]
442 pub const DIVIDE_47: u32 = 0x2e;
443 #[doc = "Divide by 48"]
444 pub const DIVIDE_48: u32 = 0x2f;
445 #[doc = "Divide by 49"]
446 pub const DIVIDE_49: u32 = 0x30;
447 #[doc = "Divide by 50"]
448 pub const DIVIDE_50: u32 = 0x31;
449 #[doc = "Divide by 51"]
450 pub const DIVIDE_51: u32 = 0x32;
451 #[doc = "Divide by 52"]
452 pub const DIVIDE_52: u32 = 0x33;
453 #[doc = "Divide by 53"]
454 pub const DIVIDE_53: u32 = 0x34;
455 #[doc = "Divide by 54"]
456 pub const DIVIDE_54: u32 = 0x35;
457 #[doc = "Divide by 55"]
458 pub const DIVIDE_55: u32 = 0x36;
459 #[doc = "Divide by 56"]
460 pub const DIVIDE_56: u32 = 0x37;
461 #[doc = "Divide by 57"]
462 pub const DIVIDE_57: u32 = 0x38;
463 #[doc = "Divide by 58"]
464 pub const DIVIDE_58: u32 = 0x39;
465 #[doc = "Divide by 59"]
466 pub const DIVIDE_59: u32 = 0x3a;
467 #[doc = "Divide by 60"]
468 pub const DIVIDE_60: u32 = 0x3b;
469 #[doc = "Divide by 61"]
470 pub const DIVIDE_61: u32 = 0x3c;
471 #[doc = "Divide by 62"]
472 pub const DIVIDE_62: u32 = 0x3d;
473 #[doc = "Divide by 63"]
474 pub const DIVIDE_63: u32 = 0x3e;
475 #[doc = "Divide by 64"]
476 pub const DIVIDE_64: u32 = 0x3f;
477 }
478 }
479 #[doc = "Selector for the perclk clock multiplexor"]
480 pub mod PERCLK_CLK_SEL {
481 pub const offset: u32 = 6;
482 pub const mask: u32 = 0x01 << offset;
483 pub mod R {}
484 pub mod W {}
485 pub mod RW {
486 #[doc = "derive clock from ipg clk root"]
487 pub const PERCLK_CLK_SEL_0: u32 = 0;
488 #[doc = "derive clock from osc_clk"]
489 pub const PERCLK_CLK_SEL_1: u32 = 0x01;
490 }
491 }
492 #[doc = "Selector for sai1 clock multiplexer"]
493 pub mod SAI1_CLK_SEL {
494 pub const offset: u32 = 10;
495 pub const mask: u32 = 0x03 << offset;
496 pub mod R {}
497 pub mod W {}
498 pub mod RW {
499 #[doc = "derive clock from PLL3 PFD2"]
500 pub const SAI1_CLK_SEL_0: u32 = 0;
501 #[doc = "derive from pll3_sw_clk"]
502 pub const SAI1_CLK_SEL_1: u32 = 0x01;
503 #[doc = "derive clock from PLL4"]
504 pub const SAI1_CLK_SEL_2: u32 = 0x02;
505 }
506 }
507 #[doc = "Selector for sai3 clock multiplexer"]
508 pub mod SAI3_CLK_SEL {
509 pub const offset: u32 = 14;
510 pub const mask: u32 = 0x03 << offset;
511 pub mod R {}
512 pub mod W {}
513 pub mod RW {
514 #[doc = "derive clock from PLL3 PFD2"]
515 pub const SAI3_CLK_SEL_0: u32 = 0;
516 #[doc = "derive from pll3_sw_clk"]
517 pub const SAI3_CLK_SEL_1: u32 = 0x01;
518 #[doc = "derive clock from PLL4"]
519 pub const SAI3_CLK_SEL_2: u32 = 0x02;
520 }
521 }
522 #[doc = "Divider for flexspi clock root."]
523 pub mod FLEXSPI_PODF {
524 pub const offset: u32 = 23;
525 pub const mask: u32 = 0x07 << offset;
526 pub mod R {}
527 pub mod W {}
528 pub mod RW {
529 #[doc = "divide by 1"]
530 pub const FLEXSPI_PODF_0: u32 = 0;
531 #[doc = "divide by 2"]
532 pub const FLEXSPI_PODF_1: u32 = 0x01;
533 #[doc = "divide by 3"]
534 pub const FLEXSPI_PODF_2: u32 = 0x02;
535 #[doc = "divide by 4"]
536 pub const FLEXSPI_PODF_3: u32 = 0x03;
537 #[doc = "divide by 5"]
538 pub const FLEXSPI_PODF_4: u32 = 0x04;
539 #[doc = "divide by 6"]
540 pub const FLEXSPI_PODF_5: u32 = 0x05;
541 #[doc = "divide by 7"]
542 pub const FLEXSPI_PODF_6: u32 = 0x06;
543 #[doc = "divide by 8"]
544 pub const FLEXSPI_PODF_7: u32 = 0x07;
545 }
546 }
547 #[doc = "Selector for flexspi clock multiplexer"]
548 pub mod FLEXSPI_CLK_SEL {
549 pub const offset: u32 = 29;
550 pub const mask: u32 = 0x03 << offset;
551 pub mod R {}
552 pub mod W {}
553 pub mod RW {
554 #[doc = "derive clock from PLL2"]
555 pub const FLEXSPI_CLK_SEL_0: u32 = 0;
556 #[doc = "derive clock from pll3_sw_clk"]
557 pub const FLEXSPI_CLK_SEL_1: u32 = 0x01;
558 #[doc = "derive clock from PLL2 PFD2"]
559 pub const FLEXSPI_CLK_SEL_2: u32 = 0x02;
560 #[doc = "derive clock from PLL3 PFD0"]
561 pub const FLEXSPI_CLK_SEL_3: u32 = 0x03;
562 }
563 }
564 #[doc = "Select for source of flexspi_clk_root"]
565 pub mod FLEXSPI_CLK_SRC {
566 pub const offset: u32 = 31;
567 pub const mask: u32 = 0x01 << offset;
568 pub mod R {}
569 pub mod W {}
570 pub mod RW {
571 #[doc = "derive clock selected by CCM_CSCMR1\\[FLEXSPI_CLK_SEL\\]"]
572 pub const FLEXSPI_CLK_SRC_0: u32 = 0;
573 #[doc = "derive clock selected by CCM_CBCMR\\[PERIPH_CLK2_ SEL\\]"]
574 pub const FLEXSPI_CLK_SRC_1: u32 = 0x01;
575 }
576 }
577}
578#[doc = "CCM Serial Clock Multiplexer Register 2"]
579pub mod CSCMR2 {
580 #[doc = "Selector for flexio1 clock multiplexer"]
581 pub mod FLEXIO1_CLK_SEL {
582 pub const offset: u32 = 19;
583 pub const mask: u32 = 0x03 << offset;
584 pub mod R {}
585 pub mod W {}
586 pub mod RW {
587 #[doc = "derive clock from PLL4 divided clock"]
588 pub const FLEXIO1_CLK_SEL_0: u32 = 0;
589 #[doc = "derive clock from PLL3 PFD2 clock"]
590 pub const FLEXIO1_CLK_SEL_1: u32 = 0x01;
591 #[doc = "derive from PLL2"]
592 pub const FLEXIO1_CLK_SEL_2: u32 = 0x02;
593 #[doc = "derive clock from pll3_sw_clk"]
594 pub const FLEXIO1_CLK_SEL_3: u32 = 0x03;
595 }
596 }
597 #[doc = "Divider for ADC alt_clk, as the list below (other values reserved)."]
598 pub mod ADC_ACLK_PODF {
599 pub const offset: u32 = 27;
600 pub const mask: u32 = 0x0f << offset;
601 pub mod R {}
602 pub mod W {}
603 pub mod RW {
604 #[doc = "pll3_sw_clk / 8"]
605 pub const ADC_ACLK_PODF_7: u32 = 0x07;
606 #[doc = "pll3_sw_clk / 12"]
607 pub const ADC_ACLK_PODF_11: u32 = 0x0b;
608 #[doc = "pll3_sw_clk / 16"]
609 pub const ADC_ACLK_PODF_15: u32 = 0x0f;
610 }
611 }
612 #[doc = "Enable ADC alt_clk, so that ADC alt_clk can be driven be divided pll3_sw_clk."]
613 pub mod ADC_ACLK_EN {
614 pub const offset: u32 = 31;
615 pub const mask: u32 = 0x01 << offset;
616 pub mod R {}
617 pub mod W {}
618 pub mod RW {
619 #[doc = "ADC alt_clk source is disabled"]
620 pub const ADC_ACLK_EN_0: u32 = 0;
621 #[doc = "ADC alt_clk source is enabled"]
622 pub const ADC_ACLK_EN_1: u32 = 0x01;
623 }
624 }
625}
626#[doc = "CCM Serial Clock Divider Register 1"]
627pub mod CSCDR1 {
628 #[doc = "Divider for uart clock podf."]
629 pub mod UART_CLK_PODF {
630 pub const offset: u32 = 0;
631 pub const mask: u32 = 0x3f << offset;
632 pub mod R {}
633 pub mod W {}
634 pub mod RW {
635 #[doc = "Divide by 1"]
636 pub const DIVIDE_1: u32 = 0;
637 #[doc = "Divide by 2"]
638 pub const DIVIDE_2: u32 = 0x01;
639 #[doc = "Divide by 3"]
640 pub const DIVIDE_3: u32 = 0x02;
641 #[doc = "Divide by 4"]
642 pub const DIVIDE_4: u32 = 0x03;
643 #[doc = "Divide by 5"]
644 pub const DIVIDE_5: u32 = 0x04;
645 #[doc = "Divide by 6"]
646 pub const DIVIDE_6: u32 = 0x05;
647 #[doc = "Divide by 7"]
648 pub const DIVIDE_7: u32 = 0x06;
649 #[doc = "Divide by 8"]
650 pub const DIVIDE_8: u32 = 0x07;
651 #[doc = "Divide by 9"]
652 pub const DIVIDE_9: u32 = 0x08;
653 #[doc = "Divide by 10"]
654 pub const DIVIDE_10: u32 = 0x09;
655 #[doc = "Divide by 11"]
656 pub const DIVIDE_11: u32 = 0x0a;
657 #[doc = "Divide by 12"]
658 pub const DIVIDE_12: u32 = 0x0b;
659 #[doc = "Divide by 13"]
660 pub const DIVIDE_13: u32 = 0x0c;
661 #[doc = "Divide by 14"]
662 pub const DIVIDE_14: u32 = 0x0d;
663 #[doc = "Divide by 15"]
664 pub const DIVIDE_15: u32 = 0x0e;
665 #[doc = "Divide by 16"]
666 pub const DIVIDE_16: u32 = 0x0f;
667 #[doc = "Divide by 17"]
668 pub const DIVIDE_17: u32 = 0x10;
669 #[doc = "Divide by 18"]
670 pub const DIVIDE_18: u32 = 0x11;
671 #[doc = "Divide by 19"]
672 pub const DIVIDE_19: u32 = 0x12;
673 #[doc = "Divide by 20"]
674 pub const DIVIDE_20: u32 = 0x13;
675 #[doc = "Divide by 21"]
676 pub const DIVIDE_21: u32 = 0x14;
677 #[doc = "Divide by 22"]
678 pub const DIVIDE_22: u32 = 0x15;
679 #[doc = "Divide by 23"]
680 pub const DIVIDE_23: u32 = 0x16;
681 #[doc = "Divide by 24"]
682 pub const DIVIDE_24: u32 = 0x17;
683 #[doc = "Divide by 25"]
684 pub const DIVIDE_25: u32 = 0x18;
685 #[doc = "Divide by 26"]
686 pub const DIVIDE_26: u32 = 0x19;
687 #[doc = "Divide by 27"]
688 pub const DIVIDE_27: u32 = 0x1a;
689 #[doc = "Divide by 28"]
690 pub const DIVIDE_28: u32 = 0x1b;
691 #[doc = "Divide by 29"]
692 pub const DIVIDE_29: u32 = 0x1c;
693 #[doc = "Divide by 30"]
694 pub const DIVIDE_30: u32 = 0x1d;
695 #[doc = "Divide by 31"]
696 pub const DIVIDE_31: u32 = 0x1e;
697 #[doc = "Divide by 32"]
698 pub const DIVIDE_32: u32 = 0x1f;
699 #[doc = "Divide by 33"]
700 pub const DIVIDE_33: u32 = 0x20;
701 #[doc = "Divide by 34"]
702 pub const DIVIDE_34: u32 = 0x21;
703 #[doc = "Divide by 35"]
704 pub const DIVIDE_35: u32 = 0x22;
705 #[doc = "Divide by 36"]
706 pub const DIVIDE_36: u32 = 0x23;
707 #[doc = "Divide by 37"]
708 pub const DIVIDE_37: u32 = 0x24;
709 #[doc = "Divide by 38"]
710 pub const DIVIDE_38: u32 = 0x25;
711 #[doc = "Divide by 39"]
712 pub const DIVIDE_39: u32 = 0x26;
713 #[doc = "Divide by 40"]
714 pub const DIVIDE_40: u32 = 0x27;
715 #[doc = "Divide by 41"]
716 pub const DIVIDE_41: u32 = 0x28;
717 #[doc = "Divide by 42"]
718 pub const DIVIDE_42: u32 = 0x29;
719 #[doc = "Divide by 43"]
720 pub const DIVIDE_43: u32 = 0x2a;
721 #[doc = "Divide by 44"]
722 pub const DIVIDE_44: u32 = 0x2b;
723 #[doc = "Divide by 45"]
724 pub const DIVIDE_45: u32 = 0x2c;
725 #[doc = "Divide by 46"]
726 pub const DIVIDE_46: u32 = 0x2d;
727 #[doc = "Divide by 47"]
728 pub const DIVIDE_47: u32 = 0x2e;
729 #[doc = "Divide by 48"]
730 pub const DIVIDE_48: u32 = 0x2f;
731 #[doc = "Divide by 49"]
732 pub const DIVIDE_49: u32 = 0x30;
733 #[doc = "Divide by 50"]
734 pub const DIVIDE_50: u32 = 0x31;
735 #[doc = "Divide by 51"]
736 pub const DIVIDE_51: u32 = 0x32;
737 #[doc = "Divide by 52"]
738 pub const DIVIDE_52: u32 = 0x33;
739 #[doc = "Divide by 53"]
740 pub const DIVIDE_53: u32 = 0x34;
741 #[doc = "Divide by 54"]
742 pub const DIVIDE_54: u32 = 0x35;
743 #[doc = "Divide by 55"]
744 pub const DIVIDE_55: u32 = 0x36;
745 #[doc = "Divide by 56"]
746 pub const DIVIDE_56: u32 = 0x37;
747 #[doc = "Divide by 57"]
748 pub const DIVIDE_57: u32 = 0x38;
749 #[doc = "Divide by 58"]
750 pub const DIVIDE_58: u32 = 0x39;
751 #[doc = "Divide by 59"]
752 pub const DIVIDE_59: u32 = 0x3a;
753 #[doc = "Divide by 60"]
754 pub const DIVIDE_60: u32 = 0x3b;
755 #[doc = "Divide by 61"]
756 pub const DIVIDE_61: u32 = 0x3c;
757 #[doc = "Divide by 62"]
758 pub const DIVIDE_62: u32 = 0x3d;
759 #[doc = "Divide by 63"]
760 pub const DIVIDE_63: u32 = 0x3e;
761 #[doc = "Divide by 64"]
762 pub const DIVIDE_64: u32 = 0x3f;
763 }
764 }
765 #[doc = "Selector for the UART clock multiplexor"]
766 pub mod UART_CLK_SEL {
767 pub const offset: u32 = 6;
768 pub const mask: u32 = 0x03 << offset;
769 pub mod R {}
770 pub mod W {}
771 pub mod RW {
772 #[doc = "derive clock from pll3_80m"]
773 pub const UART_CLK_SEL_0: u32 = 0;
774 #[doc = "derive clock from osc_clk"]
775 pub const UART_CLK_SEL_1: u32 = 0x01;
776 #[doc = "derive clock from per_clk_root"]
777 pub const UART_CLK_SEL_2: u32 = 0x02;
778 }
779 }
780 #[doc = "Divider for trace clock. Divider should be updated when output clock is gated."]
781 pub mod TRACE_PODF {
782 pub const offset: u32 = 25;
783 pub const mask: u32 = 0x0f << offset;
784 pub mod R {}
785 pub mod W {}
786 pub mod RW {
787 #[doc = "divide by 1"]
788 pub const TRACE_PODF_0: u32 = 0;
789 #[doc = "divide by 2"]
790 pub const TRACE_PODF_1: u32 = 0x01;
791 #[doc = "divide by 3"]
792 pub const TRACE_PODF_2: u32 = 0x02;
793 #[doc = "divide by 4"]
794 pub const TRACE_PODF_3: u32 = 0x03;
795 #[doc = "divide by 5"]
796 pub const TRACE_PODF_4: u32 = 0x04;
797 #[doc = "divide by 6"]
798 pub const TRACE_PODF_5: u32 = 0x05;
799 #[doc = "divide by 7"]
800 pub const TRACE_PODF_6: u32 = 0x06;
801 #[doc = "divide by 8"]
802 pub const TRACE_PODF_7: u32 = 0x07;
803 #[doc = "divide by 9"]
804 pub const TRACE_PODF_8: u32 = 0x08;
805 #[doc = "divide by 10"]
806 pub const TRACE_PODF_9: u32 = 0x09;
807 #[doc = "divide by 11"]
808 pub const TRACE_PODF_10: u32 = 0x0a;
809 #[doc = "divide by 12"]
810 pub const TRACE_PODF_11: u32 = 0x0b;
811 #[doc = "divide by 13"]
812 pub const TRACE_PODF_12: u32 = 0x0c;
813 #[doc = "divide by 14"]
814 pub const TRACE_PODF_13: u32 = 0x0d;
815 #[doc = "divide by 15"]
816 pub const TRACE_PODF_14: u32 = 0x0e;
817 #[doc = "divide by 16"]
818 pub const TRACE_PODF_15: u32 = 0x0f;
819 }
820 }
821}
822#[doc = "CCM Clock Divider Register"]
823pub mod CS1CDR {
824 #[doc = "Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this."]
825 pub mod SAI1_CLK_PODF {
826 pub const offset: u32 = 0;
827 pub const mask: u32 = 0x3f << offset;
828 pub mod R {}
829 pub mod W {}
830 pub mod RW {
831 #[doc = "Divide by 1"]
832 pub const DIVIDE_1: u32 = 0;
833 #[doc = "Divide by 2"]
834 pub const DIVIDE_2: u32 = 0x01;
835 #[doc = "Divide by 3"]
836 pub const DIVIDE_3: u32 = 0x02;
837 #[doc = "Divide by 4"]
838 pub const DIVIDE_4: u32 = 0x03;
839 #[doc = "Divide by 5"]
840 pub const DIVIDE_5: u32 = 0x04;
841 #[doc = "Divide by 6"]
842 pub const DIVIDE_6: u32 = 0x05;
843 #[doc = "Divide by 7"]
844 pub const DIVIDE_7: u32 = 0x06;
845 #[doc = "Divide by 8"]
846 pub const DIVIDE_8: u32 = 0x07;
847 #[doc = "Divide by 9"]
848 pub const DIVIDE_9: u32 = 0x08;
849 #[doc = "Divide by 10"]
850 pub const DIVIDE_10: u32 = 0x09;
851 #[doc = "Divide by 11"]
852 pub const DIVIDE_11: u32 = 0x0a;
853 #[doc = "Divide by 12"]
854 pub const DIVIDE_12: u32 = 0x0b;
855 #[doc = "Divide by 13"]
856 pub const DIVIDE_13: u32 = 0x0c;
857 #[doc = "Divide by 14"]
858 pub const DIVIDE_14: u32 = 0x0d;
859 #[doc = "Divide by 15"]
860 pub const DIVIDE_15: u32 = 0x0e;
861 #[doc = "Divide by 16"]
862 pub const DIVIDE_16: u32 = 0x0f;
863 #[doc = "Divide by 17"]
864 pub const DIVIDE_17: u32 = 0x10;
865 #[doc = "Divide by 18"]
866 pub const DIVIDE_18: u32 = 0x11;
867 #[doc = "Divide by 19"]
868 pub const DIVIDE_19: u32 = 0x12;
869 #[doc = "Divide by 20"]
870 pub const DIVIDE_20: u32 = 0x13;
871 #[doc = "Divide by 21"]
872 pub const DIVIDE_21: u32 = 0x14;
873 #[doc = "Divide by 22"]
874 pub const DIVIDE_22: u32 = 0x15;
875 #[doc = "Divide by 23"]
876 pub const DIVIDE_23: u32 = 0x16;
877 #[doc = "Divide by 24"]
878 pub const DIVIDE_24: u32 = 0x17;
879 #[doc = "Divide by 25"]
880 pub const DIVIDE_25: u32 = 0x18;
881 #[doc = "Divide by 26"]
882 pub const DIVIDE_26: u32 = 0x19;
883 #[doc = "Divide by 27"]
884 pub const DIVIDE_27: u32 = 0x1a;
885 #[doc = "Divide by 28"]
886 pub const DIVIDE_28: u32 = 0x1b;
887 #[doc = "Divide by 29"]
888 pub const DIVIDE_29: u32 = 0x1c;
889 #[doc = "Divide by 30"]
890 pub const DIVIDE_30: u32 = 0x1d;
891 #[doc = "Divide by 31"]
892 pub const DIVIDE_31: u32 = 0x1e;
893 #[doc = "Divide by 32"]
894 pub const DIVIDE_32: u32 = 0x1f;
895 #[doc = "Divide by 33"]
896 pub const DIVIDE_33: u32 = 0x20;
897 #[doc = "Divide by 34"]
898 pub const DIVIDE_34: u32 = 0x21;
899 #[doc = "Divide by 35"]
900 pub const DIVIDE_35: u32 = 0x22;
901 #[doc = "Divide by 36"]
902 pub const DIVIDE_36: u32 = 0x23;
903 #[doc = "Divide by 37"]
904 pub const DIVIDE_37: u32 = 0x24;
905 #[doc = "Divide by 38"]
906 pub const DIVIDE_38: u32 = 0x25;
907 #[doc = "Divide by 39"]
908 pub const DIVIDE_39: u32 = 0x26;
909 #[doc = "Divide by 40"]
910 pub const DIVIDE_40: u32 = 0x27;
911 #[doc = "Divide by 41"]
912 pub const DIVIDE_41: u32 = 0x28;
913 #[doc = "Divide by 42"]
914 pub const DIVIDE_42: u32 = 0x29;
915 #[doc = "Divide by 43"]
916 pub const DIVIDE_43: u32 = 0x2a;
917 #[doc = "Divide by 44"]
918 pub const DIVIDE_44: u32 = 0x2b;
919 #[doc = "Divide by 45"]
920 pub const DIVIDE_45: u32 = 0x2c;
921 #[doc = "Divide by 46"]
922 pub const DIVIDE_46: u32 = 0x2d;
923 #[doc = "Divide by 47"]
924 pub const DIVIDE_47: u32 = 0x2e;
925 #[doc = "Divide by 48"]
926 pub const DIVIDE_48: u32 = 0x2f;
927 #[doc = "Divide by 49"]
928 pub const DIVIDE_49: u32 = 0x30;
929 #[doc = "Divide by 50"]
930 pub const DIVIDE_50: u32 = 0x31;
931 #[doc = "Divide by 51"]
932 pub const DIVIDE_51: u32 = 0x32;
933 #[doc = "Divide by 52"]
934 pub const DIVIDE_52: u32 = 0x33;
935 #[doc = "Divide by 53"]
936 pub const DIVIDE_53: u32 = 0x34;
937 #[doc = "Divide by 54"]
938 pub const DIVIDE_54: u32 = 0x35;
939 #[doc = "Divide by 55"]
940 pub const DIVIDE_55: u32 = 0x36;
941 #[doc = "Divide by 56"]
942 pub const DIVIDE_56: u32 = 0x37;
943 #[doc = "Divide by 57"]
944 pub const DIVIDE_57: u32 = 0x38;
945 #[doc = "Divide by 58"]
946 pub const DIVIDE_58: u32 = 0x39;
947 #[doc = "Divide by 59"]
948 pub const DIVIDE_59: u32 = 0x3a;
949 #[doc = "Divide by 60"]
950 pub const DIVIDE_60: u32 = 0x3b;
951 #[doc = "Divide by 61"]
952 pub const DIVIDE_61: u32 = 0x3c;
953 #[doc = "Divide by 62"]
954 pub const DIVIDE_62: u32 = 0x3d;
955 #[doc = "Divide by 63"]
956 pub const DIVIDE_63: u32 = 0x3e;
957 #[doc = "Divide by 64"]
958 pub const DIVIDE_64: u32 = 0x3f;
959 }
960 }
961 #[doc = "Divider for sai1 clock pred."]
962 pub mod SAI1_CLK_PRED {
963 pub const offset: u32 = 6;
964 pub const mask: u32 = 0x07 << offset;
965 pub mod R {}
966 pub mod W {}
967 pub mod RW {
968 #[doc = "divide by 1"]
969 pub const SAI1_CLK_PRED_0: u32 = 0;
970 #[doc = "divide by 2"]
971 pub const SAI1_CLK_PRED_1: u32 = 0x01;
972 #[doc = "divide by 3"]
973 pub const SAI1_CLK_PRED_2: u32 = 0x02;
974 #[doc = "divide by 4"]
975 pub const SAI1_CLK_PRED_3: u32 = 0x03;
976 #[doc = "divide by 5"]
977 pub const SAI1_CLK_PRED_4: u32 = 0x04;
978 #[doc = "divide by 6"]
979 pub const SAI1_CLK_PRED_5: u32 = 0x05;
980 #[doc = "divide by 7"]
981 pub const SAI1_CLK_PRED_6: u32 = 0x06;
982 #[doc = "divide by 8"]
983 pub const SAI1_CLK_PRED_7: u32 = 0x07;
984 }
985 }
986 #[doc = "Divider for flexio1 clock."]
987 pub mod FLEXIO1_CLK_PRED {
988 pub const offset: u32 = 9;
989 pub const mask: u32 = 0x07 << offset;
990 pub mod R {}
991 pub mod W {}
992 pub mod RW {
993 #[doc = "divide by 1"]
994 pub const FLEXIO1_CLK_PRED_0: u32 = 0;
995 #[doc = "divide by 2"]
996 pub const FLEXIO1_CLK_PRED_1: u32 = 0x01;
997 #[doc = "divide by 3"]
998 pub const FLEXIO1_CLK_PRED_2: u32 = 0x02;
999 #[doc = "divide by 4"]
1000 pub const FLEXIO1_CLK_PRED_3: u32 = 0x03;
1001 #[doc = "divide by 5"]
1002 pub const FLEXIO1_CLK_PRED_4: u32 = 0x04;
1003 #[doc = "divide by 6"]
1004 pub const FLEXIO1_CLK_PRED_5: u32 = 0x05;
1005 #[doc = "divide by 7"]
1006 pub const FLEXIO1_CLK_PRED_6: u32 = 0x06;
1007 #[doc = "divide by 8"]
1008 pub const FLEXIO1_CLK_PRED_7: u32 = 0x07;
1009 }
1010 }
1011 #[doc = "Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this."]
1012 pub mod SAI3_CLK_PODF {
1013 pub const offset: u32 = 16;
1014 pub const mask: u32 = 0x3f << offset;
1015 pub mod R {}
1016 pub mod W {}
1017 pub mod RW {
1018 #[doc = "Divide by 1"]
1019 pub const DIVIDE_1: u32 = 0;
1020 #[doc = "Divide by 2"]
1021 pub const DIVIDE_2: u32 = 0x01;
1022 #[doc = "Divide by 3"]
1023 pub const DIVIDE_3: u32 = 0x02;
1024 #[doc = "Divide by 4"]
1025 pub const DIVIDE_4: u32 = 0x03;
1026 #[doc = "Divide by 5"]
1027 pub const DIVIDE_5: u32 = 0x04;
1028 #[doc = "Divide by 6"]
1029 pub const DIVIDE_6: u32 = 0x05;
1030 #[doc = "Divide by 7"]
1031 pub const DIVIDE_7: u32 = 0x06;
1032 #[doc = "Divide by 8"]
1033 pub const DIVIDE_8: u32 = 0x07;
1034 #[doc = "Divide by 9"]
1035 pub const DIVIDE_9: u32 = 0x08;
1036 #[doc = "Divide by 10"]
1037 pub const DIVIDE_10: u32 = 0x09;
1038 #[doc = "Divide by 11"]
1039 pub const DIVIDE_11: u32 = 0x0a;
1040 #[doc = "Divide by 12"]
1041 pub const DIVIDE_12: u32 = 0x0b;
1042 #[doc = "Divide by 13"]
1043 pub const DIVIDE_13: u32 = 0x0c;
1044 #[doc = "Divide by 14"]
1045 pub const DIVIDE_14: u32 = 0x0d;
1046 #[doc = "Divide by 15"]
1047 pub const DIVIDE_15: u32 = 0x0e;
1048 #[doc = "Divide by 16"]
1049 pub const DIVIDE_16: u32 = 0x0f;
1050 #[doc = "Divide by 17"]
1051 pub const DIVIDE_17: u32 = 0x10;
1052 #[doc = "Divide by 18"]
1053 pub const DIVIDE_18: u32 = 0x11;
1054 #[doc = "Divide by 19"]
1055 pub const DIVIDE_19: u32 = 0x12;
1056 #[doc = "Divide by 20"]
1057 pub const DIVIDE_20: u32 = 0x13;
1058 #[doc = "Divide by 21"]
1059 pub const DIVIDE_21: u32 = 0x14;
1060 #[doc = "Divide by 22"]
1061 pub const DIVIDE_22: u32 = 0x15;
1062 #[doc = "Divide by 23"]
1063 pub const DIVIDE_23: u32 = 0x16;
1064 #[doc = "Divide by 24"]
1065 pub const DIVIDE_24: u32 = 0x17;
1066 #[doc = "Divide by 25"]
1067 pub const DIVIDE_25: u32 = 0x18;
1068 #[doc = "Divide by 26"]
1069 pub const DIVIDE_26: u32 = 0x19;
1070 #[doc = "Divide by 27"]
1071 pub const DIVIDE_27: u32 = 0x1a;
1072 #[doc = "Divide by 28"]
1073 pub const DIVIDE_28: u32 = 0x1b;
1074 #[doc = "Divide by 29"]
1075 pub const DIVIDE_29: u32 = 0x1c;
1076 #[doc = "Divide by 30"]
1077 pub const DIVIDE_30: u32 = 0x1d;
1078 #[doc = "Divide by 31"]
1079 pub const DIVIDE_31: u32 = 0x1e;
1080 #[doc = "Divide by 32"]
1081 pub const DIVIDE_32: u32 = 0x1f;
1082 #[doc = "Divide by 33"]
1083 pub const DIVIDE_33: u32 = 0x20;
1084 #[doc = "Divide by 34"]
1085 pub const DIVIDE_34: u32 = 0x21;
1086 #[doc = "Divide by 35"]
1087 pub const DIVIDE_35: u32 = 0x22;
1088 #[doc = "Divide by 36"]
1089 pub const DIVIDE_36: u32 = 0x23;
1090 #[doc = "Divide by 37"]
1091 pub const DIVIDE_37: u32 = 0x24;
1092 #[doc = "Divide by 38"]
1093 pub const DIVIDE_38: u32 = 0x25;
1094 #[doc = "Divide by 39"]
1095 pub const DIVIDE_39: u32 = 0x26;
1096 #[doc = "Divide by 40"]
1097 pub const DIVIDE_40: u32 = 0x27;
1098 #[doc = "Divide by 41"]
1099 pub const DIVIDE_41: u32 = 0x28;
1100 #[doc = "Divide by 42"]
1101 pub const DIVIDE_42: u32 = 0x29;
1102 #[doc = "Divide by 43"]
1103 pub const DIVIDE_43: u32 = 0x2a;
1104 #[doc = "Divide by 44"]
1105 pub const DIVIDE_44: u32 = 0x2b;
1106 #[doc = "Divide by 45"]
1107 pub const DIVIDE_45: u32 = 0x2c;
1108 #[doc = "Divide by 46"]
1109 pub const DIVIDE_46: u32 = 0x2d;
1110 #[doc = "Divide by 47"]
1111 pub const DIVIDE_47: u32 = 0x2e;
1112 #[doc = "Divide by 48"]
1113 pub const DIVIDE_48: u32 = 0x2f;
1114 #[doc = "Divide by 49"]
1115 pub const DIVIDE_49: u32 = 0x30;
1116 #[doc = "Divide by 50"]
1117 pub const DIVIDE_50: u32 = 0x31;
1118 #[doc = "Divide by 51"]
1119 pub const DIVIDE_51: u32 = 0x32;
1120 #[doc = "Divide by 52"]
1121 pub const DIVIDE_52: u32 = 0x33;
1122 #[doc = "Divide by 53"]
1123 pub const DIVIDE_53: u32 = 0x34;
1124 #[doc = "Divide by 54"]
1125 pub const DIVIDE_54: u32 = 0x35;
1126 #[doc = "Divide by 55"]
1127 pub const DIVIDE_55: u32 = 0x36;
1128 #[doc = "Divide by 56"]
1129 pub const DIVIDE_56: u32 = 0x37;
1130 #[doc = "Divide by 57"]
1131 pub const DIVIDE_57: u32 = 0x38;
1132 #[doc = "Divide by 58"]
1133 pub const DIVIDE_58: u32 = 0x39;
1134 #[doc = "Divide by 59"]
1135 pub const DIVIDE_59: u32 = 0x3a;
1136 #[doc = "Divide by 60"]
1137 pub const DIVIDE_60: u32 = 0x3b;
1138 #[doc = "Divide by 61"]
1139 pub const DIVIDE_61: u32 = 0x3c;
1140 #[doc = "Divide by 62"]
1141 pub const DIVIDE_62: u32 = 0x3d;
1142 #[doc = "Divide by 63"]
1143 pub const DIVIDE_63: u32 = 0x3e;
1144 #[doc = "Divide by 64"]
1145 pub const DIVIDE_64: u32 = 0x3f;
1146 }
1147 }
1148 #[doc = "Divider for sai3 clock pred."]
1149 pub mod SAI3_CLK_PRED {
1150 pub const offset: u32 = 22;
1151 pub const mask: u32 = 0x07 << offset;
1152 pub mod R {}
1153 pub mod W {}
1154 pub mod RW {
1155 #[doc = "divide by 1"]
1156 pub const SAI3_CLK_PRED_0: u32 = 0;
1157 #[doc = "divide by 2"]
1158 pub const SAI3_CLK_PRED_1: u32 = 0x01;
1159 #[doc = "divide by 3"]
1160 pub const SAI3_CLK_PRED_2: u32 = 0x02;
1161 #[doc = "divide by 4"]
1162 pub const SAI3_CLK_PRED_3: u32 = 0x03;
1163 #[doc = "divide by 5"]
1164 pub const SAI3_CLK_PRED_4: u32 = 0x04;
1165 #[doc = "divide by 6"]
1166 pub const SAI3_CLK_PRED_5: u32 = 0x05;
1167 #[doc = "divide by 7"]
1168 pub const SAI3_CLK_PRED_6: u32 = 0x06;
1169 #[doc = "divide by 8"]
1170 pub const SAI3_CLK_PRED_7: u32 = 0x07;
1171 }
1172 }
1173 #[doc = "Divider for flexio1 clock. Divider should be updated when output clock is gated."]
1174 pub mod FLEXIO1_CLK_PODF {
1175 pub const offset: u32 = 25;
1176 pub const mask: u32 = 0x0f << offset;
1177 pub mod R {}
1178 pub mod W {}
1179 pub mod RW {
1180 #[doc = "Divide by 1"]
1181 pub const DIVIDE_1: u32 = 0;
1182 #[doc = "Divide by 2"]
1183 pub const DIVIDE_2: u32 = 0x01;
1184 #[doc = "Divide by 3"]
1185 pub const DIVIDE_3: u32 = 0x02;
1186 #[doc = "Divide by 4"]
1187 pub const DIVIDE_4: u32 = 0x03;
1188 #[doc = "Divide by 5"]
1189 pub const DIVIDE_5: u32 = 0x04;
1190 #[doc = "Divide by 6"]
1191 pub const DIVIDE_6: u32 = 0x05;
1192 #[doc = "Divide by 7"]
1193 pub const DIVIDE_7: u32 = 0x06;
1194 #[doc = "Divide by 8"]
1195 pub const DIVIDE_8: u32 = 0x07;
1196 #[doc = "Divide by 9"]
1197 pub const DIVIDE_9: u32 = 0x08;
1198 #[doc = "Divide by 10"]
1199 pub const DIVIDE_10: u32 = 0x09;
1200 #[doc = "Divide by 11"]
1201 pub const DIVIDE_11: u32 = 0x0a;
1202 #[doc = "Divide by 12"]
1203 pub const DIVIDE_12: u32 = 0x0b;
1204 #[doc = "Divide by 13"]
1205 pub const DIVIDE_13: u32 = 0x0c;
1206 #[doc = "Divide by 14"]
1207 pub const DIVIDE_14: u32 = 0x0d;
1208 #[doc = "Divide by 15"]
1209 pub const DIVIDE_15: u32 = 0x0e;
1210 #[doc = "Divide by 16"]
1211 pub const DIVIDE_16: u32 = 0x0f;
1212 }
1213 }
1214}
1215#[doc = "CCM D1 Clock Divider Register"]
1216pub mod CDCDR {
1217 #[doc = "Selector for spdif0 clock multiplexer"]
1218 pub mod SPDIF0_CLK_SEL {
1219 pub const offset: u32 = 20;
1220 pub const mask: u32 = 0x03 << offset;
1221 pub mod R {}
1222 pub mod W {}
1223 pub mod RW {
1224 #[doc = "derive clock from PLL4"]
1225 pub const SPDIF0_CLK_SEL_0: u32 = 0;
1226 #[doc = "derive clock from PLL3 PFD2"]
1227 pub const SPDIF0_CLK_SEL_1: u32 = 0x01;
1228 #[doc = "derive clock from pll3_sw_clk"]
1229 pub const SPDIF0_CLK_SEL_3: u32 = 0x03;
1230 }
1231 }
1232 #[doc = "Divider for spdif0 clock podf. Divider should be updated when output clock is gated."]
1233 pub mod SPDIF0_CLK_PODF {
1234 pub const offset: u32 = 22;
1235 pub const mask: u32 = 0x07 << offset;
1236 pub mod R {}
1237 pub mod W {}
1238 pub mod RW {
1239 #[doc = "Divide by 1"]
1240 pub const DIVIDE_1: u32 = 0;
1241 #[doc = "Divide by 2"]
1242 pub const DIVIDE_2: u32 = 0x01;
1243 #[doc = "Divide by 3"]
1244 pub const DIVIDE_3: u32 = 0x02;
1245 #[doc = "Divide by 4"]
1246 pub const DIVIDE_4: u32 = 0x03;
1247 #[doc = "Divide by 5"]
1248 pub const DIVIDE_5: u32 = 0x04;
1249 #[doc = "Divide by 6"]
1250 pub const DIVIDE_6: u32 = 0x05;
1251 #[doc = "Divide by 7"]
1252 pub const DIVIDE_7: u32 = 0x06;
1253 #[doc = "Divide by 8"]
1254 pub const DIVIDE_8: u32 = 0x07;
1255 }
1256 }
1257 #[doc = "Divider for spdif0 clock pred. Divider should be updated when output clock is gated."]
1258 pub mod SPDIF0_CLK_PRED {
1259 pub const offset: u32 = 25;
1260 pub const mask: u32 = 0x07 << offset;
1261 pub mod R {}
1262 pub mod W {}
1263 pub mod RW {
1264 #[doc = "Divide by 1"]
1265 pub const DIVIDE_1: u32 = 0;
1266 #[doc = "Divide by 2"]
1267 pub const DIVIDE_2: u32 = 0x01;
1268 #[doc = "Divide by 3"]
1269 pub const DIVIDE_3: u32 = 0x02;
1270 #[doc = "Divide by 4"]
1271 pub const DIVIDE_4: u32 = 0x03;
1272 #[doc = "Divide by 5"]
1273 pub const DIVIDE_5: u32 = 0x04;
1274 #[doc = "Divide by 6"]
1275 pub const DIVIDE_6: u32 = 0x05;
1276 #[doc = "Divide by 7"]
1277 pub const DIVIDE_7: u32 = 0x06;
1278 #[doc = "Divide by 8"]
1279 pub const DIVIDE_8: u32 = 0x07;
1280 }
1281 }
1282}
1283#[doc = "CCM Serial Clock Divider Register 2"]
1284pub mod CSCDR2 {
1285 #[doc = "Selector for the LPI2C clock multiplexor"]
1286 pub mod LPI2C_CLK_SEL {
1287 pub const offset: u32 = 18;
1288 pub const mask: u32 = 0x01 << offset;
1289 pub mod R {}
1290 pub mod W {}
1291 pub mod RW {
1292 #[doc = "derive clock from pll3_60m"]
1293 pub const LPI2C_CLK_SEL_0: u32 = 0;
1294 #[doc = "derive clock from osc_clk"]
1295 pub const LPI2C_CLK_SEL_1: u32 = 0x01;
1296 }
1297 }
1298 #[doc = "Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this."]
1299 pub mod LPI2C_CLK_PODF {
1300 pub const offset: u32 = 19;
1301 pub const mask: u32 = 0x3f << offset;
1302 pub mod R {}
1303 pub mod W {}
1304 pub mod RW {
1305 #[doc = "Divide by 1"]
1306 pub const DIVIDE_1: u32 = 0;
1307 #[doc = "Divide by 2"]
1308 pub const DIVIDE_2: u32 = 0x01;
1309 #[doc = "Divide by 3"]
1310 pub const DIVIDE_3: u32 = 0x02;
1311 #[doc = "Divide by 4"]
1312 pub const DIVIDE_4: u32 = 0x03;
1313 #[doc = "Divide by 5"]
1314 pub const DIVIDE_5: u32 = 0x04;
1315 #[doc = "Divide by 6"]
1316 pub const DIVIDE_6: u32 = 0x05;
1317 #[doc = "Divide by 7"]
1318 pub const DIVIDE_7: u32 = 0x06;
1319 #[doc = "Divide by 8"]
1320 pub const DIVIDE_8: u32 = 0x07;
1321 #[doc = "Divide by 9"]
1322 pub const DIVIDE_9: u32 = 0x08;
1323 #[doc = "Divide by 10"]
1324 pub const DIVIDE_10: u32 = 0x09;
1325 #[doc = "Divide by 11"]
1326 pub const DIVIDE_11: u32 = 0x0a;
1327 #[doc = "Divide by 12"]
1328 pub const DIVIDE_12: u32 = 0x0b;
1329 #[doc = "Divide by 13"]
1330 pub const DIVIDE_13: u32 = 0x0c;
1331 #[doc = "Divide by 14"]
1332 pub const DIVIDE_14: u32 = 0x0d;
1333 #[doc = "Divide by 15"]
1334 pub const DIVIDE_15: u32 = 0x0e;
1335 #[doc = "Divide by 16"]
1336 pub const DIVIDE_16: u32 = 0x0f;
1337 #[doc = "Divide by 17"]
1338 pub const DIVIDE_17: u32 = 0x10;
1339 #[doc = "Divide by 18"]
1340 pub const DIVIDE_18: u32 = 0x11;
1341 #[doc = "Divide by 19"]
1342 pub const DIVIDE_19: u32 = 0x12;
1343 #[doc = "Divide by 20"]
1344 pub const DIVIDE_20: u32 = 0x13;
1345 #[doc = "Divide by 21"]
1346 pub const DIVIDE_21: u32 = 0x14;
1347 #[doc = "Divide by 22"]
1348 pub const DIVIDE_22: u32 = 0x15;
1349 #[doc = "Divide by 23"]
1350 pub const DIVIDE_23: u32 = 0x16;
1351 #[doc = "Divide by 24"]
1352 pub const DIVIDE_24: u32 = 0x17;
1353 #[doc = "Divide by 25"]
1354 pub const DIVIDE_25: u32 = 0x18;
1355 #[doc = "Divide by 26"]
1356 pub const DIVIDE_26: u32 = 0x19;
1357 #[doc = "Divide by 27"]
1358 pub const DIVIDE_27: u32 = 0x1a;
1359 #[doc = "Divide by 28"]
1360 pub const DIVIDE_28: u32 = 0x1b;
1361 #[doc = "Divide by 29"]
1362 pub const DIVIDE_29: u32 = 0x1c;
1363 #[doc = "Divide by 30"]
1364 pub const DIVIDE_30: u32 = 0x1d;
1365 #[doc = "Divide by 31"]
1366 pub const DIVIDE_31: u32 = 0x1e;
1367 #[doc = "Divide by 32"]
1368 pub const DIVIDE_32: u32 = 0x1f;
1369 #[doc = "Divide by 33"]
1370 pub const DIVIDE_33: u32 = 0x20;
1371 #[doc = "Divide by 34"]
1372 pub const DIVIDE_34: u32 = 0x21;
1373 #[doc = "Divide by 35"]
1374 pub const DIVIDE_35: u32 = 0x22;
1375 #[doc = "Divide by 36"]
1376 pub const DIVIDE_36: u32 = 0x23;
1377 #[doc = "Divide by 37"]
1378 pub const DIVIDE_37: u32 = 0x24;
1379 #[doc = "Divide by 38"]
1380 pub const DIVIDE_38: u32 = 0x25;
1381 #[doc = "Divide by 39"]
1382 pub const DIVIDE_39: u32 = 0x26;
1383 #[doc = "Divide by 40"]
1384 pub const DIVIDE_40: u32 = 0x27;
1385 #[doc = "Divide by 41"]
1386 pub const DIVIDE_41: u32 = 0x28;
1387 #[doc = "Divide by 42"]
1388 pub const DIVIDE_42: u32 = 0x29;
1389 #[doc = "Divide by 43"]
1390 pub const DIVIDE_43: u32 = 0x2a;
1391 #[doc = "Divide by 44"]
1392 pub const DIVIDE_44: u32 = 0x2b;
1393 #[doc = "Divide by 45"]
1394 pub const DIVIDE_45: u32 = 0x2c;
1395 #[doc = "Divide by 46"]
1396 pub const DIVIDE_46: u32 = 0x2d;
1397 #[doc = "Divide by 47"]
1398 pub const DIVIDE_47: u32 = 0x2e;
1399 #[doc = "Divide by 48"]
1400 pub const DIVIDE_48: u32 = 0x2f;
1401 #[doc = "Divide by 49"]
1402 pub const DIVIDE_49: u32 = 0x30;
1403 #[doc = "Divide by 50"]
1404 pub const DIVIDE_50: u32 = 0x31;
1405 #[doc = "Divide by 51"]
1406 pub const DIVIDE_51: u32 = 0x32;
1407 #[doc = "Divide by 52"]
1408 pub const DIVIDE_52: u32 = 0x33;
1409 #[doc = "Divide by 53"]
1410 pub const DIVIDE_53: u32 = 0x34;
1411 #[doc = "Divide by 54"]
1412 pub const DIVIDE_54: u32 = 0x35;
1413 #[doc = "Divide by 55"]
1414 pub const DIVIDE_55: u32 = 0x36;
1415 #[doc = "Divide by 56"]
1416 pub const DIVIDE_56: u32 = 0x37;
1417 #[doc = "Divide by 57"]
1418 pub const DIVIDE_57: u32 = 0x38;
1419 #[doc = "Divide by 58"]
1420 pub const DIVIDE_58: u32 = 0x39;
1421 #[doc = "Divide by 59"]
1422 pub const DIVIDE_59: u32 = 0x3a;
1423 #[doc = "Divide by 60"]
1424 pub const DIVIDE_60: u32 = 0x3b;
1425 #[doc = "Divide by 61"]
1426 pub const DIVIDE_61: u32 = 0x3c;
1427 #[doc = "Divide by 62"]
1428 pub const DIVIDE_62: u32 = 0x3d;
1429 #[doc = "Divide by 63"]
1430 pub const DIVIDE_63: u32 = 0x3e;
1431 #[doc = "Divide by 64"]
1432 pub const DIVIDE_64: u32 = 0x3f;
1433 }
1434 }
1435}
1436#[doc = "CCM Divider Handshake In-Process Register"]
1437pub mod CDHIPR {
1438 #[doc = "Busy indicator for ahb_podf."]
1439 pub mod AHB_PODF_BUSY {
1440 pub const offset: u32 = 1;
1441 pub const mask: u32 = 0x01 << offset;
1442 pub mod R {}
1443 pub mod W {}
1444 pub mod RW {
1445 #[doc = "divider is not busy and its value represents the actual division."]
1446 pub const AHB_PODF_BUSY_0: u32 = 0;
1447 #[doc = "divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied."]
1448 pub const AHB_PODF_BUSY_1: u32 = 0x01;
1449 }
1450 }
1451 #[doc = "Busy indicator for flexspi_podf."]
1452 pub mod FLEXSPI_PODF_BUSY {
1453 pub const offset: u32 = 3;
1454 pub const mask: u32 = 0x01 << offset;
1455 pub mod R {}
1456 pub mod W {}
1457 pub mod RW {
1458 #[doc = "divider is not busy and its value represents the actual division."]
1459 pub const FLEXSPI_PODF_BUSY_0: u32 = 0;
1460 #[doc = "divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the flexspi_podf will be applied."]
1461 pub const FLEXSPI_PODF_BUSY_1: u32 = 0x01;
1462 }
1463 }
1464 #[doc = "Busy indicator for perclk_podf."]
1465 pub mod PERCLK_PODF_BUSY {
1466 pub const offset: u32 = 4;
1467 pub const mask: u32 = 0x01 << offset;
1468 pub mod R {}
1469 pub mod W {}
1470 pub mod RW {
1471 #[doc = "divider is not busy and its value represents the actual division."]
1472 pub const PERCLK_PODF_BUSY_0: u32 = 0;
1473 #[doc = "divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the perclk_podf will be applied."]
1474 pub const PERCLK_PODF_BUSY_1: u32 = 0x01;
1475 }
1476 }
1477 #[doc = "Busy indicator for periph_clk_sel mux control."]
1478 pub mod PERIPH_CLK_SEL_BUSY {
1479 pub const offset: u32 = 5;
1480 pub const mask: u32 = 0x01 << offset;
1481 pub mod R {}
1482 pub mod W {}
1483 pub mod RW {
1484 #[doc = "mux is not busy and its value represents the actual division."]
1485 pub const PERIPH_CLK_SEL_BUSY_0: u32 = 0;
1486 #[doc = "mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied."]
1487 pub const PERIPH_CLK_SEL_BUSY_1: u32 = 0x01;
1488 }
1489 }
1490}
1491#[doc = "CCM Low Power Control Register"]
1492pub mod CLPCR {
1493 #[doc = "Setting the low power mode that system will enter on next assertion of dsm_request signal."]
1494 pub mod LPM {
1495 pub const offset: u32 = 0;
1496 pub const mask: u32 = 0x03 << offset;
1497 pub mod R {}
1498 pub mod W {}
1499 pub mod RW {
1500 #[doc = "Remain in run mode"]
1501 pub const LPM_0: u32 = 0;
1502 #[doc = "Transfer to wait mode"]
1503 pub const LPM_1: u32 = 0x01;
1504 #[doc = "Transfer to stop mode"]
1505 pub const LPM_2: u32 = 0x02;
1506 }
1507 }
1508 #[doc = "Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode"]
1509 pub mod ARM_CLK_DIS_ON_LPM {
1510 pub const offset: u32 = 5;
1511 pub const mask: u32 = 0x01 << offset;
1512 pub mod R {}
1513 pub mod W {}
1514 pub mod RW {
1515 #[doc = "ARM clock enabled on wait mode."]
1516 pub const ARM_CLK_DIS_ON_LPM_0: u32 = 0;
1517 #[doc = "ARM clock disabled on wait mode. ."]
1518 pub const ARM_CLK_DIS_ON_LPM_1: u32 = 0x01;
1519 }
1520 }
1521 #[doc = "Standby clock oscillator bit"]
1522 pub mod SBYOS {
1523 pub const offset: u32 = 6;
1524 pub const mask: u32 = 0x01 << offset;
1525 pub mod R {}
1526 pub mod W {}
1527 pub mod RW {
1528 #[doc = "On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0')"]
1529 pub const SBYOS_0: u32 = 0;
1530 #[doc = "On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process."]
1531 pub const SBYOS_1: u32 = 0x01;
1532 }
1533 }
1534 #[doc = "dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i"]
1535 pub mod DIS_REF_OSC {
1536 pub const offset: u32 = 7;
1537 pub const mask: u32 = 0x01 << offset;
1538 pub mod R {}
1539 pub mod W {}
1540 pub mod RW {
1541 #[doc = "external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'."]
1542 pub const DIS_REF_OSC_0: u32 = 0;
1543 #[doc = "external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'"]
1544 pub const DIS_REF_OSC_1: u32 = 0x01;
1545 }
1546 }
1547 #[doc = "Voltage standby request bit"]
1548 pub mod VSTBY {
1549 pub const offset: u32 = 8;
1550 pub const mask: u32 = 0x01 << offset;
1551 pub mod R {}
1552 pub mod W {}
1553 pub mod RW {
1554 #[doc = "Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')"]
1555 pub const VSTBY_0: u32 = 0;
1556 #[doc = "Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1')."]
1557 pub const VSTBY_1: u32 = 0x01;
1558 }
1559 }
1560 #[doc = "Standby counter definition"]
1561 pub mod STBY_COUNT {
1562 pub const offset: u32 = 9;
1563 pub const mask: u32 = 0x03 << offset;
1564 pub mod R {}
1565 pub mod W {}
1566 pub mod RW {
1567 #[doc = "CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles"]
1568 pub const STBY_COUNT_0: u32 = 0;
1569 #[doc = "CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles"]
1570 pub const STBY_COUNT_1: u32 = 0x01;
1571 #[doc = "CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles"]
1572 pub const STBY_COUNT_2: u32 = 0x02;
1573 #[doc = "CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles"]
1574 pub const STBY_COUNT_3: u32 = 0x03;
1575 }
1576 }
1577 #[doc = "In run mode, software can manually control powering down of on chip oscillator, i"]
1578 pub mod COSC_PWRDOWN {
1579 pub const offset: u32 = 11;
1580 pub const mask: u32 = 0x01 << offset;
1581 pub mod R {}
1582 pub mod W {}
1583 pub mod RW {
1584 #[doc = "On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'."]
1585 pub const COSC_PWRDOWN_0: u32 = 0;
1586 #[doc = "On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'."]
1587 pub const COSC_PWRDOWN_1: u32 = 0x01;
1588 }
1589 }
1590 #[doc = "Mask WFI of core0 for entering low power mode Assertion of all bits\\[27:22\\] will generate low power mode request"]
1591 pub mod MASK_CORE0_WFI {
1592 pub const offset: u32 = 22;
1593 pub const mask: u32 = 0x01 << offset;
1594 pub mod R {}
1595 pub mod W {}
1596 pub mod RW {
1597 #[doc = "WFI of core0 is not masked"]
1598 pub const MASK_CORE0_WFI_0: u32 = 0;
1599 #[doc = "WFI of core0 is masked"]
1600 pub const MASK_CORE0_WFI_1: u32 = 0x01;
1601 }
1602 }
1603 #[doc = "Mask SCU IDLE for entering low power mode Assertion of all bits\\[27:22\\] will generate low power mode request"]
1604 pub mod MASK_SCU_IDLE {
1605 pub const offset: u32 = 26;
1606 pub const mask: u32 = 0x01 << offset;
1607 pub mod R {}
1608 pub mod W {}
1609 pub mod RW {
1610 #[doc = "SCU IDLE is not masked"]
1611 pub const MASK_SCU_IDLE_0: u32 = 0;
1612 #[doc = "SCU IDLE is masked"]
1613 pub const MASK_SCU_IDLE_1: u32 = 0x01;
1614 }
1615 }
1616 #[doc = "Mask L2CC IDLE for entering low power mode"]
1617 pub mod MASK_L2CC_IDLE {
1618 pub const offset: u32 = 27;
1619 pub const mask: u32 = 0x01 << offset;
1620 pub mod R {}
1621 pub mod W {}
1622 pub mod RW {
1623 #[doc = "L2CC IDLE is not masked"]
1624 pub const MASK_L2CC_IDLE_0: u32 = 0;
1625 #[doc = "L2CC IDLE is masked"]
1626 pub const MASK_L2CC_IDLE_1: u32 = 0x01;
1627 }
1628 }
1629}
1630#[doc = "CCM Interrupt Status Register"]
1631pub mod CISR {
1632 #[doc = "CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs"]
1633 pub mod LRF_PLL {
1634 pub const offset: u32 = 0;
1635 pub const mask: u32 = 0x01 << offset;
1636 pub mod R {}
1637 pub mod W {}
1638 pub mod RW {
1639 #[doc = "interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs"]
1640 pub const LRF_PLL_0: u32 = 0;
1641 #[doc = "interrupt generated due to lock ready of all enabled and not bypaseed PLLs"]
1642 pub const LRF_PLL_1: u32 = 0x01;
1643 }
1644 }
1645 #[doc = "CCM interrupt request 2 generated due to on board oscillator ready, i"]
1646 pub mod COSC_READY {
1647 pub const offset: u32 = 6;
1648 pub const mask: u32 = 0x01 << offset;
1649 pub mod R {}
1650 pub mod W {}
1651 pub mod RW {
1652 #[doc = "interrupt is not generated due to on board oscillator ready"]
1653 pub const COSC_READY_0: u32 = 0;
1654 #[doc = "interrupt generated due to on board oscillator ready"]
1655 pub const COSC_READY_1: u32 = 0x01;
1656 }
1657 }
1658 #[doc = "CCM interrupt request 1 generated due to frequency change of flexspi_podf"]
1659 pub mod FLEXSPI_PODF_LOADED {
1660 pub const offset: u32 = 16;
1661 pub const mask: u32 = 0x01 << offset;
1662 pub mod R {}
1663 pub mod W {}
1664 pub mod RW {
1665 #[doc = "interrupt is not generated due to frequency change of flexspi_podf"]
1666 pub const FLEXSPI_PODF_LOADED_0: u32 = 0;
1667 #[doc = "interrupt generated due to frequency change of flexspi_podf"]
1668 pub const FLEXSPI_PODF_LOADED_1: u32 = 0x01;
1669 }
1670 }
1671 #[doc = "CCM interrupt request 1 generated due to frequency change of perclk_podf"]
1672 pub mod PERCLK_PODF_LOADED {
1673 pub const offset: u32 = 18;
1674 pub const mask: u32 = 0x01 << offset;
1675 pub mod R {}
1676 pub mod W {}
1677 pub mod RW {
1678 #[doc = "interrupt is not generated due to frequency change of perclk_podf"]
1679 pub const PERCLK_PODF_LOADED_0: u32 = 0;
1680 #[doc = "interrupt generated due to frequency change of perclk_podf"]
1681 pub const PERCLK_PODF_LOADED_1: u32 = 0x01;
1682 }
1683 }
1684 #[doc = "CCM interrupt request 1 generated due to frequency change of ahb_podf"]
1685 pub mod AHB_PODF_LOADED {
1686 pub const offset: u32 = 20;
1687 pub const mask: u32 = 0x01 << offset;
1688 pub mod R {}
1689 pub mod W {}
1690 pub mod RW {
1691 #[doc = "interrupt is not generated due to frequency change of ahb_podf"]
1692 pub const AHB_PODF_LOADED_0: u32 = 0;
1693 #[doc = "interrupt generated due to frequency change of ahb_podf"]
1694 pub const AHB_PODF_LOADED_1: u32 = 0x01;
1695 }
1696 }
1697 #[doc = "CCM interrupt request 1 generated due to update of periph_clk_sel."]
1698 pub mod PERIPH_CLK_SEL_LOADED {
1699 pub const offset: u32 = 22;
1700 pub const mask: u32 = 0x01 << offset;
1701 pub mod R {}
1702 pub mod W {}
1703 pub mod RW {
1704 #[doc = "interrupt is not generated due to update of periph_clk_sel."]
1705 pub const PERIPH_CLK_SEL_LOADED_0: u32 = 0;
1706 #[doc = "interrupt generated due to update of periph_clk_sel."]
1707 pub const PERIPH_CLK_SEL_LOADED_1: u32 = 0x01;
1708 }
1709 }
1710}
1711#[doc = "CCM Interrupt Mask Register"]
1712pub mod CIMR {
1713 #[doc = "mask interrupt generation due to lrf of PLLs"]
1714 pub mod MASK_LRF_PLL {
1715 pub const offset: u32 = 0;
1716 pub const mask: u32 = 0x01 << offset;
1717 pub mod R {}
1718 pub mod W {}
1719 pub mod RW {
1720 #[doc = "don't mask interrupt due to lrf of PLLs - interrupt will be created"]
1721 pub const MASK_LRF_PLL_0: u32 = 0;
1722 #[doc = "mask interrupt due to lrf of PLLs"]
1723 pub const MASK_LRF_PLL_1: u32 = 0x01;
1724 }
1725 }
1726 #[doc = "mask interrupt generation due to on board oscillator ready"]
1727 pub mod MASK_COSC_READY {
1728 pub const offset: u32 = 6;
1729 pub const mask: u32 = 0x01 << offset;
1730 pub mod R {}
1731 pub mod W {}
1732 pub mod RW {
1733 #[doc = "don't mask interrupt due to on board oscillator ready - interrupt will be created"]
1734 pub const MASK_COSC_READY_0: u32 = 0;
1735 #[doc = "mask interrupt due to on board oscillator ready"]
1736 pub const MASK_COSC_READY_1: u32 = 0x01;
1737 }
1738 }
1739 #[doc = "mask interrupt generation due to update of flexspi_podf"]
1740 pub mod MASK_FLEXSPI_PODF_LOADED {
1741 pub const offset: u32 = 16;
1742 pub const mask: u32 = 0x01 << offset;
1743 pub mod R {}
1744 pub mod W {}
1745 pub mod RW {
1746 #[doc = "don't mask interrupt due to update of flexspi_podf"]
1747 pub const MASK_FLEXSPI_PODF_LOADED_0: u32 = 0;
1748 #[doc = "mask interrupt due to update of flexspi_podf"]
1749 pub const MASK_FLEXSPI_PODF_LOADED_1: u32 = 0x01;
1750 }
1751 }
1752 #[doc = "mask interrupt generation due to update of perclk_podf"]
1753 pub mod MASK_PERCLK_PODF_LOADED {
1754 pub const offset: u32 = 18;
1755 pub const mask: u32 = 0x01 << offset;
1756 pub mod R {}
1757 pub mod W {}
1758 pub mod RW {
1759 #[doc = "don't mask interrupt due to update of perclk_podf"]
1760 pub const MASK_PERCLK_PODF_LOADED_0: u32 = 0;
1761 #[doc = "mask interrupt due to update of perclk_podf"]
1762 pub const MASK_PERCLK_PODF_LOADED_1: u32 = 0x01;
1763 }
1764 }
1765 #[doc = "mask interrupt generation due to frequency change of ahb_podf"]
1766 pub mod MASK_AHB_PODF_LOADED {
1767 pub const offset: u32 = 20;
1768 pub const mask: u32 = 0x01 << offset;
1769 pub mod R {}
1770 pub mod W {}
1771 pub mod RW {
1772 #[doc = "don't mask interrupt due to frequency change of ahb_podf - interrupt will be created"]
1773 pub const MASK_AHB_PODF_LOADED_0: u32 = 0;
1774 #[doc = "mask interrupt due to frequency change of ahb_podf"]
1775 pub const MASK_AHB_PODF_LOADED_1: u32 = 0x01;
1776 }
1777 }
1778 #[doc = "mask interrupt generation due to update of periph_clk_sel."]
1779 pub mod MASK_PERIPH_CLK_SEL_LOADED {
1780 pub const offset: u32 = 22;
1781 pub const mask: u32 = 0x01 << offset;
1782 pub mod R {}
1783 pub mod W {}
1784 pub mod RW {
1785 #[doc = "don't mask interrupt due to update of periph_clk_sel - interrupt will be created"]
1786 pub const MASK_PERIPH_CLK_SEL_LOADED_0: u32 = 0;
1787 #[doc = "mask interrupt due to update of periph_clk_sel"]
1788 pub const MASK_PERIPH_CLK_SEL_LOADED_1: u32 = 0x01;
1789 }
1790 }
1791}
1792#[doc = "CCM Clock Output Source Register"]
1793pub mod CCOSR {
1794 #[doc = "Selection of the clock to be generated on CCM_CLKO1"]
1795 pub mod CLKO1_SEL {
1796 pub const offset: u32 = 0;
1797 pub const mask: u32 = 0x0f << offset;
1798 pub mod R {}
1799 pub mod W {}
1800 pub mod RW {
1801 #[doc = "pll3_sw_clk (divided by 2)"]
1802 pub const CLKO1_SEL_0: u32 = 0;
1803 #[doc = "PLL2 (divided by 2)"]
1804 pub const CLKO1_SEL_1: u32 = 0x01;
1805 #[doc = "ENET PLL (divided by 2)"]
1806 pub const CLKO1_SEL_2: u32 = 0x02;
1807 #[doc = "core_clk_root"]
1808 pub const CLKO1_SEL_11: u32 = 0x0b;
1809 #[doc = "ipg_clk_root"]
1810 pub const CLKO1_SEL_12: u32 = 0x0c;
1811 #[doc = "perclk_root"]
1812 pub const CLKO1_SEL_13: u32 = 0x0d;
1813 #[doc = "pll4_main_clk"]
1814 pub const CLKO1_SEL_15: u32 = 0x0f;
1815 }
1816 }
1817 #[doc = "Setting the divider of CCM_CLKO1"]
1818 pub mod CLKO1_DIV {
1819 pub const offset: u32 = 4;
1820 pub const mask: u32 = 0x07 << offset;
1821 pub mod R {}
1822 pub mod W {}
1823 pub mod RW {
1824 #[doc = "divide by 1"]
1825 pub const CLKO1_DIV_0: u32 = 0;
1826 #[doc = "divide by 2"]
1827 pub const CLKO1_DIV_1: u32 = 0x01;
1828 #[doc = "divide by 3"]
1829 pub const CLKO1_DIV_2: u32 = 0x02;
1830 #[doc = "divide by 4"]
1831 pub const CLKO1_DIV_3: u32 = 0x03;
1832 #[doc = "divide by 5"]
1833 pub const CLKO1_DIV_4: u32 = 0x04;
1834 #[doc = "divide by 6"]
1835 pub const CLKO1_DIV_5: u32 = 0x05;
1836 #[doc = "divide by 7"]
1837 pub const CLKO1_DIV_6: u32 = 0x06;
1838 #[doc = "divide by 8"]
1839 pub const CLKO1_DIV_7: u32 = 0x07;
1840 }
1841 }
1842 #[doc = "Enable of CCM_CLKO1 clock"]
1843 pub mod CLKO1_EN {
1844 pub const offset: u32 = 7;
1845 pub const mask: u32 = 0x01 << offset;
1846 pub mod R {}
1847 pub mod W {}
1848 pub mod RW {
1849 #[doc = "CCM_CLKO1 disabled."]
1850 pub const CLKO1_EN_0: u32 = 0;
1851 #[doc = "CCM_CLKO1 enabled."]
1852 pub const CLKO1_EN_1: u32 = 0x01;
1853 }
1854 }
1855 #[doc = "CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks"]
1856 pub mod CLK_OUT_SEL {
1857 pub const offset: u32 = 8;
1858 pub const mask: u32 = 0x01 << offset;
1859 pub mod R {}
1860 pub mod W {}
1861 pub mod RW {
1862 #[doc = "CCM_CLKO1 output drives CCM_CLKO1 clock"]
1863 pub const CLK_OUT_SEL_0: u32 = 0;
1864 #[doc = "CCM_CLKO1 output drives CCM_CLKO2 clock"]
1865 pub const CLK_OUT_SEL_1: u32 = 0x01;
1866 }
1867 }
1868 #[doc = "Selection of the clock to be generated on CCM_CLKO2"]
1869 pub mod CLKO2_SEL {
1870 pub const offset: u32 = 16;
1871 pub const mask: u32 = 0x1f << offset;
1872 pub mod R {}
1873 pub mod W {}
1874 pub mod RW {
1875 #[doc = "lpi2c_clk_root"]
1876 pub const CLKO2_SEL_6: u32 = 0x06;
1877 #[doc = "osc_clk"]
1878 pub const CLKO2_SEL_14: u32 = 0x0e;
1879 #[doc = "lpspi_clk_root"]
1880 pub const CLKO2_SEL_16: u32 = 0x10;
1881 #[doc = "sai1_clk_root"]
1882 pub const CLKO2_SEL_18: u32 = 0x12;
1883 #[doc = "sai3_clk_root"]
1884 pub const CLKO2_SEL_20: u32 = 0x14;
1885 #[doc = "trace_clk_root"]
1886 pub const CLKO2_SEL_22: u32 = 0x16;
1887 #[doc = "flexspi_clk_root"]
1888 pub const CLKO2_SEL_27: u32 = 0x1b;
1889 #[doc = "uart_clk_root"]
1890 pub const CLKO2_SEL_28: u32 = 0x1c;
1891 #[doc = "spdif0_clk_root"]
1892 pub const CLKO2_SEL_29: u32 = 0x1d;
1893 }
1894 }
1895 #[doc = "Setting the divider of CCM_CLKO2"]
1896 pub mod CLKO2_DIV {
1897 pub const offset: u32 = 21;
1898 pub const mask: u32 = 0x07 << offset;
1899 pub mod R {}
1900 pub mod W {}
1901 pub mod RW {
1902 #[doc = "divide by 1"]
1903 pub const CLKO2_DIV_0: u32 = 0;
1904 #[doc = "divide by 2"]
1905 pub const CLKO2_DIV_1: u32 = 0x01;
1906 #[doc = "divide by 3"]
1907 pub const CLKO2_DIV_2: u32 = 0x02;
1908 #[doc = "divide by 4"]
1909 pub const CLKO2_DIV_3: u32 = 0x03;
1910 #[doc = "divide by 5"]
1911 pub const CLKO2_DIV_4: u32 = 0x04;
1912 #[doc = "divide by 6"]
1913 pub const CLKO2_DIV_5: u32 = 0x05;
1914 #[doc = "divide by 7"]
1915 pub const CLKO2_DIV_6: u32 = 0x06;
1916 #[doc = "divide by 8"]
1917 pub const CLKO2_DIV_7: u32 = 0x07;
1918 }
1919 }
1920 #[doc = "Enable of CCM_CLKO2 clock"]
1921 pub mod CLKO2_EN {
1922 pub const offset: u32 = 24;
1923 pub const mask: u32 = 0x01 << offset;
1924 pub mod R {}
1925 pub mod W {}
1926 pub mod RW {
1927 #[doc = "CCM_CLKO2 disabled."]
1928 pub const CLKO2_EN_0: u32 = 0;
1929 #[doc = "CCM_CLKO2 enabled."]
1930 pub const CLKO2_EN_1: u32 = 0x01;
1931 }
1932 }
1933}
1934#[doc = "CCM General Purpose Register"]
1935pub mod CGPR {
1936 #[doc = "Defines clock dividion of clock for stby_count (pmic delay counter)"]
1937 pub mod PMIC_DELAY_SCALER {
1938 pub const offset: u32 = 0;
1939 pub const mask: u32 = 0x01 << offset;
1940 pub mod R {}
1941 pub mod W {}
1942 pub mod RW {
1943 #[doc = "clock is not divided"]
1944 pub const PMIC_DELAY_SCALER_0: u32 = 0;
1945 #[doc = "clock is divided /8"]
1946 pub const PMIC_DELAY_SCALER_1: u32 = 0x01;
1947 }
1948 }
1949 #[doc = "Defines the value of the output signal cgpr_dout\\[4\\]. Gate of program supply for efuse programing"]
1950 pub mod EFUSE_PROG_SUPPLY_GATE {
1951 pub const offset: u32 = 4;
1952 pub const mask: u32 = 0x01 << offset;
1953 pub mod R {}
1954 pub mod W {}
1955 pub mod RW {
1956 #[doc = "fuse programing supply voltage is gated off to the efuse module"]
1957 pub const EFUSE_PROG_SUPPLY_GATE_0: u32 = 0;
1958 #[doc = "allow fuse programing."]
1959 pub const EFUSE_PROG_SUPPLY_GATE_1: u32 = 0x01;
1960 }
1961 }
1962 #[doc = "System memory DS control"]
1963 pub mod SYS_MEM_DS_CTRL {
1964 pub const offset: u32 = 14;
1965 pub const mask: u32 = 0x03 << offset;
1966 pub mod R {}
1967 pub mod W {}
1968 pub mod RW {
1969 #[doc = "Disable memory DS mode always"]
1970 pub const SYS_MEM_DS_CTRL_0: u32 = 0;
1971 #[doc = "Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled"]
1972 pub const SYS_MEM_DS_CTRL_1: u32 = 0x01;
1973 #[doc = "enable memory (outside ARM platform) DS mode when system is in STOP mode"]
1974 pub const SYS_MEM_DS_CTRL_2: u32 = 0x02;
1975 }
1976 }
1977 #[doc = "Fast PLL enable."]
1978 pub mod FPL {
1979 pub const offset: u32 = 16;
1980 pub const mask: u32 = 0x01 << offset;
1981 pub mod R {}
1982 pub mod W {}
1983 pub mod RW {
1984 #[doc = "Engage PLL enable default way."]
1985 pub const FPL_0: u32 = 0;
1986 #[doc = "Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode."]
1987 pub const FPL_1: u32 = 0x01;
1988 }
1989 }
1990 #[doc = "Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal"]
1991 pub mod INT_MEM_CLK_LPM {
1992 pub const offset: u32 = 17;
1993 pub const mask: u32 = 0x01 << offset;
1994 pub mod R {}
1995 pub mod W {}
1996 pub mod RW {
1997 #[doc = "Disable the clock to the ARM platform memories when entering Low Power Mode"]
1998 pub const INT_MEM_CLK_LPM_0: u32 = 0;
1999 #[doc = "Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)"]
2000 pub const INT_MEM_CLK_LPM_1: u32 = 0x01;
2001 }
2002 }
2003}
2004#[doc = "CCM Clock Gating Register 0"]
2005pub mod CCGR0 {
2006 #[doc = "aips_tz1 clocks (aips_tz1_clk_enable)"]
2007 pub mod CG0 {
2008 pub const offset: u32 = 0;
2009 pub const mask: u32 = 0x03 << offset;
2010 pub mod R {}
2011 pub mod W {}
2012 pub mod RW {}
2013 }
2014 #[doc = "aips_tz2 clocks (aips_tz2_clk_enable)"]
2015 pub mod CG1 {
2016 pub const offset: u32 = 2;
2017 pub const mask: u32 = 0x03 << offset;
2018 pub mod R {}
2019 pub mod W {}
2020 pub mod RW {}
2021 }
2022 #[doc = "mqs clock ( mqs_hmclk_clock_enable)"]
2023 pub mod CG2 {
2024 pub const offset: u32 = 4;
2025 pub const mask: u32 = 0x03 << offset;
2026 pub mod R {}
2027 pub mod W {}
2028 pub mod RW {}
2029 }
2030 #[doc = "flexspi_exsc clock (flexspi_exsc_clk_enable)"]
2031 pub mod CG3 {
2032 pub const offset: u32 = 6;
2033 pub const mask: u32 = 0x03 << offset;
2034 pub mod R {}
2035 pub mod W {}
2036 pub mod RW {}
2037 }
2038 #[doc = "sim_m_clk_r_clk_enable"]
2039 pub mod CG4 {
2040 pub const offset: u32 = 8;
2041 pub const mask: u32 = 0x03 << offset;
2042 pub mod R {}
2043 pub mod W {}
2044 pub mod RW {}
2045 }
2046 #[doc = "dcp clock (dcp_clk_enable)"]
2047 pub mod CG5 {
2048 pub const offset: u32 = 10;
2049 pub const mask: u32 = 0x03 << offset;
2050 pub mod R {}
2051 pub mod W {}
2052 pub mod RW {}
2053 }
2054 #[doc = "lpuart3 clock (lpuart3_clk_enable)"]
2055 pub mod CG6 {
2056 pub const offset: u32 = 12;
2057 pub const mask: u32 = 0x03 << offset;
2058 pub mod R {}
2059 pub mod W {}
2060 pub mod RW {}
2061 }
2062 #[doc = "trace clock (trace_clk_enable)"]
2063 pub mod CG11 {
2064 pub const offset: u32 = 22;
2065 pub const mask: u32 = 0x03 << offset;
2066 pub mod R {}
2067 pub mod W {}
2068 pub mod RW {}
2069 }
2070 #[doc = "gpt2 bus clocks (gpt2_bus_clk_enable)"]
2071 pub mod CG12 {
2072 pub const offset: u32 = 24;
2073 pub const mask: u32 = 0x03 << offset;
2074 pub mod R {}
2075 pub mod W {}
2076 pub mod RW {}
2077 }
2078 #[doc = "gpt2 serial clocks (gpt2_serial_clk_enable)"]
2079 pub mod CG13 {
2080 pub const offset: u32 = 26;
2081 pub const mask: u32 = 0x03 << offset;
2082 pub mod R {}
2083 pub mod W {}
2084 pub mod RW {}
2085 }
2086 #[doc = "lpuart2 clock (lpuart2_clk_enable)"]
2087 pub mod CG14 {
2088 pub const offset: u32 = 28;
2089 pub const mask: u32 = 0x03 << offset;
2090 pub mod R {}
2091 pub mod W {}
2092 pub mod RW {}
2093 }
2094 #[doc = "gpio2_clocks (gpio2_clk_enable)"]
2095 pub mod CG15 {
2096 pub const offset: u32 = 30;
2097 pub const mask: u32 = 0x03 << offset;
2098 pub mod R {}
2099 pub mod W {}
2100 pub mod RW {}
2101 }
2102}
2103#[doc = "CCM Clock Gating Register 1"]
2104pub mod CCGR1 {
2105 #[doc = "lpspi1 clocks (lpspi1_clk_enable)"]
2106 pub mod CG0 {
2107 pub const offset: u32 = 0;
2108 pub const mask: u32 = 0x03 << offset;
2109 pub mod R {}
2110 pub mod W {}
2111 pub mod RW {}
2112 }
2113 #[doc = "lpspi2 clocks (lpspi2_clk_enable)"]
2114 pub mod CG1 {
2115 pub const offset: u32 = 2;
2116 pub const mask: u32 = 0x03 << offset;
2117 pub mod R {}
2118 pub mod W {}
2119 pub mod RW {}
2120 }
2121 #[doc = "pit clocks (pit_clk_enable)"]
2122 pub mod CG6 {
2123 pub const offset: u32 = 12;
2124 pub const mask: u32 = 0x03 << offset;
2125 pub mod R {}
2126 pub mod W {}
2127 pub mod RW {}
2128 }
2129 #[doc = "adc1 clock (adc1_clk_enable)"]
2130 pub mod CG8 {
2131 pub const offset: u32 = 16;
2132 pub const mask: u32 = 0x03 << offset;
2133 pub mod R {}
2134 pub mod W {}
2135 pub mod RW {}
2136 }
2137 #[doc = "gpt1 bus clock (gpt_clk_enable)"]
2138 pub mod CG10 {
2139 pub const offset: u32 = 20;
2140 pub const mask: u32 = 0x03 << offset;
2141 pub mod R {}
2142 pub mod W {}
2143 pub mod RW {}
2144 }
2145 #[doc = "gpt1 serial clock (gpt_serial_clk_enable)"]
2146 pub mod CG11 {
2147 pub const offset: u32 = 22;
2148 pub const mask: u32 = 0x03 << offset;
2149 pub mod R {}
2150 pub mod W {}
2151 pub mod RW {}
2152 }
2153 #[doc = "lpuart4 clock (lpuart4_clk_enable)"]
2154 pub mod CG12 {
2155 pub const offset: u32 = 24;
2156 pub const mask: u32 = 0x03 << offset;
2157 pub mod R {}
2158 pub mod W {}
2159 pub mod RW {}
2160 }
2161 #[doc = "gpio1 clock (gpio1_clk_enable)"]
2162 pub mod CG13 {
2163 pub const offset: u32 = 26;
2164 pub const mask: u32 = 0x03 << offset;
2165 pub mod R {}
2166 pub mod W {}
2167 pub mod RW {}
2168 }
2169 #[doc = "csu clock (csu_clk_enable)"]
2170 pub mod CG14 {
2171 pub const offset: u32 = 28;
2172 pub const mask: u32 = 0x03 << offset;
2173 pub mod R {}
2174 pub mod W {}
2175 pub mod RW {}
2176 }
2177 #[doc = "gpio5 clock (gpio5_clk_enable)"]
2178 pub mod CG15 {
2179 pub const offset: u32 = 30;
2180 pub const mask: u32 = 0x03 << offset;
2181 pub mod R {}
2182 pub mod W {}
2183 pub mod RW {}
2184 }
2185}
2186#[doc = "CCM Clock Gating Register 2"]
2187pub mod CCGR2 {
2188 #[doc = "ocram_exsc clock (ocram_exsc_clk_enable)"]
2189 pub mod CG0 {
2190 pub const offset: u32 = 0;
2191 pub const mask: u32 = 0x03 << offset;
2192 pub mod R {}
2193 pub mod W {}
2194 pub mod RW {}
2195 }
2196 #[doc = "iomuxc_snvs clock (iomuxc_snvs_clk_enable)"]
2197 pub mod CG2 {
2198 pub const offset: u32 = 4;
2199 pub const mask: u32 = 0x03 << offset;
2200 pub mod R {}
2201 pub mod W {}
2202 pub mod RW {}
2203 }
2204 #[doc = "lpi2c1 clock (lpi2c1_clk_enable)"]
2205 pub mod CG3 {
2206 pub const offset: u32 = 6;
2207 pub const mask: u32 = 0x03 << offset;
2208 pub mod R {}
2209 pub mod W {}
2210 pub mod RW {}
2211 }
2212 #[doc = "lpi2c2 clock (lpi2c2_clk_enable)"]
2213 pub mod CG4 {
2214 pub const offset: u32 = 8;
2215 pub const mask: u32 = 0x03 << offset;
2216 pub mod R {}
2217 pub mod W {}
2218 pub mod RW {}
2219 }
2220 #[doc = "OCOTP_CTRL clock (iim_clk_enable)"]
2221 pub mod CG6 {
2222 pub const offset: u32 = 12;
2223 pub const mask: u32 = 0x03 << offset;
2224 pub mod R {}
2225 pub mod W {}
2226 pub mod RW {}
2227 }
2228 #[doc = "xbar1 clock (xbar1_clk_enable)"]
2229 pub mod CG11 {
2230 pub const offset: u32 = 22;
2231 pub const mask: u32 = 0x03 << offset;
2232 pub mod R {}
2233 pub mod W {}
2234 pub mod RW {}
2235 }
2236}
2237#[doc = "CCM Clock Gating Register 3"]
2238pub mod CCGR3 {
2239 #[doc = "aoi1 clock (aoi1_clk_enable)"]
2240 pub mod CG4 {
2241 pub const offset: u32 = 8;
2242 pub const mask: u32 = 0x03 << offset;
2243 pub mod R {}
2244 pub mod W {}
2245 pub mod RW {}
2246 }
2247 #[doc = "ewm clocks (ewm_clk_enable)"]
2248 pub mod CG7 {
2249 pub const offset: u32 = 14;
2250 pub const mask: u32 = 0x03 << offset;
2251 pub mod R {}
2252 pub mod W {}
2253 pub mod RW {}
2254 }
2255 #[doc = "wdog1 clock (wdog1_clk_enable)"]
2256 pub mod CG8 {
2257 pub const offset: u32 = 16;
2258 pub const mask: u32 = 0x03 << offset;
2259 pub mod R {}
2260 pub mod W {}
2261 pub mod RW {}
2262 }
2263 #[doc = "flexram clock (flexram_clk_enable)"]
2264 pub mod CG9 {
2265 pub const offset: u32 = 18;
2266 pub const mask: u32 = 0x03 << offset;
2267 pub mod R {}
2268 pub mod W {}
2269 pub mod RW {}
2270 }
2271 #[doc = "The OCRAM clock cannot be turned off when the CM cache is running on this device."]
2272 pub mod CG14 {
2273 pub const offset: u32 = 28;
2274 pub const mask: u32 = 0x03 << offset;
2275 pub mod R {}
2276 pub mod W {}
2277 pub mod RW {}
2278 }
2279 #[doc = "iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable)"]
2280 pub mod CG15 {
2281 pub const offset: u32 = 30;
2282 pub const mask: u32 = 0x03 << offset;
2283 pub mod R {}
2284 pub mod W {}
2285 pub mod RW {}
2286 }
2287}
2288#[doc = "CCM Clock Gating Register 4"]
2289pub mod CCGR4 {
2290 #[doc = "sim_m7_clk_r_enable"]
2291 pub mod CG0 {
2292 pub const offset: u32 = 0;
2293 pub const mask: u32 = 0x03 << offset;
2294 pub mod R {}
2295 pub mod W {}
2296 pub mod RW {}
2297 }
2298 #[doc = "iomuxc clock (iomuxc_clk_enable)"]
2299 pub mod CG1 {
2300 pub const offset: u32 = 2;
2301 pub const mask: u32 = 0x03 << offset;
2302 pub mod R {}
2303 pub mod W {}
2304 pub mod RW {}
2305 }
2306 #[doc = "iomuxc gpr clock (iomuxc_gpr_clk_enable)"]
2307 pub mod CG2 {
2308 pub const offset: u32 = 4;
2309 pub const mask: u32 = 0x03 << offset;
2310 pub mod R {}
2311 pub mod W {}
2312 pub mod RW {}
2313 }
2314 #[doc = "sim_m7 clock (sim_m7_clk_enable)"]
2315 pub mod CG4 {
2316 pub const offset: u32 = 8;
2317 pub const mask: u32 = 0x03 << offset;
2318 pub mod R {}
2319 pub mod W {}
2320 pub mod RW {}
2321 }
2322 #[doc = "sim_m clocks (sim_m_clk_enable)"]
2323 pub mod CG6 {
2324 pub const offset: u32 = 12;
2325 pub const mask: u32 = 0x03 << offset;
2326 pub mod R {}
2327 pub mod W {}
2328 pub mod RW {}
2329 }
2330 #[doc = "sim_ems clocks (sim_ems_clk_enable)"]
2331 pub mod CG7 {
2332 pub const offset: u32 = 14;
2333 pub const mask: u32 = 0x03 << offset;
2334 pub mod R {}
2335 pub mod W {}
2336 pub mod RW {}
2337 }
2338 #[doc = "pwm1 clocks (pwm1_clk_enable)"]
2339 pub mod CG8 {
2340 pub const offset: u32 = 16;
2341 pub const mask: u32 = 0x03 << offset;
2342 pub mod R {}
2343 pub mod W {}
2344 pub mod RW {}
2345 }
2346 #[doc = "dma_ps clocks (dma_ps_clk_enable)"]
2347 pub mod CG15 {
2348 pub const offset: u32 = 30;
2349 pub const mask: u32 = 0x03 << offset;
2350 pub mod R {}
2351 pub mod W {}
2352 pub mod RW {}
2353 }
2354}
2355#[doc = "CCM Clock Gating Register 5"]
2356pub mod CCGR5 {
2357 #[doc = "rom clock (rom_clk_enable)"]
2358 pub mod CG0 {
2359 pub const offset: u32 = 0;
2360 pub const mask: u32 = 0x03 << offset;
2361 pub mod R {}
2362 pub mod W {}
2363 pub mod RW {}
2364 }
2365 #[doc = "flexio1 clock (flexio1_clk_enable)"]
2366 pub mod CG1 {
2367 pub const offset: u32 = 2;
2368 pub const mask: u32 = 0x03 << offset;
2369 pub mod R {}
2370 pub mod W {}
2371 pub mod RW {}
2372 }
2373 #[doc = "wdog3 clock (wdog3_clk_enable)"]
2374 pub mod CG2 {
2375 pub const offset: u32 = 4;
2376 pub const mask: u32 = 0x03 << offset;
2377 pub mod R {}
2378 pub mod W {}
2379 pub mod RW {}
2380 }
2381 #[doc = "dma clock (dma_clk_enable)"]
2382 pub mod CG3 {
2383 pub const offset: u32 = 6;
2384 pub const mask: u32 = 0x03 << offset;
2385 pub mod R {}
2386 pub mod W {}
2387 pub mod RW {}
2388 }
2389 #[doc = "kpp clock (kpp_clk_enable)"]
2390 pub mod CG4 {
2391 pub const offset: u32 = 8;
2392 pub const mask: u32 = 0x03 << offset;
2393 pub mod R {}
2394 pub mod W {}
2395 pub mod RW {}
2396 }
2397 #[doc = "wdog2 clock (wdog2_clk_enable)"]
2398 pub mod CG5 {
2399 pub const offset: u32 = 10;
2400 pub const mask: u32 = 0x03 << offset;
2401 pub mod R {}
2402 pub mod W {}
2403 pub mod RW {}
2404 }
2405 #[doc = "spdif clock (spdif_clk_enable)"]
2406 pub mod CG7 {
2407 pub const offset: u32 = 14;
2408 pub const mask: u32 = 0x03 << offset;
2409 pub mod R {}
2410 pub mod W {}
2411 pub mod RW {}
2412 }
2413 #[doc = "sai1 clock (sai1_clk_enable)"]
2414 pub mod CG9 {
2415 pub const offset: u32 = 18;
2416 pub const mask: u32 = 0x03 << offset;
2417 pub mod R {}
2418 pub mod W {}
2419 pub mod RW {}
2420 }
2421 #[doc = "sai3 clock (sai3_clk_enable)"]
2422 pub mod CG11 {
2423 pub const offset: u32 = 22;
2424 pub const mask: u32 = 0x03 << offset;
2425 pub mod R {}
2426 pub mod W {}
2427 pub mod RW {}
2428 }
2429 #[doc = "lpuart1 clock (lpuart1_clk_enable)"]
2430 pub mod CG12 {
2431 pub const offset: u32 = 24;
2432 pub const mask: u32 = 0x03 << offset;
2433 pub mod R {}
2434 pub mod W {}
2435 pub mod RW {}
2436 }
2437 #[doc = "snvs_hp clock (snvs_hp_clk_enable)"]
2438 pub mod CG14 {
2439 pub const offset: u32 = 28;
2440 pub const mask: u32 = 0x03 << offset;
2441 pub mod R {}
2442 pub mod W {}
2443 pub mod RW {}
2444 }
2445 #[doc = "snvs_lp clock (snvs_lp_clk_enable)"]
2446 pub mod CG15 {
2447 pub const offset: u32 = 30;
2448 pub const mask: u32 = 0x03 << offset;
2449 pub mod R {}
2450 pub mod W {}
2451 pub mod RW {}
2452 }
2453}
2454#[doc = "CCM Clock Gating Register 6"]
2455pub mod CCGR6 {
2456 #[doc = "usboh3 clock (usboh3_clk_enable)"]
2457 pub mod CG0 {
2458 pub const offset: u32 = 0;
2459 pub const mask: u32 = 0x03 << offset;
2460 pub mod R {}
2461 pub mod W {}
2462 pub mod RW {}
2463 }
2464 #[doc = "dcdc clocks (dcdc_clk_enable)"]
2465 pub mod CG3 {
2466 pub const offset: u32 = 6;
2467 pub const mask: u32 = 0x03 << offset;
2468 pub mod R {}
2469 pub mod W {}
2470 pub mod RW {}
2471 }
2472 #[doc = "flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared"]
2473 pub mod CG5 {
2474 pub const offset: u32 = 10;
2475 pub const mask: u32 = 0x03 << offset;
2476 pub mod R {}
2477 pub mod W {}
2478 pub mod RW {}
2479 }
2480 #[doc = "trng clock (trng_clk_enable)"]
2481 pub mod CG6 {
2482 pub const offset: u32 = 12;
2483 pub const mask: u32 = 0x03 << offset;
2484 pub mod R {}
2485 pub mod W {}
2486 pub mod RW {}
2487 }
2488 #[doc = "sim_per clock (sim_per_clk_enable)"]
2489 pub mod CG10 {
2490 pub const offset: u32 = 20;
2491 pub const mask: u32 = 0x03 << offset;
2492 pub mod R {}
2493 pub mod W {}
2494 pub mod RW {}
2495 }
2496 #[doc = "anadig clocks (anadig_clk_enable)"]
2497 pub mod CG11 {
2498 pub const offset: u32 = 22;
2499 pub const mask: u32 = 0x03 << offset;
2500 pub mod R {}
2501 pub mod W {}
2502 pub mod RW {}
2503 }
2504}
2505#[doc = "CCM Module Enable Overide Register"]
2506pub mod CMEOR {
2507 #[doc = "Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk'"]
2508 pub mod MOD_EN_OV_GPT {
2509 pub const offset: u32 = 5;
2510 pub const mask: u32 = 0x01 << offset;
2511 pub mod R {}
2512 pub mod W {}
2513 pub mod RW {
2514 #[doc = "don't override module enable signal"]
2515 pub const MOD_EN_OV_GPT_0: u32 = 0;
2516 #[doc = "override module enable signal"]
2517 pub const MOD_EN_OV_GPT_1: u32 = 0x01;
2518 }
2519 }
2520 #[doc = "Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk'"]
2521 pub mod MOD_EN_OV_PIT {
2522 pub const offset: u32 = 6;
2523 pub const mask: u32 = 0x01 << offset;
2524 pub mod R {}
2525 pub mod W {}
2526 pub mod RW {
2527 #[doc = "don't override module enable signal"]
2528 pub const MOD_EN_OV_PIT_0: u32 = 0;
2529 #[doc = "override module enable signal"]
2530 pub const MOD_EN_OV_PIT_1: u32 = 0x01;
2531 }
2532 }
2533 #[doc = "Overide clock enable signal from TRNG"]
2534 pub mod MOD_EN_OV_TRNG {
2535 pub const offset: u32 = 9;
2536 pub const mask: u32 = 0x01 << offset;
2537 pub mod R {}
2538 pub mod W {}
2539 pub mod RW {
2540 #[doc = "don't override module enable signal"]
2541 pub const MOD_EN_OV_TRNG_0: u32 = 0;
2542 #[doc = "override module enable signal"]
2543 pub const MOD_EN_OV_TRNG_1: u32 = 0x01;
2544 }
2545 }
2546}