rp2040_pac/xip_ssi/
spi_ctrlr0.rs

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1#[doc = "Register `SPI_CTRLR0` reader"]
2pub type R = crate::R<SPI_CTRLR0_SPEC>;
3#[doc = "Register `SPI_CTRLR0` writer"]
4pub type W = crate::W<SPI_CTRLR0_SPEC>;
5#[doc = "Field `TRANS_TYPE` reader - Address and instruction transfer format"]
6pub type TRANS_TYPE_R = crate::FieldReader<TRANS_TYPE_A>;
7#[doc = "Address and instruction transfer format  
8
9Value on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum TRANS_TYPE_A {
13    #[doc = "0: Command and address both in standard SPI frame format"]
14    _1C1A = 0,
15    #[doc = "1: Command in standard SPI format, address in format specified by FRF"]
16    _1C2A = 1,
17    #[doc = "2: Command and address both in format specified by FRF (e.g. Dual-SPI)"]
18    _2C2A = 2,
19}
20impl From<TRANS_TYPE_A> for u8 {
21    #[inline(always)]
22    fn from(variant: TRANS_TYPE_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for TRANS_TYPE_A {
27    type Ux = u8;
28}
29impl TRANS_TYPE_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<TRANS_TYPE_A> {
33        match self.bits {
34            0 => Some(TRANS_TYPE_A::_1C1A),
35            1 => Some(TRANS_TYPE_A::_1C2A),
36            2 => Some(TRANS_TYPE_A::_2C2A),
37            _ => None,
38        }
39    }
40    #[doc = "Command and address both in standard SPI frame format"]
41    #[inline(always)]
42    pub fn is_1c1a(&self) -> bool {
43        *self == TRANS_TYPE_A::_1C1A
44    }
45    #[doc = "Command in standard SPI format, address in format specified by FRF"]
46    #[inline(always)]
47    pub fn is_1c2a(&self) -> bool {
48        *self == TRANS_TYPE_A::_1C2A
49    }
50    #[doc = "Command and address both in format specified by FRF (e.g. Dual-SPI)"]
51    #[inline(always)]
52    pub fn is_2c2a(&self) -> bool {
53        *self == TRANS_TYPE_A::_2C2A
54    }
55}
56#[doc = "Field `TRANS_TYPE` writer - Address and instruction transfer format"]
57pub type TRANS_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TRANS_TYPE_A>;
58impl<'a, REG> TRANS_TYPE_W<'a, REG>
59where
60    REG: crate::Writable + crate::RegisterSpec,
61    REG::Ux: From<u8>,
62{
63    #[doc = "Command and address both in standard SPI frame format"]
64    #[inline(always)]
65    pub fn _1c1a(self) -> &'a mut crate::W<REG> {
66        self.variant(TRANS_TYPE_A::_1C1A)
67    }
68    #[doc = "Command in standard SPI format, address in format specified by FRF"]
69    #[inline(always)]
70    pub fn _1c2a(self) -> &'a mut crate::W<REG> {
71        self.variant(TRANS_TYPE_A::_1C2A)
72    }
73    #[doc = "Command and address both in format specified by FRF (e.g. Dual-SPI)"]
74    #[inline(always)]
75    pub fn _2c2a(self) -> &'a mut crate::W<REG> {
76        self.variant(TRANS_TYPE_A::_2C2A)
77    }
78}
79#[doc = "Field `ADDR_L` reader - Address length (0b-60b in 4b increments)"]
80pub type ADDR_L_R = crate::FieldReader;
81#[doc = "Field `ADDR_L` writer - Address length (0b-60b in 4b increments)"]
82pub type ADDR_L_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
83#[doc = "Field `INST_L` reader - Instruction length (0/4/8/16b)"]
84pub type INST_L_R = crate::FieldReader<INST_L_A>;
85#[doc = "Instruction length (0/4/8/16b)  
86
87Value on reset: 0"]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89#[repr(u8)]
90pub enum INST_L_A {
91    #[doc = "0: No instruction"]
92    NONE = 0,
93    #[doc = "1: 4-bit instruction"]
94    _4B = 1,
95    #[doc = "2: 8-bit instruction"]
96    _8B = 2,
97    #[doc = "3: 16-bit instruction"]
98    _16B = 3,
99}
100impl From<INST_L_A> for u8 {
101    #[inline(always)]
102    fn from(variant: INST_L_A) -> Self {
103        variant as _
104    }
105}
106impl crate::FieldSpec for INST_L_A {
107    type Ux = u8;
108}
109impl INST_L_R {
110    #[doc = "Get enumerated values variant"]
111    #[inline(always)]
112    pub const fn variant(&self) -> INST_L_A {
113        match self.bits {
114            0 => INST_L_A::NONE,
115            1 => INST_L_A::_4B,
116            2 => INST_L_A::_8B,
117            3 => INST_L_A::_16B,
118            _ => unreachable!(),
119        }
120    }
121    #[doc = "No instruction"]
122    #[inline(always)]
123    pub fn is_none(&self) -> bool {
124        *self == INST_L_A::NONE
125    }
126    #[doc = "4-bit instruction"]
127    #[inline(always)]
128    pub fn is_4b(&self) -> bool {
129        *self == INST_L_A::_4B
130    }
131    #[doc = "8-bit instruction"]
132    #[inline(always)]
133    pub fn is_8b(&self) -> bool {
134        *self == INST_L_A::_8B
135    }
136    #[doc = "16-bit instruction"]
137    #[inline(always)]
138    pub fn is_16b(&self) -> bool {
139        *self == INST_L_A::_16B
140    }
141}
142#[doc = "Field `INST_L` writer - Instruction length (0/4/8/16b)"]
143pub type INST_L_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INST_L_A>;
144impl<'a, REG> INST_L_W<'a, REG>
145where
146    REG: crate::Writable + crate::RegisterSpec,
147    REG::Ux: From<u8>,
148{
149    #[doc = "No instruction"]
150    #[inline(always)]
151    pub fn none(self) -> &'a mut crate::W<REG> {
152        self.variant(INST_L_A::NONE)
153    }
154    #[doc = "4-bit instruction"]
155    #[inline(always)]
156    pub fn _4b(self) -> &'a mut crate::W<REG> {
157        self.variant(INST_L_A::_4B)
158    }
159    #[doc = "8-bit instruction"]
160    #[inline(always)]
161    pub fn _8b(self) -> &'a mut crate::W<REG> {
162        self.variant(INST_L_A::_8B)
163    }
164    #[doc = "16-bit instruction"]
165    #[inline(always)]
166    pub fn _16b(self) -> &'a mut crate::W<REG> {
167        self.variant(INST_L_A::_16B)
168    }
169}
170#[doc = "Field `WAIT_CYCLES` reader - Wait cycles between control frame transmit and data reception (in SCLK cycles)"]
171pub type WAIT_CYCLES_R = crate::FieldReader;
172#[doc = "Field `WAIT_CYCLES` writer - Wait cycles between control frame transmit and data reception (in SCLK cycles)"]
173pub type WAIT_CYCLES_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
174#[doc = "Field `SPI_DDR_EN` reader - SPI DDR transfer enable"]
175pub type SPI_DDR_EN_R = crate::BitReader;
176#[doc = "Field `SPI_DDR_EN` writer - SPI DDR transfer enable"]
177pub type SPI_DDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
178#[doc = "Field `INST_DDR_EN` reader - Instruction DDR transfer enable"]
179pub type INST_DDR_EN_R = crate::BitReader;
180#[doc = "Field `INST_DDR_EN` writer - Instruction DDR transfer enable"]
181pub type INST_DDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
182#[doc = "Field `SPI_RXDS_EN` reader - Read data strobe enable"]
183pub type SPI_RXDS_EN_R = crate::BitReader;
184#[doc = "Field `SPI_RXDS_EN` writer - Read data strobe enable"]
185pub type SPI_RXDS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
186#[doc = "Field `XIP_CMD` reader - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)"]
187pub type XIP_CMD_R = crate::FieldReader;
188#[doc = "Field `XIP_CMD` writer - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)"]
189pub type XIP_CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
190impl R {
191    #[doc = "Bits 0:1 - Address and instruction transfer format"]
192    #[inline(always)]
193    pub fn trans_type(&self) -> TRANS_TYPE_R {
194        TRANS_TYPE_R::new((self.bits & 3) as u8)
195    }
196    #[doc = "Bits 2:5 - Address length (0b-60b in 4b increments)"]
197    #[inline(always)]
198    pub fn addr_l(&self) -> ADDR_L_R {
199        ADDR_L_R::new(((self.bits >> 2) & 0x0f) as u8)
200    }
201    #[doc = "Bits 8:9 - Instruction length (0/4/8/16b)"]
202    #[inline(always)]
203    pub fn inst_l(&self) -> INST_L_R {
204        INST_L_R::new(((self.bits >> 8) & 3) as u8)
205    }
206    #[doc = "Bits 11:15 - Wait cycles between control frame transmit and data reception (in SCLK cycles)"]
207    #[inline(always)]
208    pub fn wait_cycles(&self) -> WAIT_CYCLES_R {
209        WAIT_CYCLES_R::new(((self.bits >> 11) & 0x1f) as u8)
210    }
211    #[doc = "Bit 16 - SPI DDR transfer enable"]
212    #[inline(always)]
213    pub fn spi_ddr_en(&self) -> SPI_DDR_EN_R {
214        SPI_DDR_EN_R::new(((self.bits >> 16) & 1) != 0)
215    }
216    #[doc = "Bit 17 - Instruction DDR transfer enable"]
217    #[inline(always)]
218    pub fn inst_ddr_en(&self) -> INST_DDR_EN_R {
219        INST_DDR_EN_R::new(((self.bits >> 17) & 1) != 0)
220    }
221    #[doc = "Bit 18 - Read data strobe enable"]
222    #[inline(always)]
223    pub fn spi_rxds_en(&self) -> SPI_RXDS_EN_R {
224        SPI_RXDS_EN_R::new(((self.bits >> 18) & 1) != 0)
225    }
226    #[doc = "Bits 24:31 - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)"]
227    #[inline(always)]
228    pub fn xip_cmd(&self) -> XIP_CMD_R {
229        XIP_CMD_R::new(((self.bits >> 24) & 0xff) as u8)
230    }
231}
232impl W {
233    #[doc = "Bits 0:1 - Address and instruction transfer format"]
234    #[inline(always)]
235    #[must_use]
236    pub fn trans_type(&mut self) -> TRANS_TYPE_W<SPI_CTRLR0_SPEC> {
237        TRANS_TYPE_W::new(self, 0)
238    }
239    #[doc = "Bits 2:5 - Address length (0b-60b in 4b increments)"]
240    #[inline(always)]
241    #[must_use]
242    pub fn addr_l(&mut self) -> ADDR_L_W<SPI_CTRLR0_SPEC> {
243        ADDR_L_W::new(self, 2)
244    }
245    #[doc = "Bits 8:9 - Instruction length (0/4/8/16b)"]
246    #[inline(always)]
247    #[must_use]
248    pub fn inst_l(&mut self) -> INST_L_W<SPI_CTRLR0_SPEC> {
249        INST_L_W::new(self, 8)
250    }
251    #[doc = "Bits 11:15 - Wait cycles between control frame transmit and data reception (in SCLK cycles)"]
252    #[inline(always)]
253    #[must_use]
254    pub fn wait_cycles(&mut self) -> WAIT_CYCLES_W<SPI_CTRLR0_SPEC> {
255        WAIT_CYCLES_W::new(self, 11)
256    }
257    #[doc = "Bit 16 - SPI DDR transfer enable"]
258    #[inline(always)]
259    #[must_use]
260    pub fn spi_ddr_en(&mut self) -> SPI_DDR_EN_W<SPI_CTRLR0_SPEC> {
261        SPI_DDR_EN_W::new(self, 16)
262    }
263    #[doc = "Bit 17 - Instruction DDR transfer enable"]
264    #[inline(always)]
265    #[must_use]
266    pub fn inst_ddr_en(&mut self) -> INST_DDR_EN_W<SPI_CTRLR0_SPEC> {
267        INST_DDR_EN_W::new(self, 17)
268    }
269    #[doc = "Bit 18 - Read data strobe enable"]
270    #[inline(always)]
271    #[must_use]
272    pub fn spi_rxds_en(&mut self) -> SPI_RXDS_EN_W<SPI_CTRLR0_SPEC> {
273        SPI_RXDS_EN_W::new(self, 18)
274    }
275    #[doc = "Bits 24:31 - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)"]
276    #[inline(always)]
277    #[must_use]
278    pub fn xip_cmd(&mut self) -> XIP_CMD_W<SPI_CTRLR0_SPEC> {
279        XIP_CMD_W::new(self, 24)
280    }
281    #[doc = r" Writes raw bits to the register."]
282    #[doc = r""]
283    #[doc = r" # Safety"]
284    #[doc = r""]
285    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
286    #[inline(always)]
287    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
288        self.bits = bits;
289        self
290    }
291}
292#[doc = "SPI control  
293
294You can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrlr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrlr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
295pub struct SPI_CTRLR0_SPEC;
296impl crate::RegisterSpec for SPI_CTRLR0_SPEC {
297    type Ux = u32;
298}
299#[doc = "`read()` method returns [`spi_ctrlr0::R`](R) reader structure"]
300impl crate::Readable for SPI_CTRLR0_SPEC {}
301#[doc = "`write(|w| ..)` method takes [`spi_ctrlr0::W`](W) writer structure"]
302impl crate::Writable for SPI_CTRLR0_SPEC {
303    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
304    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
305}
306#[doc = "`reset()` method sets SPI_CTRLR0 to value 0x0300_0000"]
307impl crate::Resettable for SPI_CTRLR0_SPEC {
308    const RESET_VALUE: u32 = 0x0300_0000;
309}
rp2040_pac/xip_ssi/spi_ctrlr0.rs

rp2040_pac/xip_ssi/
spi_ctrlr0.rs
