rp2040_pac/sio/
gpio_out.rs

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1#[doc = "Register `GPIO_OUT` reader"]
2pub type R = crate::R<GPIO_OUT_SPEC>;
3#[doc = "Register `GPIO_OUT` writer"]
4pub type W = crate::W<GPIO_OUT_SPEC>;
5#[doc = "Field `GPIO_OUT` reader - Set output level (1/0 -> high/low) for GPIO0...29.  
6 Reading back gives the last value written, NOT the input value from the pins.  
7 If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),  
8 the result is as though the write from core 0 took place first,  
9 and the write from core 1 was then applied to that intermediate result."]
10pub type GPIO_OUT_R = crate::FieldReader<u32>;
11#[doc = "Field `GPIO_OUT` writer - Set output level (1/0 -> high/low) for GPIO0...29.  
12 Reading back gives the last value written, NOT the input value from the pins.  
13 If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),  
14 the result is as though the write from core 0 took place first,  
15 and the write from core 1 was then applied to that intermediate result."]
16pub type GPIO_OUT_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
17impl R {
18    #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29.  
19 Reading back gives the last value written, NOT the input value from the pins.  
20 If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),  
21 the result is as though the write from core 0 took place first,  
22 and the write from core 1 was then applied to that intermediate result."]
23    #[inline(always)]
24    pub fn gpio_out(&self) -> GPIO_OUT_R {
25        GPIO_OUT_R::new(self.bits & 0x3fff_ffff)
26    }
27}
28impl W {
29    #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29.  
30 Reading back gives the last value written, NOT the input value from the pins.  
31 If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),  
32 the result is as though the write from core 0 took place first,  
33 and the write from core 1 was then applied to that intermediate result."]
34    #[inline(always)]
35    #[must_use]
36    pub fn gpio_out(&mut self) -> GPIO_OUT_W<GPIO_OUT_SPEC> {
37        GPIO_OUT_W::new(self, 0)
38    }
39    #[doc = r" Writes raw bits to the register."]
40    #[doc = r""]
41    #[doc = r" # Safety"]
42    #[doc = r""]
43    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
44    #[inline(always)]
45    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
46        self.bits = bits;
47        self
48    }
49}
50#[doc = "GPIO output value  
51
52You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
53pub struct GPIO_OUT_SPEC;
54impl crate::RegisterSpec for GPIO_OUT_SPEC {
55    type Ux = u32;
56}
57#[doc = "`read()` method returns [`gpio_out::R`](R) reader structure"]
58impl crate::Readable for GPIO_OUT_SPEC {}
59#[doc = "`write(|w| ..)` method takes [`gpio_out::W`](W) writer structure"]
60impl crate::Writable for GPIO_OUT_SPEC {
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63}
64#[doc = "`reset()` method sets GPIO_OUT to value 0"]
65impl crate::Resettable for GPIO_OUT_SPEC {
66    const RESET_VALUE: u32 = 0;
67}
rp2040_pac/sio/gpio_out.rs

rp2040_pac/sio/
gpio_out.rs
