rp2040_pac/pio0/sm/
sm_clkdiv.rs

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1#[doc = "Register `SM_CLKDIV` reader"]
2pub type R = crate::R<SM_CLKDIV_SPEC>;
3#[doc = "Register `SM_CLKDIV` writer"]
4pub type W = crate::W<SM_CLKDIV_SPEC>;
5#[doc = "Field `FRAC` reader - Fractional part of clock divisor"]
6pub type FRAC_R = crate::FieldReader;
7#[doc = "Field `FRAC` writer - Fractional part of clock divisor"]
8pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `INT` reader - Effective frequency is sysclk/(int + frac/256).  
10 Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
11pub type INT_R = crate::FieldReader<u16>;
12#[doc = "Field `INT` writer - Effective frequency is sysclk/(int + frac/256).  
13 Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
14pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15impl R {
16    #[doc = "Bits 8:15 - Fractional part of clock divisor"]
17    #[inline(always)]
18    pub fn frac(&self) -> FRAC_R {
19        FRAC_R::new(((self.bits >> 8) & 0xff) as u8)
20    }
21    #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256).  
22 Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
23    #[inline(always)]
24    pub fn int(&self) -> INT_R {
25        INT_R::new(((self.bits >> 16) & 0xffff) as u16)
26    }
27}
28impl W {
29    #[doc = "Bits 8:15 - Fractional part of clock divisor"]
30    #[inline(always)]
31    #[must_use]
32    pub fn frac(&mut self) -> FRAC_W<SM_CLKDIV_SPEC> {
33        FRAC_W::new(self, 8)
34    }
35    #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256).  
36 Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
37    #[inline(always)]
38    #[must_use]
39    pub fn int(&mut self) -> INT_W<SM_CLKDIV_SPEC> {
40        INT_W::new(self, 16)
41    }
42    #[doc = r" Writes raw bits to the register."]
43    #[doc = r""]
44    #[doc = r" # Safety"]
45    #[doc = r""]
46    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
47    #[inline(always)]
48    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
49        self.bits = bits;
50        self
51    }
52}
53#[doc = "Clock divisor register for state machine 0  
54 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)  
55
56You can [`read`](crate::generic::Reg::read) this register and get [`sm_clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
57pub struct SM_CLKDIV_SPEC;
58impl crate::RegisterSpec for SM_CLKDIV_SPEC {
59    type Ux = u32;
60}
61#[doc = "`read()` method returns [`sm_clkdiv::R`](R) reader structure"]
62impl crate::Readable for SM_CLKDIV_SPEC {}
63#[doc = "`write(|w| ..)` method takes [`sm_clkdiv::W`](W) writer structure"]
64impl crate::Writable for SM_CLKDIV_SPEC {
65    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
67}
68#[doc = "`reset()` method sets SM_CLKDIV to value 0x0001_0000"]
69impl crate::Resettable for SM_CLKDIV_SPEC {
70    const RESET_VALUE: u32 = 0x0001_0000;
71}
rp2040_pac/pio0/sm/sm_clkdiv.rs

rp2040_pac/pio0/sm/
sm_clkdiv.rs
