imxrt_ral/blocks/imxrt1011/
lpi2c.rs
1#[doc = "LPI2C"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Version ID Register"]
5 pub VERID: crate::RORegister<u32>,
6 #[doc = "Parameter Register"]
7 pub PARAM: crate::RORegister<u32>,
8 _reserved0: [u8; 0x08],
9 #[doc = "Master Control Register"]
10 pub MCR: crate::RWRegister<u32>,
11 #[doc = "Master Status Register"]
12 pub MSR: crate::RWRegister<u32>,
13 #[doc = "Master Interrupt Enable Register"]
14 pub MIER: crate::RWRegister<u32>,
15 #[doc = "Master DMA Enable Register"]
16 pub MDER: crate::RWRegister<u32>,
17 #[doc = "Master Configuration Register 0"]
18 pub MCFGR0: crate::RWRegister<u32>,
19 #[doc = "Master Configuration Register 1"]
20 pub MCFGR1: crate::RWRegister<u32>,
21 #[doc = "Master Configuration Register 2"]
22 pub MCFGR2: crate::RWRegister<u32>,
23 #[doc = "Master Configuration Register 3"]
24 pub MCFGR3: crate::RWRegister<u32>,
25 _reserved1: [u8; 0x10],
26 #[doc = "Master Data Match Register"]
27 pub MDMR: crate::RWRegister<u32>,
28 _reserved2: [u8; 0x04],
29 #[doc = "Master Clock Configuration Register 0"]
30 pub MCCR0: crate::RWRegister<u32>,
31 _reserved3: [u8; 0x04],
32 #[doc = "Master Clock Configuration Register 1"]
33 pub MCCR1: crate::RWRegister<u32>,
34 _reserved4: [u8; 0x04],
35 #[doc = "Master FIFO Control Register"]
36 pub MFCR: crate::RWRegister<u32>,
37 #[doc = "Master FIFO Status Register"]
38 pub MFSR: crate::RORegister<u32>,
39 #[doc = "Master Transmit Data Register"]
40 pub MTDR: crate::WORegister<u32>,
41 _reserved5: [u8; 0x0c],
42 #[doc = "Master Receive Data Register"]
43 pub MRDR: crate::RORegister<u32>,
44 _reserved6: [u8; 0x9c],
45 #[doc = "Slave Control Register"]
46 pub SCR: crate::RWRegister<u32>,
47 #[doc = "Slave Status Register"]
48 pub SSR: crate::RWRegister<u32>,
49 #[doc = "Slave Interrupt Enable Register"]
50 pub SIER: crate::RWRegister<u32>,
51 #[doc = "Slave DMA Enable Register"]
52 pub SDER: crate::RWRegister<u32>,
53 _reserved7: [u8; 0x04],
54 #[doc = "Slave Configuration Register 1"]
55 pub SCFGR1: crate::RWRegister<u32>,
56 #[doc = "Slave Configuration Register 2"]
57 pub SCFGR2: crate::RWRegister<u32>,
58 _reserved8: [u8; 0x14],
59 #[doc = "Slave Address Match Register"]
60 pub SAMR: crate::RWRegister<u32>,
61 _reserved9: [u8; 0x0c],
62 #[doc = "Slave Address Status Register"]
63 pub SASR: crate::RORegister<u32>,
64 #[doc = "Slave Transmit ACK Register"]
65 pub STAR: crate::RWRegister<u32>,
66 _reserved10: [u8; 0x08],
67 #[doc = "Slave Transmit Data Register"]
68 pub STDR: crate::WORegister<u32>,
69 _reserved11: [u8; 0x0c],
70 #[doc = "Slave Receive Data Register"]
71 pub SRDR: crate::RORegister<u32>,
72}
73#[doc = "Version ID Register"]
74pub mod VERID {
75 #[doc = "Feature Specification Number"]
76 pub mod FEATURE {
77 pub const offset: u32 = 0;
78 pub const mask: u32 = 0xffff << offset;
79 pub mod R {}
80 pub mod W {}
81 pub mod RW {
82 #[doc = "Master only, with standard feature set"]
83 pub const FEATURE_2: u32 = 0x02;
84 #[doc = "Master and slave, with standard feature set"]
85 pub const FEATURE_3: u32 = 0x03;
86 }
87 }
88 #[doc = "Minor Version Number"]
89 pub mod MINOR {
90 pub const offset: u32 = 16;
91 pub const mask: u32 = 0xff << offset;
92 pub mod R {}
93 pub mod W {}
94 pub mod RW {}
95 }
96 #[doc = "Major Version Number"]
97 pub mod MAJOR {
98 pub const offset: u32 = 24;
99 pub const mask: u32 = 0xff << offset;
100 pub mod R {}
101 pub mod W {}
102 pub mod RW {}
103 }
104}
105#[doc = "Parameter Register"]
106pub mod PARAM {
107 #[doc = "Master Transmit FIFO Size"]
108 pub mod MTXFIFO {
109 pub const offset: u32 = 0;
110 pub const mask: u32 = 0x0f << offset;
111 pub mod R {}
112 pub mod W {}
113 pub mod RW {}
114 }
115 #[doc = "Master Receive FIFO Size"]
116 pub mod MRXFIFO {
117 pub const offset: u32 = 8;
118 pub const mask: u32 = 0x0f << offset;
119 pub mod R {}
120 pub mod W {}
121 pub mod RW {}
122 }
123}
124#[doc = "Master Control Register"]
125pub mod MCR {
126 #[doc = "Master Enable"]
127 pub mod MEN {
128 pub const offset: u32 = 0;
129 pub const mask: u32 = 0x01 << offset;
130 pub mod R {}
131 pub mod W {}
132 pub mod RW {
133 #[doc = "Master logic is disabled"]
134 pub const MEN_0: u32 = 0;
135 #[doc = "Master logic is enabled"]
136 pub const MEN_1: u32 = 0x01;
137 }
138 }
139 #[doc = "Software Reset"]
140 pub mod RST {
141 pub const offset: u32 = 1;
142 pub const mask: u32 = 0x01 << offset;
143 pub mod R {}
144 pub mod W {}
145 pub mod RW {
146 #[doc = "Master logic is not reset"]
147 pub const RST_0: u32 = 0;
148 #[doc = "Master logic is reset"]
149 pub const RST_1: u32 = 0x01;
150 }
151 }
152 #[doc = "Doze mode enable"]
153 pub mod DOZEN {
154 pub const offset: u32 = 2;
155 pub const mask: u32 = 0x01 << offset;
156 pub mod R {}
157 pub mod W {}
158 pub mod RW {
159 #[doc = "Master is enabled in Doze mode"]
160 pub const DOZEN_0: u32 = 0;
161 #[doc = "Master is disabled in Doze mode"]
162 pub const DOZEN_1: u32 = 0x01;
163 }
164 }
165 #[doc = "Debug Enable"]
166 pub mod DBGEN {
167 pub const offset: u32 = 3;
168 pub const mask: u32 = 0x01 << offset;
169 pub mod R {}
170 pub mod W {}
171 pub mod RW {
172 #[doc = "Master is disabled in debug mode"]
173 pub const DBGEN_0: u32 = 0;
174 #[doc = "Master is enabled in debug mode"]
175 pub const DBGEN_1: u32 = 0x01;
176 }
177 }
178 #[doc = "Reset Transmit FIFO"]
179 pub mod RTF {
180 pub const offset: u32 = 8;
181 pub const mask: u32 = 0x01 << offset;
182 pub mod R {}
183 pub mod W {}
184 pub mod RW {
185 #[doc = "No effect"]
186 pub const RTF_0: u32 = 0;
187 #[doc = "Transmit FIFO is reset"]
188 pub const RTF_1: u32 = 0x01;
189 }
190 }
191 #[doc = "Reset Receive FIFO"]
192 pub mod RRF {
193 pub const offset: u32 = 9;
194 pub const mask: u32 = 0x01 << offset;
195 pub mod R {}
196 pub mod W {}
197 pub mod RW {
198 #[doc = "No effect"]
199 pub const RRF_0: u32 = 0;
200 #[doc = "Receive FIFO is reset"]
201 pub const RRF_1: u32 = 0x01;
202 }
203 }
204}
205#[doc = "Master Status Register"]
206pub mod MSR {
207 #[doc = "Transmit Data Flag"]
208 pub mod TDF {
209 pub const offset: u32 = 0;
210 pub const mask: u32 = 0x01 << offset;
211 pub mod R {}
212 pub mod W {}
213 pub mod RW {
214 #[doc = "Transmit data is not requested"]
215 pub const TDF_0: u32 = 0;
216 #[doc = "Transmit data is requested"]
217 pub const TDF_1: u32 = 0x01;
218 }
219 }
220 #[doc = "Receive Data Flag"]
221 pub mod RDF {
222 pub const offset: u32 = 1;
223 pub const mask: u32 = 0x01 << offset;
224 pub mod R {}
225 pub mod W {}
226 pub mod RW {
227 #[doc = "Receive Data is not ready"]
228 pub const RDF_0: u32 = 0;
229 #[doc = "Receive data is ready"]
230 pub const RDF_1: u32 = 0x01;
231 }
232 }
233 #[doc = "End Packet Flag"]
234 pub mod EPF {
235 pub const offset: u32 = 8;
236 pub const mask: u32 = 0x01 << offset;
237 pub mod R {}
238 pub mod W {}
239 pub mod RW {
240 #[doc = "Master has not generated a STOP or Repeated START condition"]
241 pub const EPF_0: u32 = 0;
242 #[doc = "Master has generated a STOP or Repeated START condition"]
243 pub const EPF_1: u32 = 0x01;
244 }
245 }
246 #[doc = "STOP Detect Flag"]
247 pub mod SDF {
248 pub const offset: u32 = 9;
249 pub const mask: u32 = 0x01 << offset;
250 pub mod R {}
251 pub mod W {}
252 pub mod RW {
253 #[doc = "Master has not generated a STOP condition"]
254 pub const SDF_0: u32 = 0;
255 #[doc = "Master has generated a STOP condition"]
256 pub const SDF_1: u32 = 0x01;
257 }
258 }
259 #[doc = "NACK Detect Flag"]
260 pub mod NDF {
261 pub const offset: u32 = 10;
262 pub const mask: u32 = 0x01 << offset;
263 pub mod R {}
264 pub mod W {}
265 pub mod RW {
266 #[doc = "Unexpected NACK was not detected"]
267 pub const NDF_0: u32 = 0;
268 #[doc = "Unexpected NACK was detected"]
269 pub const NDF_1: u32 = 0x01;
270 }
271 }
272 #[doc = "Arbitration Lost Flag"]
273 pub mod ALF {
274 pub const offset: u32 = 11;
275 pub const mask: u32 = 0x01 << offset;
276 pub mod R {}
277 pub mod W {}
278 pub mod RW {
279 #[doc = "Master has not lost arbitration"]
280 pub const ALF_0: u32 = 0;
281 #[doc = "Master has lost arbitration"]
282 pub const ALF_1: u32 = 0x01;
283 }
284 }
285 #[doc = "FIFO Error Flag"]
286 pub mod FEF {
287 pub const offset: u32 = 12;
288 pub const mask: u32 = 0x01 << offset;
289 pub mod R {}
290 pub mod W {}
291 pub mod RW {
292 #[doc = "No error"]
293 pub const FEF_0: u32 = 0;
294 #[doc = "Master sending or receiving data without a START condition"]
295 pub const FEF_1: u32 = 0x01;
296 }
297 }
298 #[doc = "Pin Low Timeout Flag"]
299 pub mod PLTF {
300 pub const offset: u32 = 13;
301 pub const mask: u32 = 0x01 << offset;
302 pub mod R {}
303 pub mod W {}
304 pub mod RW {
305 #[doc = "Pin low timeout has not occurred or is disabled"]
306 pub const PLTF_0: u32 = 0;
307 #[doc = "Pin low timeout has occurred"]
308 pub const PLTF_1: u32 = 0x01;
309 }
310 }
311 #[doc = "Data Match Flag"]
312 pub mod DMF {
313 pub const offset: u32 = 14;
314 pub const mask: u32 = 0x01 << offset;
315 pub mod R {}
316 pub mod W {}
317 pub mod RW {
318 #[doc = "Have not received matching data"]
319 pub const DMF_0: u32 = 0;
320 #[doc = "Have received matching data"]
321 pub const DMF_1: u32 = 0x01;
322 }
323 }
324 #[doc = "Master Busy Flag"]
325 pub mod MBF {
326 pub const offset: u32 = 24;
327 pub const mask: u32 = 0x01 << offset;
328 pub mod R {}
329 pub mod W {}
330 pub mod RW {
331 #[doc = "I2C Master is idle"]
332 pub const MBF_0: u32 = 0;
333 #[doc = "I2C Master is busy"]
334 pub const MBF_1: u32 = 0x01;
335 }
336 }
337 #[doc = "Bus Busy Flag"]
338 pub mod BBF {
339 pub const offset: u32 = 25;
340 pub const mask: u32 = 0x01 << offset;
341 pub mod R {}
342 pub mod W {}
343 pub mod RW {
344 #[doc = "I2C Bus is idle"]
345 pub const BBF_0: u32 = 0;
346 #[doc = "I2C Bus is busy"]
347 pub const BBF_1: u32 = 0x01;
348 }
349 }
350}
351#[doc = "Master Interrupt Enable Register"]
352pub mod MIER {
353 #[doc = "Transmit Data Interrupt Enable"]
354 pub mod TDIE {
355 pub const offset: u32 = 0;
356 pub const mask: u32 = 0x01 << offset;
357 pub mod R {}
358 pub mod W {}
359 pub mod RW {
360 #[doc = "Disabled"]
361 pub const TDIE_0: u32 = 0;
362 #[doc = "Enabled"]
363 pub const TDIE_1: u32 = 0x01;
364 }
365 }
366 #[doc = "Receive Data Interrupt Enable"]
367 pub mod RDIE {
368 pub const offset: u32 = 1;
369 pub const mask: u32 = 0x01 << offset;
370 pub mod R {}
371 pub mod W {}
372 pub mod RW {
373 #[doc = "Disabled"]
374 pub const RDIE_0: u32 = 0;
375 #[doc = "Enabled"]
376 pub const RDIE_1: u32 = 0x01;
377 }
378 }
379 #[doc = "End Packet Interrupt Enable"]
380 pub mod EPIE {
381 pub const offset: u32 = 8;
382 pub const mask: u32 = 0x01 << offset;
383 pub mod R {}
384 pub mod W {}
385 pub mod RW {
386 #[doc = "Disabled"]
387 pub const EPIE_0: u32 = 0;
388 #[doc = "Enabled"]
389 pub const EPIE_1: u32 = 0x01;
390 }
391 }
392 #[doc = "STOP Detect Interrupt Enable"]
393 pub mod SDIE {
394 pub const offset: u32 = 9;
395 pub const mask: u32 = 0x01 << offset;
396 pub mod R {}
397 pub mod W {}
398 pub mod RW {
399 #[doc = "Disabled"]
400 pub const SDIE_0: u32 = 0;
401 #[doc = "Enabled"]
402 pub const SDIE_1: u32 = 0x01;
403 }
404 }
405 #[doc = "NACK Detect Interrupt Enable"]
406 pub mod NDIE {
407 pub const offset: u32 = 10;
408 pub const mask: u32 = 0x01 << offset;
409 pub mod R {}
410 pub mod W {}
411 pub mod RW {
412 #[doc = "Disabled"]
413 pub const NDIE_0: u32 = 0;
414 #[doc = "Enabled"]
415 pub const NDIE_1: u32 = 0x01;
416 }
417 }
418 #[doc = "Arbitration Lost Interrupt Enable"]
419 pub mod ALIE {
420 pub const offset: u32 = 11;
421 pub const mask: u32 = 0x01 << offset;
422 pub mod R {}
423 pub mod W {}
424 pub mod RW {
425 #[doc = "Disabled"]
426 pub const ALIE_0: u32 = 0;
427 #[doc = "Enabled"]
428 pub const ALIE_1: u32 = 0x01;
429 }
430 }
431 #[doc = "FIFO Error Interrupt Enable"]
432 pub mod FEIE {
433 pub const offset: u32 = 12;
434 pub const mask: u32 = 0x01 << offset;
435 pub mod R {}
436 pub mod W {}
437 pub mod RW {
438 #[doc = "Enabled"]
439 pub const FEIE_0: u32 = 0;
440 #[doc = "Disabled"]
441 pub const FEIE_1: u32 = 0x01;
442 }
443 }
444 #[doc = "Pin Low Timeout Interrupt Enable"]
445 pub mod PLTIE {
446 pub const offset: u32 = 13;
447 pub const mask: u32 = 0x01 << offset;
448 pub mod R {}
449 pub mod W {}
450 pub mod RW {
451 #[doc = "Disabled"]
452 pub const PLTIE_0: u32 = 0;
453 #[doc = "Enabled"]
454 pub const PLTIE_1: u32 = 0x01;
455 }
456 }
457 #[doc = "Data Match Interrupt Enable"]
458 pub mod DMIE {
459 pub const offset: u32 = 14;
460 pub const mask: u32 = 0x01 << offset;
461 pub mod R {}
462 pub mod W {}
463 pub mod RW {
464 #[doc = "Disabled"]
465 pub const DMIE_0: u32 = 0;
466 #[doc = "Enabled"]
467 pub const DMIE_1: u32 = 0x01;
468 }
469 }
470}
471#[doc = "Master DMA Enable Register"]
472pub mod MDER {
473 #[doc = "Transmit Data DMA Enable"]
474 pub mod TDDE {
475 pub const offset: u32 = 0;
476 pub const mask: u32 = 0x01 << offset;
477 pub mod R {}
478 pub mod W {}
479 pub mod RW {
480 #[doc = "DMA request is disabled"]
481 pub const TDDE_0: u32 = 0;
482 #[doc = "DMA request is enabled"]
483 pub const TDDE_1: u32 = 0x01;
484 }
485 }
486 #[doc = "Receive Data DMA Enable"]
487 pub mod RDDE {
488 pub const offset: u32 = 1;
489 pub const mask: u32 = 0x01 << offset;
490 pub mod R {}
491 pub mod W {}
492 pub mod RW {
493 #[doc = "DMA request is disabled"]
494 pub const RDDE_0: u32 = 0;
495 #[doc = "DMA request is enabled"]
496 pub const RDDE_1: u32 = 0x01;
497 }
498 }
499}
500#[doc = "Master Configuration Register 0"]
501pub mod MCFGR0 {
502 #[doc = "Host Request Enable"]
503 pub mod HREN {
504 pub const offset: u32 = 0;
505 pub const mask: u32 = 0x01 << offset;
506 pub mod R {}
507 pub mod W {}
508 pub mod RW {
509 #[doc = "Host request input is disabled"]
510 pub const HREN_0: u32 = 0;
511 #[doc = "Host request input is enabled"]
512 pub const HREN_1: u32 = 0x01;
513 }
514 }
515 #[doc = "Host Request Polarity"]
516 pub mod HRPOL {
517 pub const offset: u32 = 1;
518 pub const mask: u32 = 0x01 << offset;
519 pub mod R {}
520 pub mod W {}
521 pub mod RW {
522 #[doc = "Active low"]
523 pub const HRPOL_0: u32 = 0;
524 #[doc = "Active high"]
525 pub const HRPOL_1: u32 = 0x01;
526 }
527 }
528 #[doc = "Host Request Select"]
529 pub mod HRSEL {
530 pub const offset: u32 = 2;
531 pub const mask: u32 = 0x01 << offset;
532 pub mod R {}
533 pub mod W {}
534 pub mod RW {
535 #[doc = "Host request input is pin HREQ"]
536 pub const HRSEL_0: u32 = 0;
537 #[doc = "Host request input is input trigger"]
538 pub const HRSEL_1: u32 = 0x01;
539 }
540 }
541 #[doc = "Circular FIFO Enable"]
542 pub mod CIRFIFO {
543 pub const offset: u32 = 8;
544 pub const mask: u32 = 0x01 << offset;
545 pub mod R {}
546 pub mod W {}
547 pub mod RW {
548 #[doc = "Circular FIFO is disabled"]
549 pub const CIRFIFO_0: u32 = 0;
550 #[doc = "Circular FIFO is enabled"]
551 pub const CIRFIFO_1: u32 = 0x01;
552 }
553 }
554 #[doc = "Receive Data Match Only"]
555 pub mod RDMO {
556 pub const offset: u32 = 9;
557 pub const mask: u32 = 0x01 << offset;
558 pub mod R {}
559 pub mod W {}
560 pub mod RW {
561 #[doc = "Received data is stored in the receive FIFO"]
562 pub const RDMO_0: u32 = 0;
563 #[doc = "Received data is discarded unless the the Data Match Flag (MSR\\[DMF\\]) is set"]
564 pub const RDMO_1: u32 = 0x01;
565 }
566 }
567}
568#[doc = "Master Configuration Register 1"]
569pub mod MCFGR1 {
570 #[doc = "Prescaler"]
571 pub mod PRESCALE {
572 pub const offset: u32 = 0;
573 pub const mask: u32 = 0x07 << offset;
574 pub mod R {}
575 pub mod W {}
576 pub mod RW {
577 #[doc = "Divide by 1"]
578 pub const PRESCALE_0: u32 = 0;
579 #[doc = "Divide by 2"]
580 pub const PRESCALE_1: u32 = 0x01;
581 #[doc = "Divide by 4"]
582 pub const PRESCALE_2: u32 = 0x02;
583 #[doc = "Divide by 8"]
584 pub const PRESCALE_3: u32 = 0x03;
585 #[doc = "Divide by 16"]
586 pub const PRESCALE_4: u32 = 0x04;
587 #[doc = "Divide by 32"]
588 pub const PRESCALE_5: u32 = 0x05;
589 #[doc = "Divide by 64"]
590 pub const PRESCALE_6: u32 = 0x06;
591 #[doc = "Divide by 128"]
592 pub const PRESCALE_7: u32 = 0x07;
593 }
594 }
595 #[doc = "Automatic STOP Generation"]
596 pub mod AUTOSTOP {
597 pub const offset: u32 = 8;
598 pub const mask: u32 = 0x01 << offset;
599 pub mod R {}
600 pub mod W {}
601 pub mod RW {
602 #[doc = "No effect"]
603 pub const AUTOSTOP_0: u32 = 0;
604 #[doc = "STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy"]
605 pub const AUTOSTOP_1: u32 = 0x01;
606 }
607 }
608 #[doc = "IGNACK"]
609 pub mod IGNACK {
610 pub const offset: u32 = 9;
611 pub const mask: u32 = 0x01 << offset;
612 pub mod R {}
613 pub mod W {}
614 pub mod RW {
615 #[doc = "LPI2C Master will receive ACK and NACK normally"]
616 pub const IGNACK_0: u32 = 0;
617 #[doc = "LPI2C Master will treat a received NACK as if it (NACK) was an ACK"]
618 pub const IGNACK_1: u32 = 0x01;
619 }
620 }
621 #[doc = "Timeout Configuration"]
622 pub mod TIMECFG {
623 pub const offset: u32 = 10;
624 pub const mask: u32 = 0x01 << offset;
625 pub mod R {}
626 pub mod W {}
627 pub mod RW {
628 #[doc = "Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout"]
629 pub const TIMECFG_0: u32 = 0;
630 #[doc = "Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout"]
631 pub const TIMECFG_1: u32 = 0x01;
632 }
633 }
634 #[doc = "Match Configuration"]
635 pub mod MATCFG {
636 pub const offset: u32 = 16;
637 pub const mask: u32 = 0x07 << offset;
638 pub mod R {}
639 pub mod W {}
640 pub mod RW {
641 #[doc = "Match is disabled"]
642 pub const MATCFG_0: u32 = 0;
643 #[doc = "Match is enabled (1st data word equals MATCH0 OR MATCH1)"]
644 pub const MATCFG_2: u32 = 0x02;
645 #[doc = "Match is enabled (any data word equals MATCH0 OR MATCH1)"]
646 pub const MATCFG_3: u32 = 0x03;
647 #[doc = "Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)"]
648 pub const MATCFG_4: u32 = 0x04;
649 #[doc = "Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)"]
650 pub const MATCFG_5: u32 = 0x05;
651 #[doc = "Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)"]
652 pub const MATCFG_6: u32 = 0x06;
653 #[doc = "Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)"]
654 pub const MATCFG_7: u32 = 0x07;
655 }
656 }
657 #[doc = "Pin Configuration"]
658 pub mod PINCFG {
659 pub const offset: u32 = 24;
660 pub const mask: u32 = 0x07 << offset;
661 pub mod R {}
662 pub mod W {}
663 pub mod RW {
664 #[doc = "2-pin open drain mode"]
665 pub const PINCFG_0: u32 = 0;
666 #[doc = "2-pin output only mode (ultra-fast mode)"]
667 pub const PINCFG_1: u32 = 0x01;
668 #[doc = "2-pin push-pull mode"]
669 pub const PINCFG_2: u32 = 0x02;
670 #[doc = "4-pin push-pull mode"]
671 pub const PINCFG_3: u32 = 0x03;
672 #[doc = "2-pin open drain mode with separate LPI2C slave"]
673 pub const PINCFG_4: u32 = 0x04;
674 #[doc = "2-pin output only mode (ultra-fast mode) with separate LPI2C slave"]
675 pub const PINCFG_5: u32 = 0x05;
676 #[doc = "2-pin push-pull mode with separate LPI2C slave"]
677 pub const PINCFG_6: u32 = 0x06;
678 #[doc = "4-pin push-pull mode (inverted outputs)"]
679 pub const PINCFG_7: u32 = 0x07;
680 }
681 }
682}
683#[doc = "Master Configuration Register 2"]
684pub mod MCFGR2 {
685 #[doc = "Bus Idle Timeout"]
686 pub mod BUSIDLE {
687 pub const offset: u32 = 0;
688 pub const mask: u32 = 0x0fff << offset;
689 pub mod R {}
690 pub mod W {}
691 pub mod RW {}
692 }
693 #[doc = "Glitch Filter SCL"]
694 pub mod FILTSCL {
695 pub const offset: u32 = 16;
696 pub const mask: u32 = 0x0f << offset;
697 pub mod R {}
698 pub mod W {}
699 pub mod RW {}
700 }
701 #[doc = "Glitch Filter SDA"]
702 pub mod FILTSDA {
703 pub const offset: u32 = 24;
704 pub const mask: u32 = 0x0f << offset;
705 pub mod R {}
706 pub mod W {}
707 pub mod RW {}
708 }
709}
710#[doc = "Master Configuration Register 3"]
711pub mod MCFGR3 {
712 #[doc = "Pin Low Timeout"]
713 pub mod PINLOW {
714 pub const offset: u32 = 8;
715 pub const mask: u32 = 0x0fff << offset;
716 pub mod R {}
717 pub mod W {}
718 pub mod RW {}
719 }
720}
721#[doc = "Master Data Match Register"]
722pub mod MDMR {
723 #[doc = "Match 0 Value"]
724 pub mod MATCH0 {
725 pub const offset: u32 = 0;
726 pub const mask: u32 = 0xff << offset;
727 pub mod R {}
728 pub mod W {}
729 pub mod RW {}
730 }
731 #[doc = "Match 1 Value"]
732 pub mod MATCH1 {
733 pub const offset: u32 = 16;
734 pub const mask: u32 = 0xff << offset;
735 pub mod R {}
736 pub mod W {}
737 pub mod RW {}
738 }
739}
740#[doc = "Master Clock Configuration Register 0"]
741pub mod MCCR0 {
742 #[doc = "Clock Low Period"]
743 pub mod CLKLO {
744 pub const offset: u32 = 0;
745 pub const mask: u32 = 0x3f << offset;
746 pub mod R {}
747 pub mod W {}
748 pub mod RW {}
749 }
750 #[doc = "Clock High Period"]
751 pub mod CLKHI {
752 pub const offset: u32 = 8;
753 pub const mask: u32 = 0x3f << offset;
754 pub mod R {}
755 pub mod W {}
756 pub mod RW {}
757 }
758 #[doc = "Setup Hold Delay"]
759 pub mod SETHOLD {
760 pub const offset: u32 = 16;
761 pub const mask: u32 = 0x3f << offset;
762 pub mod R {}
763 pub mod W {}
764 pub mod RW {}
765 }
766 #[doc = "Data Valid Delay"]
767 pub mod DATAVD {
768 pub const offset: u32 = 24;
769 pub const mask: u32 = 0x3f << offset;
770 pub mod R {}
771 pub mod W {}
772 pub mod RW {}
773 }
774}
775#[doc = "Master Clock Configuration Register 1"]
776pub mod MCCR1 {
777 #[doc = "Clock Low Period"]
778 pub mod CLKLO {
779 pub const offset: u32 = 0;
780 pub const mask: u32 = 0x3f << offset;
781 pub mod R {}
782 pub mod W {}
783 pub mod RW {}
784 }
785 #[doc = "Clock High Period"]
786 pub mod CLKHI {
787 pub const offset: u32 = 8;
788 pub const mask: u32 = 0x3f << offset;
789 pub mod R {}
790 pub mod W {}
791 pub mod RW {}
792 }
793 #[doc = "Setup Hold Delay"]
794 pub mod SETHOLD {
795 pub const offset: u32 = 16;
796 pub const mask: u32 = 0x3f << offset;
797 pub mod R {}
798 pub mod W {}
799 pub mod RW {}
800 }
801 #[doc = "Data Valid Delay"]
802 pub mod DATAVD {
803 pub const offset: u32 = 24;
804 pub const mask: u32 = 0x3f << offset;
805 pub mod R {}
806 pub mod W {}
807 pub mod RW {}
808 }
809}
810#[doc = "Master FIFO Control Register"]
811pub mod MFCR {
812 #[doc = "Transmit FIFO Watermark"]
813 pub mod TXWATER {
814 pub const offset: u32 = 0;
815 pub const mask: u32 = 0x03 << offset;
816 pub mod R {}
817 pub mod W {}
818 pub mod RW {}
819 }
820 #[doc = "Receive FIFO Watermark"]
821 pub mod RXWATER {
822 pub const offset: u32 = 16;
823 pub const mask: u32 = 0x03 << offset;
824 pub mod R {}
825 pub mod W {}
826 pub mod RW {}
827 }
828}
829#[doc = "Master FIFO Status Register"]
830pub mod MFSR {
831 #[doc = "Transmit FIFO Count"]
832 pub mod TXCOUNT {
833 pub const offset: u32 = 0;
834 pub const mask: u32 = 0x07 << offset;
835 pub mod R {}
836 pub mod W {}
837 pub mod RW {}
838 }
839 #[doc = "Receive FIFO Count"]
840 pub mod RXCOUNT {
841 pub const offset: u32 = 16;
842 pub const mask: u32 = 0x07 << offset;
843 pub mod R {}
844 pub mod W {}
845 pub mod RW {}
846 }
847}
848#[doc = "Master Transmit Data Register"]
849pub mod MTDR {
850 #[doc = "Transmit Data"]
851 pub mod DATA {
852 pub const offset: u32 = 0;
853 pub const mask: u32 = 0xff << offset;
854 pub mod R {}
855 pub mod W {}
856 pub mod RW {}
857 }
858 #[doc = "Command Data"]
859 pub mod CMD {
860 pub const offset: u32 = 8;
861 pub const mask: u32 = 0x07 << offset;
862 pub mod R {}
863 pub mod W {}
864 pub mod RW {
865 #[doc = "Transmit DATA\\[7:0\\]"]
866 pub const CMD_0: u32 = 0;
867 #[doc = "Receive (DATA\\[7:0\\] + 1) bytes"]
868 pub const CMD_1: u32 = 0x01;
869 #[doc = "Generate STOP condition"]
870 pub const CMD_2: u32 = 0x02;
871 #[doc = "Receive and discard (DATA\\[7:0\\] + 1) bytes"]
872 pub const CMD_3: u32 = 0x03;
873 #[doc = "Generate (repeated) START and transmit address in DATA\\[7:0\\]"]
874 pub const CMD_4: u32 = 0x04;
875 #[doc = "Generate (repeated) START and transmit address in DATA\\[7:0\\]. This transfer expects a NACK to be returned."]
876 pub const CMD_5: u32 = 0x05;
877 #[doc = "Generate (repeated) START and transmit address in DATA\\[7:0\\] using high speed mode"]
878 pub const CMD_6: u32 = 0x06;
879 #[doc = "Generate (repeated) START and transmit address in DATA\\[7:0\\] using high speed mode. This transfer expects a NACK to be returned."]
880 pub const CMD_7: u32 = 0x07;
881 }
882 }
883}
884#[doc = "Master Receive Data Register"]
885pub mod MRDR {
886 #[doc = "Receive Data"]
887 pub mod DATA {
888 pub const offset: u32 = 0;
889 pub const mask: u32 = 0xff << offset;
890 pub mod R {}
891 pub mod W {}
892 pub mod RW {}
893 }
894 #[doc = "RX Empty"]
895 pub mod RXEMPTY {
896 pub const offset: u32 = 14;
897 pub const mask: u32 = 0x01 << offset;
898 pub mod R {}
899 pub mod W {}
900 pub mod RW {
901 #[doc = "Receive FIFO is not empty"]
902 pub const RXEMPTY_0: u32 = 0;
903 #[doc = "Receive FIFO is empty"]
904 pub const RXEMPTY_1: u32 = 0x01;
905 }
906 }
907}
908#[doc = "Slave Control Register"]
909pub mod SCR {
910 #[doc = "Slave Enable"]
911 pub mod SEN {
912 pub const offset: u32 = 0;
913 pub const mask: u32 = 0x01 << offset;
914 pub mod R {}
915 pub mod W {}
916 pub mod RW {
917 #[doc = "I2C Slave mode is disabled"]
918 pub const SEN_0: u32 = 0;
919 #[doc = "I2C Slave mode is enabled"]
920 pub const SEN_1: u32 = 0x01;
921 }
922 }
923 #[doc = "Software Reset"]
924 pub mod RST {
925 pub const offset: u32 = 1;
926 pub const mask: u32 = 0x01 << offset;
927 pub mod R {}
928 pub mod W {}
929 pub mod RW {
930 #[doc = "Slave mode logic is not reset"]
931 pub const RST_0: u32 = 0;
932 #[doc = "Slave mode logic is reset"]
933 pub const RST_1: u32 = 0x01;
934 }
935 }
936 #[doc = "Filter Enable"]
937 pub mod FILTEN {
938 pub const offset: u32 = 4;
939 pub const mask: u32 = 0x01 << offset;
940 pub mod R {}
941 pub mod W {}
942 pub mod RW {
943 #[doc = "Disable digital filter and output delay counter for slave mode"]
944 pub const FILTEN_0: u32 = 0;
945 #[doc = "Enable digital filter and output delay counter for slave mode"]
946 pub const FILTEN_1: u32 = 0x01;
947 }
948 }
949 #[doc = "Filter Doze Enable"]
950 pub mod FILTDZ {
951 pub const offset: u32 = 5;
952 pub const mask: u32 = 0x01 << offset;
953 pub mod R {}
954 pub mod W {}
955 pub mod RW {
956 #[doc = "Filter remains enabled in Doze mode"]
957 pub const FILTDZ_0: u32 = 0;
958 #[doc = "Filter is disabled in Doze mode"]
959 pub const FILTDZ_1: u32 = 0x01;
960 }
961 }
962 #[doc = "Reset Transmit FIFO"]
963 pub mod RTF {
964 pub const offset: u32 = 8;
965 pub const mask: u32 = 0x01 << offset;
966 pub mod R {}
967 pub mod W {}
968 pub mod RW {
969 #[doc = "No effect"]
970 pub const RTF_0: u32 = 0;
971 #[doc = "Transmit Data Register is now empty"]
972 pub const RTF_1: u32 = 0x01;
973 }
974 }
975 #[doc = "Reset Receive FIFO"]
976 pub mod RRF {
977 pub const offset: u32 = 9;
978 pub const mask: u32 = 0x01 << offset;
979 pub mod R {}
980 pub mod W {}
981 pub mod RW {
982 #[doc = "No effect"]
983 pub const RRF_0: u32 = 0;
984 #[doc = "Receive Data Register is now empty"]
985 pub const RRF_1: u32 = 0x01;
986 }
987 }
988}
989#[doc = "Slave Status Register"]
990pub mod SSR {
991 #[doc = "Transmit Data Flag"]
992 pub mod TDF {
993 pub const offset: u32 = 0;
994 pub const mask: u32 = 0x01 << offset;
995 pub mod R {}
996 pub mod W {}
997 pub mod RW {
998 #[doc = "Transmit data not requested"]
999 pub const TDF_0: u32 = 0;
1000 #[doc = "Transmit data is requested"]
1001 pub const TDF_1: u32 = 0x01;
1002 }
1003 }
1004 #[doc = "Receive Data Flag"]
1005 pub mod RDF {
1006 pub const offset: u32 = 1;
1007 pub const mask: u32 = 0x01 << offset;
1008 pub mod R {}
1009 pub mod W {}
1010 pub mod RW {
1011 #[doc = "Receive data is not ready"]
1012 pub const RDF_0: u32 = 0;
1013 #[doc = "Receive data is ready"]
1014 pub const RDF_1: u32 = 0x01;
1015 }
1016 }
1017 #[doc = "Address Valid Flag"]
1018 pub mod AVF {
1019 pub const offset: u32 = 2;
1020 pub const mask: u32 = 0x01 << offset;
1021 pub mod R {}
1022 pub mod W {}
1023 pub mod RW {
1024 #[doc = "Address Status Register is not valid"]
1025 pub const AVF_0: u32 = 0;
1026 #[doc = "Address Status Register is valid"]
1027 pub const AVF_1: u32 = 0x01;
1028 }
1029 }
1030 #[doc = "Transmit ACK Flag"]
1031 pub mod TAF {
1032 pub const offset: u32 = 3;
1033 pub const mask: u32 = 0x01 << offset;
1034 pub mod R {}
1035 pub mod W {}
1036 pub mod RW {
1037 #[doc = "Transmit ACK/NACK is not required"]
1038 pub const TAF_0: u32 = 0;
1039 #[doc = "Transmit ACK/NACK is required"]
1040 pub const TAF_1: u32 = 0x01;
1041 }
1042 }
1043 #[doc = "Repeated Start Flag"]
1044 pub mod RSF {
1045 pub const offset: u32 = 8;
1046 pub const mask: u32 = 0x01 << offset;
1047 pub mod R {}
1048 pub mod W {}
1049 pub mod RW {
1050 #[doc = "Slave has not detected a Repeated START condition"]
1051 pub const RSF_0: u32 = 0;
1052 #[doc = "Slave has detected a Repeated START condition"]
1053 pub const RSF_1: u32 = 0x01;
1054 }
1055 }
1056 #[doc = "STOP Detect Flag"]
1057 pub mod SDF {
1058 pub const offset: u32 = 9;
1059 pub const mask: u32 = 0x01 << offset;
1060 pub mod R {}
1061 pub mod W {}
1062 pub mod RW {
1063 #[doc = "Slave has not detected a STOP condition"]
1064 pub const SDF_0: u32 = 0;
1065 #[doc = "Slave has detected a STOP condition"]
1066 pub const SDF_1: u32 = 0x01;
1067 }
1068 }
1069 #[doc = "Bit Error Flag"]
1070 pub mod BEF {
1071 pub const offset: u32 = 10;
1072 pub const mask: u32 = 0x01 << offset;
1073 pub mod R {}
1074 pub mod W {}
1075 pub mod RW {
1076 #[doc = "Slave has not detected a bit error"]
1077 pub const BEF_0: u32 = 0;
1078 #[doc = "Slave has detected a bit error"]
1079 pub const BEF_1: u32 = 0x01;
1080 }
1081 }
1082 #[doc = "FIFO Error Flag"]
1083 pub mod FEF {
1084 pub const offset: u32 = 11;
1085 pub const mask: u32 = 0x01 << offset;
1086 pub mod R {}
1087 pub mod W {}
1088 pub mod RW {
1089 #[doc = "FIFO underflow or overflow was not detected"]
1090 pub const FEF_0: u32 = 0;
1091 #[doc = "FIFO underflow or overflow was detected"]
1092 pub const FEF_1: u32 = 0x01;
1093 }
1094 }
1095 #[doc = "Address Match 0 Flag"]
1096 pub mod AM0F {
1097 pub const offset: u32 = 12;
1098 pub const mask: u32 = 0x01 << offset;
1099 pub mod R {}
1100 pub mod W {}
1101 pub mod RW {
1102 #[doc = "Have not received an ADDR0 matching address"]
1103 pub const AM0F_0: u32 = 0;
1104 #[doc = "Have received an ADDR0 matching address"]
1105 pub const AM0F_1: u32 = 0x01;
1106 }
1107 }
1108 #[doc = "Address Match 1 Flag"]
1109 pub mod AM1F {
1110 pub const offset: u32 = 13;
1111 pub const mask: u32 = 0x01 << offset;
1112 pub mod R {}
1113 pub mod W {}
1114 pub mod RW {
1115 #[doc = "Have not received an ADDR1 or ADDR0/ADDR1 range matching address"]
1116 pub const AM1F_0: u32 = 0;
1117 #[doc = "Have received an ADDR1 or ADDR0/ADDR1 range matching address"]
1118 pub const AM1F_1: u32 = 0x01;
1119 }
1120 }
1121 #[doc = "General Call Flag"]
1122 pub mod GCF {
1123 pub const offset: u32 = 14;
1124 pub const mask: u32 = 0x01 << offset;
1125 pub mod R {}
1126 pub mod W {}
1127 pub mod RW {
1128 #[doc = "Slave has not detected the General Call Address or the General Call Address is disabled"]
1129 pub const GCF_0: u32 = 0;
1130 #[doc = "Slave has detected the General Call Address"]
1131 pub const GCF_1: u32 = 0x01;
1132 }
1133 }
1134 #[doc = "SMBus Alert Response Flag"]
1135 pub mod SARF {
1136 pub const offset: u32 = 15;
1137 pub const mask: u32 = 0x01 << offset;
1138 pub mod R {}
1139 pub mod W {}
1140 pub mod RW {
1141 #[doc = "SMBus Alert Response is disabled or not detected"]
1142 pub const SARF_0: u32 = 0;
1143 #[doc = "SMBus Alert Response is enabled and detected"]
1144 pub const SARF_1: u32 = 0x01;
1145 }
1146 }
1147 #[doc = "Slave Busy Flag"]
1148 pub mod SBF {
1149 pub const offset: u32 = 24;
1150 pub const mask: u32 = 0x01 << offset;
1151 pub mod R {}
1152 pub mod W {}
1153 pub mod RW {
1154 #[doc = "I2C Slave is idle"]
1155 pub const SBF_0: u32 = 0;
1156 #[doc = "I2C Slave is busy"]
1157 pub const SBF_1: u32 = 0x01;
1158 }
1159 }
1160 #[doc = "Bus Busy Flag"]
1161 pub mod BBF {
1162 pub const offset: u32 = 25;
1163 pub const mask: u32 = 0x01 << offset;
1164 pub mod R {}
1165 pub mod W {}
1166 pub mod RW {
1167 #[doc = "I2C Bus is idle"]
1168 pub const BBF_0: u32 = 0;
1169 #[doc = "I2C Bus is busy"]
1170 pub const BBF_1: u32 = 0x01;
1171 }
1172 }
1173}
1174#[doc = "Slave Interrupt Enable Register"]
1175pub mod SIER {
1176 #[doc = "Transmit Data Interrupt Enable"]
1177 pub mod TDIE {
1178 pub const offset: u32 = 0;
1179 pub const mask: u32 = 0x01 << offset;
1180 pub mod R {}
1181 pub mod W {}
1182 pub mod RW {
1183 #[doc = "Disabled"]
1184 pub const TDIE_0: u32 = 0;
1185 #[doc = "Enabled"]
1186 pub const TDIE_1: u32 = 0x01;
1187 }
1188 }
1189 #[doc = "Receive Data Interrupt Enable"]
1190 pub mod RDIE {
1191 pub const offset: u32 = 1;
1192 pub const mask: u32 = 0x01 << offset;
1193 pub mod R {}
1194 pub mod W {}
1195 pub mod RW {
1196 #[doc = "Disabled"]
1197 pub const RDIE_0: u32 = 0;
1198 #[doc = "Enabled"]
1199 pub const RDIE_1: u32 = 0x01;
1200 }
1201 }
1202 #[doc = "Address Valid Interrupt Enable"]
1203 pub mod AVIE {
1204 pub const offset: u32 = 2;
1205 pub const mask: u32 = 0x01 << offset;
1206 pub mod R {}
1207 pub mod W {}
1208 pub mod RW {
1209 #[doc = "Disabled"]
1210 pub const AVIE_0: u32 = 0;
1211 #[doc = "Enabled"]
1212 pub const AVIE_1: u32 = 0x01;
1213 }
1214 }
1215 #[doc = "Transmit ACK Interrupt Enable"]
1216 pub mod TAIE {
1217 pub const offset: u32 = 3;
1218 pub const mask: u32 = 0x01 << offset;
1219 pub mod R {}
1220 pub mod W {}
1221 pub mod RW {
1222 #[doc = "Disabled"]
1223 pub const TAIE_0: u32 = 0;
1224 #[doc = "Enabled"]
1225 pub const TAIE_1: u32 = 0x01;
1226 }
1227 }
1228 #[doc = "Repeated Start Interrupt Enable"]
1229 pub mod RSIE {
1230 pub const offset: u32 = 8;
1231 pub const mask: u32 = 0x01 << offset;
1232 pub mod R {}
1233 pub mod W {}
1234 pub mod RW {
1235 #[doc = "Disabled"]
1236 pub const RSIE_0: u32 = 0;
1237 #[doc = "Enabled"]
1238 pub const RSIE_1: u32 = 0x01;
1239 }
1240 }
1241 #[doc = "STOP Detect Interrupt Enable"]
1242 pub mod SDIE {
1243 pub const offset: u32 = 9;
1244 pub const mask: u32 = 0x01 << offset;
1245 pub mod R {}
1246 pub mod W {}
1247 pub mod RW {
1248 #[doc = "Disabled"]
1249 pub const SDIE_0: u32 = 0;
1250 #[doc = "Enabled"]
1251 pub const SDIE_1: u32 = 0x01;
1252 }
1253 }
1254 #[doc = "Bit Error Interrupt Enable"]
1255 pub mod BEIE {
1256 pub const offset: u32 = 10;
1257 pub const mask: u32 = 0x01 << offset;
1258 pub mod R {}
1259 pub mod W {}
1260 pub mod RW {
1261 #[doc = "Disabled"]
1262 pub const BEIE_0: u32 = 0;
1263 #[doc = "Enabled"]
1264 pub const BEIE_1: u32 = 0x01;
1265 }
1266 }
1267 #[doc = "FIFO Error Interrupt Enable"]
1268 pub mod FEIE {
1269 pub const offset: u32 = 11;
1270 pub const mask: u32 = 0x01 << offset;
1271 pub mod R {}
1272 pub mod W {}
1273 pub mod RW {
1274 #[doc = "Disabled"]
1275 pub const FEIE_0: u32 = 0;
1276 #[doc = "Enabled"]
1277 pub const FEIE_1: u32 = 0x01;
1278 }
1279 }
1280 #[doc = "Address Match 0 Interrupt Enable"]
1281 pub mod AM0IE {
1282 pub const offset: u32 = 12;
1283 pub const mask: u32 = 0x01 << offset;
1284 pub mod R {}
1285 pub mod W {}
1286 pub mod RW {
1287 #[doc = "Enabled"]
1288 pub const AM0IE_0: u32 = 0;
1289 #[doc = "Disabled"]
1290 pub const AM0IE_1: u32 = 0x01;
1291 }
1292 }
1293 #[doc = "Address Match 1 Interrupt Enable"]
1294 #[deprecated(since = "0.5.1", note = "Use AM1IE")]
1295 pub mod AM1F {
1296 pub use super::AM1IE::*;
1297 }
1298 #[doc = "Address Match 1 Interrupt Enable"]
1299 pub mod AM1IE {
1300 pub const offset: u32 = 13;
1301 pub const mask: u32 = 0x01 << offset;
1302 pub mod R {}
1303 pub mod W {}
1304 pub mod RW {
1305 #[doc = "Disabled"]
1306 pub const AM1F_0: u32 = 0;
1307 #[doc = "Enabled"]
1308 pub const AM1F_1: u32 = 0x01;
1309 }
1310 }
1311 #[doc = "General Call Interrupt Enable"]
1312 pub mod GCIE {
1313 pub const offset: u32 = 14;
1314 pub const mask: u32 = 0x01 << offset;
1315 pub mod R {}
1316 pub mod W {}
1317 pub mod RW {
1318 #[doc = "Disabled"]
1319 pub const GCIE_0: u32 = 0;
1320 #[doc = "Enabled"]
1321 pub const GCIE_1: u32 = 0x01;
1322 }
1323 }
1324 #[doc = "SMBus Alert Response Interrupt Enable"]
1325 pub mod SARIE {
1326 pub const offset: u32 = 15;
1327 pub const mask: u32 = 0x01 << offset;
1328 pub mod R {}
1329 pub mod W {}
1330 pub mod RW {
1331 #[doc = "Disabled"]
1332 pub const SARIE_0: u32 = 0;
1333 #[doc = "Enabled"]
1334 pub const SARIE_1: u32 = 0x01;
1335 }
1336 }
1337}
1338#[doc = "Slave DMA Enable Register"]
1339pub mod SDER {
1340 #[doc = "Transmit Data DMA Enable"]
1341 pub mod TDDE {
1342 pub const offset: u32 = 0;
1343 pub const mask: u32 = 0x01 << offset;
1344 pub mod R {}
1345 pub mod W {}
1346 pub mod RW {
1347 #[doc = "DMA request is disabled"]
1348 pub const TDDE_0: u32 = 0;
1349 #[doc = "DMA request is enabled"]
1350 pub const TDDE_1: u32 = 0x01;
1351 }
1352 }
1353 #[doc = "Receive Data DMA Enable"]
1354 pub mod RDDE {
1355 pub const offset: u32 = 1;
1356 pub const mask: u32 = 0x01 << offset;
1357 pub mod R {}
1358 pub mod W {}
1359 pub mod RW {
1360 #[doc = "DMA request is disabled"]
1361 pub const RDDE_0: u32 = 0;
1362 #[doc = "DMA request is enabled"]
1363 pub const RDDE_1: u32 = 0x01;
1364 }
1365 }
1366 #[doc = "Address Valid DMA Enable"]
1367 pub mod AVDE {
1368 pub const offset: u32 = 2;
1369 pub const mask: u32 = 0x01 << offset;
1370 pub mod R {}
1371 pub mod W {}
1372 pub mod RW {
1373 #[doc = "DMA request is disabled"]
1374 pub const AVDE_0: u32 = 0;
1375 #[doc = "DMA request is enabled"]
1376 pub const AVDE_1: u32 = 0x01;
1377 }
1378 }
1379}
1380#[doc = "Slave Configuration Register 1"]
1381pub mod SCFGR1 {
1382 #[doc = "Address SCL Stall"]
1383 pub mod ADRSTALL {
1384 pub const offset: u32 = 0;
1385 pub const mask: u32 = 0x01 << offset;
1386 pub mod R {}
1387 pub mod W {}
1388 pub mod RW {
1389 #[doc = "Clock stretching is disabled"]
1390 pub const ADRSTALL_0: u32 = 0;
1391 #[doc = "Clock stretching is enabled"]
1392 pub const ADRSTALL_1: u32 = 0x01;
1393 }
1394 }
1395 #[doc = "RX SCL Stall"]
1396 pub mod RXSTALL {
1397 pub const offset: u32 = 1;
1398 pub const mask: u32 = 0x01 << offset;
1399 pub mod R {}
1400 pub mod W {}
1401 pub mod RW {
1402 #[doc = "Clock stretching is disabled"]
1403 pub const RXSTALL_0: u32 = 0;
1404 #[doc = "Clock stretching is enabled"]
1405 pub const RXSTALL_1: u32 = 0x01;
1406 }
1407 }
1408 #[doc = "TX Data SCL Stall"]
1409 pub mod TXDSTALL {
1410 pub const offset: u32 = 2;
1411 pub const mask: u32 = 0x01 << offset;
1412 pub mod R {}
1413 pub mod W {}
1414 pub mod RW {
1415 #[doc = "Clock stretching is disabled"]
1416 pub const TXDSTALL_0: u32 = 0;
1417 #[doc = "Clock stretching is enabled"]
1418 pub const TXDSTALL_1: u32 = 0x01;
1419 }
1420 }
1421 #[doc = "ACK SCL Stall"]
1422 pub mod ACKSTALL {
1423 pub const offset: u32 = 3;
1424 pub const mask: u32 = 0x01 << offset;
1425 pub mod R {}
1426 pub mod W {}
1427 pub mod RW {
1428 #[doc = "Clock stretching is disabled"]
1429 pub const ACKSTALL_0: u32 = 0;
1430 #[doc = "Clock stretching is enabled"]
1431 pub const ACKSTALL_1: u32 = 0x01;
1432 }
1433 }
1434 #[doc = "General Call Enable"]
1435 pub mod GCEN {
1436 pub const offset: u32 = 8;
1437 pub const mask: u32 = 0x01 << offset;
1438 pub mod R {}
1439 pub mod W {}
1440 pub mod RW {
1441 #[doc = "General Call address is disabled"]
1442 pub const GCEN_0: u32 = 0;
1443 #[doc = "General Call address is enabled"]
1444 pub const GCEN_1: u32 = 0x01;
1445 }
1446 }
1447 #[doc = "SMBus Alert Enable"]
1448 pub mod SAEN {
1449 pub const offset: u32 = 9;
1450 pub const mask: u32 = 0x01 << offset;
1451 pub mod R {}
1452 pub mod W {}
1453 pub mod RW {
1454 #[doc = "Disables match on SMBus Alert"]
1455 pub const SAEN_0: u32 = 0;
1456 #[doc = "Enables match on SMBus Alert"]
1457 pub const SAEN_1: u32 = 0x01;
1458 }
1459 }
1460 #[doc = "Transmit Flag Configuration"]
1461 pub mod TXCFG {
1462 pub const offset: u32 = 10;
1463 pub const mask: u32 = 0x01 << offset;
1464 pub mod R {}
1465 pub mod W {}
1466 pub mod RW {
1467 #[doc = "Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty"]
1468 pub const TXCFG_0: u32 = 0;
1469 #[doc = "Transmit Data Flag will assert whenever the Transmit Data register is empty"]
1470 pub const TXCFG_1: u32 = 0x01;
1471 }
1472 }
1473 #[doc = "Receive Data Configuration"]
1474 pub mod RXCFG {
1475 pub const offset: u32 = 11;
1476 pub const mask: u32 = 0x01 << offset;
1477 pub mod R {}
1478 pub mod W {}
1479 pub mod RW {
1480 #[doc = "Reading the Receive Data register will return received data and clear the Receive Data flag (MSR\\[RDF\\])."]
1481 pub const RXCFG_0: u32 = 0;
1482 #[doc = "Reading the Receive Data register when the Address Valid flag (SSR\\[AVF\\])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR\\[RDF\\])."]
1483 pub const RXCFG_1: u32 = 0x01;
1484 }
1485 }
1486 #[doc = "Ignore NACK"]
1487 pub mod IGNACK {
1488 pub const offset: u32 = 12;
1489 pub const mask: u32 = 0x01 << offset;
1490 pub mod R {}
1491 pub mod W {}
1492 pub mod RW {
1493 #[doc = "Slave will end transfer when NACK is detected"]
1494 pub const IGNACK_0: u32 = 0;
1495 #[doc = "Slave will not end transfer when NACK detected"]
1496 pub const IGNACK_1: u32 = 0x01;
1497 }
1498 }
1499 #[doc = "High Speed Mode Enable"]
1500 pub mod HSMEN {
1501 pub const offset: u32 = 13;
1502 pub const mask: u32 = 0x01 << offset;
1503 pub mod R {}
1504 pub mod W {}
1505 pub mod RW {
1506 #[doc = "Disables detection of HS-mode master code"]
1507 pub const HSMEN_0: u32 = 0;
1508 #[doc = "Enables detection of HS-mode master code"]
1509 pub const HSMEN_1: u32 = 0x01;
1510 }
1511 }
1512 #[doc = "Address Configuration"]
1513 pub mod ADDRCFG {
1514 pub const offset: u32 = 16;
1515 pub const mask: u32 = 0x07 << offset;
1516 pub mod R {}
1517 pub mod W {}
1518 pub mod RW {
1519 #[doc = "Address match 0 (7-bit)"]
1520 pub const ADDRCFG_0: u32 = 0;
1521 #[doc = "Address match 0 (10-bit)"]
1522 pub const ADDRCFG_1: u32 = 0x01;
1523 #[doc = "Address match 0 (7-bit) or Address match 1 (7-bit)"]
1524 pub const ADDRCFG_2: u32 = 0x02;
1525 #[doc = "Address match 0 (10-bit) or Address match 1 (10-bit)"]
1526 pub const ADDRCFG_3: u32 = 0x03;
1527 #[doc = "Address match 0 (7-bit) or Address match 1 (10-bit)"]
1528 pub const ADDRCFG_4: u32 = 0x04;
1529 #[doc = "Address match 0 (10-bit) or Address match 1 (7-bit)"]
1530 pub const ADDRCFG_5: u32 = 0x05;
1531 #[doc = "From Address match 0 (7-bit) to Address match 1 (7-bit)"]
1532 pub const ADDRCFG_6: u32 = 0x06;
1533 #[doc = "From Address match 0 (10-bit) to Address match 1 (10-bit)"]
1534 pub const ADDRCFG_7: u32 = 0x07;
1535 }
1536 }
1537}
1538#[doc = "Slave Configuration Register 2"]
1539pub mod SCFGR2 {
1540 #[doc = "Clock Hold Time"]
1541 pub mod CLKHOLD {
1542 pub const offset: u32 = 0;
1543 pub const mask: u32 = 0x0f << offset;
1544 pub mod R {}
1545 pub mod W {}
1546 pub mod RW {}
1547 }
1548 #[doc = "Data Valid Delay"]
1549 pub mod DATAVD {
1550 pub const offset: u32 = 8;
1551 pub const mask: u32 = 0x3f << offset;
1552 pub mod R {}
1553 pub mod W {}
1554 pub mod RW {}
1555 }
1556 #[doc = "Glitch Filter SCL"]
1557 pub mod FILTSCL {
1558 pub const offset: u32 = 16;
1559 pub const mask: u32 = 0x0f << offset;
1560 pub mod R {}
1561 pub mod W {}
1562 pub mod RW {}
1563 }
1564 #[doc = "Glitch Filter SDA"]
1565 pub mod FILTSDA {
1566 pub const offset: u32 = 24;
1567 pub const mask: u32 = 0x0f << offset;
1568 pub mod R {}
1569 pub mod W {}
1570 pub mod RW {}
1571 }
1572}
1573#[doc = "Slave Address Match Register"]
1574pub mod SAMR {
1575 #[doc = "Address 0 Value"]
1576 pub mod ADDR0 {
1577 pub const offset: u32 = 1;
1578 pub const mask: u32 = 0x03ff << offset;
1579 pub mod R {}
1580 pub mod W {}
1581 pub mod RW {}
1582 }
1583 #[doc = "Address 1 Value"]
1584 pub mod ADDR1 {
1585 pub const offset: u32 = 17;
1586 pub const mask: u32 = 0x03ff << offset;
1587 pub mod R {}
1588 pub mod W {}
1589 pub mod RW {}
1590 }
1591}
1592#[doc = "Slave Address Status Register"]
1593pub mod SASR {
1594 #[doc = "Received Address"]
1595 pub mod RADDR {
1596 pub const offset: u32 = 0;
1597 pub const mask: u32 = 0x07ff << offset;
1598 pub mod R {}
1599 pub mod W {}
1600 pub mod RW {}
1601 }
1602 #[doc = "Address Not Valid"]
1603 pub mod ANV {
1604 pub const offset: u32 = 14;
1605 pub const mask: u32 = 0x01 << offset;
1606 pub mod R {}
1607 pub mod W {}
1608 pub mod RW {
1609 #[doc = "Received Address (RADDR) is valid"]
1610 pub const ANV_0: u32 = 0;
1611 #[doc = "Received Address (RADDR) is not valid"]
1612 pub const ANV_1: u32 = 0x01;
1613 }
1614 }
1615}
1616#[doc = "Slave Transmit ACK Register"]
1617pub mod STAR {
1618 #[doc = "Transmit NACK"]
1619 pub mod TXNACK {
1620 pub const offset: u32 = 0;
1621 pub const mask: u32 = 0x01 << offset;
1622 pub mod R {}
1623 pub mod W {}
1624 pub mod RW {
1625 #[doc = "Write a Transmit ACK for each received word"]
1626 pub const TXNACK_0: u32 = 0;
1627 #[doc = "Write a Transmit NACK for each received word"]
1628 pub const TXNACK_1: u32 = 0x01;
1629 }
1630 }
1631}
1632#[doc = "Slave Transmit Data Register"]
1633pub mod STDR {
1634 #[doc = "Transmit Data"]
1635 pub mod DATA {
1636 pub const offset: u32 = 0;
1637 pub const mask: u32 = 0xff << offset;
1638 pub mod R {}
1639 pub mod W {}
1640 pub mod RW {}
1641 }
1642}
1643#[doc = "Slave Receive Data Register"]
1644pub mod SRDR {
1645 #[doc = "Receive Data"]
1646 pub mod DATA {
1647 pub const offset: u32 = 0;
1648 pub const mask: u32 = 0xff << offset;
1649 pub mod R {}
1650 pub mod W {}
1651 pub mod RW {}
1652 }
1653 #[doc = "RX Empty"]
1654 pub mod RXEMPTY {
1655 pub const offset: u32 = 14;
1656 pub const mask: u32 = 0x01 << offset;
1657 pub mod R {}
1658 pub mod W {}
1659 pub mod RW {
1660 #[doc = "The Receive Data Register is not empty"]
1661 pub const RXEMPTY_0: u32 = 0;
1662 #[doc = "The Receive Data Register is empty"]
1663 pub const RXEMPTY_1: u32 = 0x01;
1664 }
1665 }
1666 #[doc = "Start Of Frame"]
1667 pub mod SOF {
1668 pub const offset: u32 = 15;
1669 pub const mask: u32 = 0x01 << offset;
1670 pub mod R {}
1671 pub mod W {}
1672 pub mod RW {
1673 #[doc = "Indicates this is not the first data word since a (repeated) START or STOP condition"]
1674 pub const SOF_0: u32 = 0;
1675 #[doc = "Indicates this is the first data word since a (repeated) START or STOP condition"]
1676 pub const SOF_1: u32 = 0x01;
1677 }
1678 }
1679}