rp2040_pac/clocks/
enabled0.rs

Help
1#[doc = "Register `ENABLED0` reader"]
2pub type R = crate::R<ENABLED0_SPEC>;
3#[doc = "Field `clk_sys_clocks` reader - "]
4pub type CLK_SYS_CLOCKS_R = crate::BitReader;
5#[doc = "Field `clk_adc_adc` reader - "]
6pub type CLK_ADC_ADC_R = crate::BitReader;
7#[doc = "Field `clk_sys_adc` reader - "]
8pub type CLK_SYS_ADC_R = crate::BitReader;
9#[doc = "Field `clk_sys_busctrl` reader - "]
10pub type CLK_SYS_BUSCTRL_R = crate::BitReader;
11#[doc = "Field `clk_sys_busfabric` reader - "]
12pub type CLK_SYS_BUSFABRIC_R = crate::BitReader;
13#[doc = "Field `clk_sys_dma` reader - "]
14pub type CLK_SYS_DMA_R = crate::BitReader;
15#[doc = "Field `clk_sys_i2c0` reader - "]
16pub type CLK_SYS_I2C0_R = crate::BitReader;
17#[doc = "Field `clk_sys_i2c1` reader - "]
18pub type CLK_SYS_I2C1_R = crate::BitReader;
19#[doc = "Field `clk_sys_io` reader - "]
20pub type CLK_SYS_IO_R = crate::BitReader;
21#[doc = "Field `clk_sys_jtag` reader - "]
22pub type CLK_SYS_JTAG_R = crate::BitReader;
23#[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "]
24pub type CLK_SYS_VREG_AND_CHIP_RESET_R = crate::BitReader;
25#[doc = "Field `clk_sys_pads` reader - "]
26pub type CLK_SYS_PADS_R = crate::BitReader;
27#[doc = "Field `clk_sys_pio0` reader - "]
28pub type CLK_SYS_PIO0_R = crate::BitReader;
29#[doc = "Field `clk_sys_pio1` reader - "]
30pub type CLK_SYS_PIO1_R = crate::BitReader;
31#[doc = "Field `clk_sys_pll_sys` reader - "]
32pub type CLK_SYS_PLL_SYS_R = crate::BitReader;
33#[doc = "Field `clk_sys_pll_usb` reader - "]
34pub type CLK_SYS_PLL_USB_R = crate::BitReader;
35#[doc = "Field `clk_sys_psm` reader - "]
36pub type CLK_SYS_PSM_R = crate::BitReader;
37#[doc = "Field `clk_sys_pwm` reader - "]
38pub type CLK_SYS_PWM_R = crate::BitReader;
39#[doc = "Field `clk_sys_resets` reader - "]
40pub type CLK_SYS_RESETS_R = crate::BitReader;
41#[doc = "Field `clk_sys_rom` reader - "]
42pub type CLK_SYS_ROM_R = crate::BitReader;
43#[doc = "Field `clk_sys_rosc` reader - "]
44pub type CLK_SYS_ROSC_R = crate::BitReader;
45#[doc = "Field `clk_rtc_rtc` reader - "]
46pub type CLK_RTC_RTC_R = crate::BitReader;
47#[doc = "Field `clk_sys_rtc` reader - "]
48pub type CLK_SYS_RTC_R = crate::BitReader;
49#[doc = "Field `clk_sys_sio` reader - "]
50pub type CLK_SYS_SIO_R = crate::BitReader;
51#[doc = "Field `clk_peri_spi0` reader - "]
52pub type CLK_PERI_SPI0_R = crate::BitReader;
53#[doc = "Field `clk_sys_spi0` reader - "]
54pub type CLK_SYS_SPI0_R = crate::BitReader;
55#[doc = "Field `clk_peri_spi1` reader - "]
56pub type CLK_PERI_SPI1_R = crate::BitReader;
57#[doc = "Field `clk_sys_spi1` reader - "]
58pub type CLK_SYS_SPI1_R = crate::BitReader;
59#[doc = "Field `clk_sys_sram0` reader - "]
60pub type CLK_SYS_SRAM0_R = crate::BitReader;
61#[doc = "Field `clk_sys_sram1` reader - "]
62pub type CLK_SYS_SRAM1_R = crate::BitReader;
63#[doc = "Field `clk_sys_sram2` reader - "]
64pub type CLK_SYS_SRAM2_R = crate::BitReader;
65#[doc = "Field `clk_sys_sram3` reader - "]
66pub type CLK_SYS_SRAM3_R = crate::BitReader;
67impl R {
68    #[doc = "Bit 0"]
69    #[inline(always)]
70    pub fn clk_sys_clocks(&self) -> CLK_SYS_CLOCKS_R {
71        CLK_SYS_CLOCKS_R::new((self.bits & 1) != 0)
72    }
73    #[doc = "Bit 1"]
74    #[inline(always)]
75    pub fn clk_adc_adc(&self) -> CLK_ADC_ADC_R {
76        CLK_ADC_ADC_R::new(((self.bits >> 1) & 1) != 0)
77    }
78    #[doc = "Bit 2"]
79    #[inline(always)]
80    pub fn clk_sys_adc(&self) -> CLK_SYS_ADC_R {
81        CLK_SYS_ADC_R::new(((self.bits >> 2) & 1) != 0)
82    }
83    #[doc = "Bit 3"]
84    #[inline(always)]
85    pub fn clk_sys_busctrl(&self) -> CLK_SYS_BUSCTRL_R {
86        CLK_SYS_BUSCTRL_R::new(((self.bits >> 3) & 1) != 0)
87    }
88    #[doc = "Bit 4"]
89    #[inline(always)]
90    pub fn clk_sys_busfabric(&self) -> CLK_SYS_BUSFABRIC_R {
91        CLK_SYS_BUSFABRIC_R::new(((self.bits >> 4) & 1) != 0)
92    }
93    #[doc = "Bit 5"]
94    #[inline(always)]
95    pub fn clk_sys_dma(&self) -> CLK_SYS_DMA_R {
96        CLK_SYS_DMA_R::new(((self.bits >> 5) & 1) != 0)
97    }
98    #[doc = "Bit 6"]
99    #[inline(always)]
100    pub fn clk_sys_i2c0(&self) -> CLK_SYS_I2C0_R {
101        CLK_SYS_I2C0_R::new(((self.bits >> 6) & 1) != 0)
102    }
103    #[doc = "Bit 7"]
104    #[inline(always)]
105    pub fn clk_sys_i2c1(&self) -> CLK_SYS_I2C1_R {
106        CLK_SYS_I2C1_R::new(((self.bits >> 7) & 1) != 0)
107    }
108    #[doc = "Bit 8"]
109    #[inline(always)]
110    pub fn clk_sys_io(&self) -> CLK_SYS_IO_R {
111        CLK_SYS_IO_R::new(((self.bits >> 8) & 1) != 0)
112    }
113    #[doc = "Bit 9"]
114    #[inline(always)]
115    pub fn clk_sys_jtag(&self) -> CLK_SYS_JTAG_R {
116        CLK_SYS_JTAG_R::new(((self.bits >> 9) & 1) != 0)
117    }
118    #[doc = "Bit 10"]
119    #[inline(always)]
120    pub fn clk_sys_vreg_and_chip_reset(&self) -> CLK_SYS_VREG_AND_CHIP_RESET_R {
121        CLK_SYS_VREG_AND_CHIP_RESET_R::new(((self.bits >> 10) & 1) != 0)
122    }
123    #[doc = "Bit 11"]
124    #[inline(always)]
125    pub fn clk_sys_pads(&self) -> CLK_SYS_PADS_R {
126        CLK_SYS_PADS_R::new(((self.bits >> 11) & 1) != 0)
127    }
128    #[doc = "Bit 12"]
129    #[inline(always)]
130    pub fn clk_sys_pio0(&self) -> CLK_SYS_PIO0_R {
131        CLK_SYS_PIO0_R::new(((self.bits >> 12) & 1) != 0)
132    }
133    #[doc = "Bit 13"]
134    #[inline(always)]
135    pub fn clk_sys_pio1(&self) -> CLK_SYS_PIO1_R {
136        CLK_SYS_PIO1_R::new(((self.bits >> 13) & 1) != 0)
137    }
138    #[doc = "Bit 14"]
139    #[inline(always)]
140    pub fn clk_sys_pll_sys(&self) -> CLK_SYS_PLL_SYS_R {
141        CLK_SYS_PLL_SYS_R::new(((self.bits >> 14) & 1) != 0)
142    }
143    #[doc = "Bit 15"]
144    #[inline(always)]
145    pub fn clk_sys_pll_usb(&self) -> CLK_SYS_PLL_USB_R {
146        CLK_SYS_PLL_USB_R::new(((self.bits >> 15) & 1) != 0)
147    }
148    #[doc = "Bit 16"]
149    #[inline(always)]
150    pub fn clk_sys_psm(&self) -> CLK_SYS_PSM_R {
151        CLK_SYS_PSM_R::new(((self.bits >> 16) & 1) != 0)
152    }
153    #[doc = "Bit 17"]
154    #[inline(always)]
155    pub fn clk_sys_pwm(&self) -> CLK_SYS_PWM_R {
156        CLK_SYS_PWM_R::new(((self.bits >> 17) & 1) != 0)
157    }
158    #[doc = "Bit 18"]
159    #[inline(always)]
160    pub fn clk_sys_resets(&self) -> CLK_SYS_RESETS_R {
161        CLK_SYS_RESETS_R::new(((self.bits >> 18) & 1) != 0)
162    }
163    #[doc = "Bit 19"]
164    #[inline(always)]
165    pub fn clk_sys_rom(&self) -> CLK_SYS_ROM_R {
166        CLK_SYS_ROM_R::new(((self.bits >> 19) & 1) != 0)
167    }
168    #[doc = "Bit 20"]
169    #[inline(always)]
170    pub fn clk_sys_rosc(&self) -> CLK_SYS_ROSC_R {
171        CLK_SYS_ROSC_R::new(((self.bits >> 20) & 1) != 0)
172    }
173    #[doc = "Bit 21"]
174    #[inline(always)]
175    pub fn clk_rtc_rtc(&self) -> CLK_RTC_RTC_R {
176        CLK_RTC_RTC_R::new(((self.bits >> 21) & 1) != 0)
177    }
178    #[doc = "Bit 22"]
179    #[inline(always)]
180    pub fn clk_sys_rtc(&self) -> CLK_SYS_RTC_R {
181        CLK_SYS_RTC_R::new(((self.bits >> 22) & 1) != 0)
182    }
183    #[doc = "Bit 23"]
184    #[inline(always)]
185    pub fn clk_sys_sio(&self) -> CLK_SYS_SIO_R {
186        CLK_SYS_SIO_R::new(((self.bits >> 23) & 1) != 0)
187    }
188    #[doc = "Bit 24"]
189    #[inline(always)]
190    pub fn clk_peri_spi0(&self) -> CLK_PERI_SPI0_R {
191        CLK_PERI_SPI0_R::new(((self.bits >> 24) & 1) != 0)
192    }
193    #[doc = "Bit 25"]
194    #[inline(always)]
195    pub fn clk_sys_spi0(&self) -> CLK_SYS_SPI0_R {
196        CLK_SYS_SPI0_R::new(((self.bits >> 25) & 1) != 0)
197    }
198    #[doc = "Bit 26"]
199    #[inline(always)]
200    pub fn clk_peri_spi1(&self) -> CLK_PERI_SPI1_R {
201        CLK_PERI_SPI1_R::new(((self.bits >> 26) & 1) != 0)
202    }
203    #[doc = "Bit 27"]
204    #[inline(always)]
205    pub fn clk_sys_spi1(&self) -> CLK_SYS_SPI1_R {
206        CLK_SYS_SPI1_R::new(((self.bits >> 27) & 1) != 0)
207    }
208    #[doc = "Bit 28"]
209    #[inline(always)]
210    pub fn clk_sys_sram0(&self) -> CLK_SYS_SRAM0_R {
211        CLK_SYS_SRAM0_R::new(((self.bits >> 28) & 1) != 0)
212    }
213    #[doc = "Bit 29"]
214    #[inline(always)]
215    pub fn clk_sys_sram1(&self) -> CLK_SYS_SRAM1_R {
216        CLK_SYS_SRAM1_R::new(((self.bits >> 29) & 1) != 0)
217    }
218    #[doc = "Bit 30"]
219    #[inline(always)]
220    pub fn clk_sys_sram2(&self) -> CLK_SYS_SRAM2_R {
221        CLK_SYS_SRAM2_R::new(((self.bits >> 30) & 1) != 0)
222    }
223    #[doc = "Bit 31"]
224    #[inline(always)]
225    pub fn clk_sys_sram3(&self) -> CLK_SYS_SRAM3_R {
226        CLK_SYS_SRAM3_R::new(((self.bits >> 31) & 1) != 0)
227    }
228}
229#[doc = "indicates the state of the clock enable  
230
231You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
232pub struct ENABLED0_SPEC;
233impl crate::RegisterSpec for ENABLED0_SPEC {
234    type Ux = u32;
235}
236#[doc = "`read()` method returns [`enabled0::R`](R) reader structure"]
237impl crate::Readable for ENABLED0_SPEC {}
238#[doc = "`reset()` method sets ENABLED0 to value 0"]
239impl crate::Resettable for ENABLED0_SPEC {
240    const RESET_VALUE: u32 = 0;
241}
rp2040_pac/clocks/enabled0.rs

rp2040_pac/clocks/
enabled0.rs
