nrf52840_pac/clock/
traceconfig.rs

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1#[doc = "Register `TRACECONFIG` reader"]
2pub struct R(crate::R<TRACECONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TRACECONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TRACECONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TRACECONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TRACECONFIG` writer"]
17pub struct W(crate::W<TRACECONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TRACECONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TRACECONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TRACECONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TRACEPORTSPEED` reader - Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two."]
38pub type TRACEPORTSPEED_R = crate::FieldReader<u8, TRACEPORTSPEED_A>;
39#[doc = "Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41#[repr(u8)]
42pub enum TRACEPORTSPEED_A {
43    #[doc = "0: 32 MHz trace port clock (TRACECLK = 16 MHz)"]
44    _32MHZ = 0,
45    #[doc = "1: 16 MHz trace port clock (TRACECLK = 8 MHz)"]
46    _16MHZ = 1,
47    #[doc = "2: 8 MHz trace port clock (TRACECLK = 4 MHz)"]
48    _8MHZ = 2,
49    #[doc = "3: 4 MHz trace port clock (TRACECLK = 2 MHz)"]
50    _4MHZ = 3,
51}
52impl From<TRACEPORTSPEED_A> for u8 {
53    #[inline(always)]
54    fn from(variant: TRACEPORTSPEED_A) -> Self {
55        variant as _
56    }
57}
58impl TRACEPORTSPEED_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> TRACEPORTSPEED_A {
62        match self.bits {
63            0 => TRACEPORTSPEED_A::_32MHZ,
64            1 => TRACEPORTSPEED_A::_16MHZ,
65            2 => TRACEPORTSPEED_A::_8MHZ,
66            3 => TRACEPORTSPEED_A::_4MHZ,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `_32MHZ`"]
71    #[inline(always)]
72    pub fn is_32mhz(&self) -> bool {
73        *self == TRACEPORTSPEED_A::_32MHZ
74    }
75    #[doc = "Checks if the value of the field is `_16MHZ`"]
76    #[inline(always)]
77    pub fn is_16mhz(&self) -> bool {
78        *self == TRACEPORTSPEED_A::_16MHZ
79    }
80    #[doc = "Checks if the value of the field is `_8MHZ`"]
81    #[inline(always)]
82    pub fn is_8mhz(&self) -> bool {
83        *self == TRACEPORTSPEED_A::_8MHZ
84    }
85    #[doc = "Checks if the value of the field is `_4MHZ`"]
86    #[inline(always)]
87    pub fn is_4mhz(&self) -> bool {
88        *self == TRACEPORTSPEED_A::_4MHZ
89    }
90}
91#[doc = "Field `TRACEPORTSPEED` writer - Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two."]
92pub type TRACEPORTSPEED_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u32, TRACECONFIG_SPEC, u8, TRACEPORTSPEED_A, 2, O>;
94impl<'a, const O: u8> TRACEPORTSPEED_W<'a, O> {
95    #[doc = "32 MHz trace port clock (TRACECLK = 16 MHz)"]
96    #[inline(always)]
97    pub fn _32mhz(self) -> &'a mut W {
98        self.variant(TRACEPORTSPEED_A::_32MHZ)
99    }
100    #[doc = "16 MHz trace port clock (TRACECLK = 8 MHz)"]
101    #[inline(always)]
102    pub fn _16mhz(self) -> &'a mut W {
103        self.variant(TRACEPORTSPEED_A::_16MHZ)
104    }
105    #[doc = "8 MHz trace port clock (TRACECLK = 4 MHz)"]
106    #[inline(always)]
107    pub fn _8mhz(self) -> &'a mut W {
108        self.variant(TRACEPORTSPEED_A::_8MHZ)
109    }
110    #[doc = "4 MHz trace port clock (TRACECLK = 2 MHz)"]
111    #[inline(always)]
112    pub fn _4mhz(self) -> &'a mut W {
113        self.variant(TRACEPORTSPEED_A::_4MHZ)
114    }
115}
116#[doc = "Field `TRACEMUX` reader - Pin multiplexing of trace signals. See pin assignment chapter for more details."]
117pub type TRACEMUX_R = crate::FieldReader<u8, TRACEMUX_A>;
118#[doc = "Pin multiplexing of trace signals. See pin assignment chapter for more details.\n\nValue on reset: 0"]
119#[derive(Clone, Copy, Debug, PartialEq)]
120#[repr(u8)]
121pub enum TRACEMUX_A {
122    #[doc = "0: No trace signals routed to pins. All pins can be used as regular GPIOs."]
123    GPIO = 0,
124    #[doc = "1: SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs."]
125    SERIAL = 1,
126    #[doc = "2: All trace signals (TRACECLK and TRACEDATA\\[n\\]) routed to pins."]
127    PARALLEL = 2,
128}
129impl From<TRACEMUX_A> for u8 {
130    #[inline(always)]
131    fn from(variant: TRACEMUX_A) -> Self {
132        variant as _
133    }
134}
135impl TRACEMUX_R {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub fn variant(&self) -> Option<TRACEMUX_A> {
139        match self.bits {
140            0 => Some(TRACEMUX_A::GPIO),
141            1 => Some(TRACEMUX_A::SERIAL),
142            2 => Some(TRACEMUX_A::PARALLEL),
143            _ => None,
144        }
145    }
146    #[doc = "Checks if the value of the field is `GPIO`"]
147    #[inline(always)]
148    pub fn is_gpio(&self) -> bool {
149        *self == TRACEMUX_A::GPIO
150    }
151    #[doc = "Checks if the value of the field is `SERIAL`"]
152    #[inline(always)]
153    pub fn is_serial(&self) -> bool {
154        *self == TRACEMUX_A::SERIAL
155    }
156    #[doc = "Checks if the value of the field is `PARALLEL`"]
157    #[inline(always)]
158    pub fn is_parallel(&self) -> bool {
159        *self == TRACEMUX_A::PARALLEL
160    }
161}
162#[doc = "Field `TRACEMUX` writer - Pin multiplexing of trace signals. See pin assignment chapter for more details."]
163pub type TRACEMUX_W<'a, const O: u8> =
164    crate::FieldWriter<'a, u32, TRACECONFIG_SPEC, u8, TRACEMUX_A, 2, O>;
165impl<'a, const O: u8> TRACEMUX_W<'a, O> {
166    #[doc = "No trace signals routed to pins. All pins can be used as regular GPIOs."]
167    #[inline(always)]
168    pub fn gpio(self) -> &'a mut W {
169        self.variant(TRACEMUX_A::GPIO)
170    }
171    #[doc = "SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs."]
172    #[inline(always)]
173    pub fn serial(self) -> &'a mut W {
174        self.variant(TRACEMUX_A::SERIAL)
175    }
176    #[doc = "All trace signals (TRACECLK and TRACEDATA\\[n\\]) routed to pins."]
177    #[inline(always)]
178    pub fn parallel(self) -> &'a mut W {
179        self.variant(TRACEMUX_A::PARALLEL)
180    }
181}
182impl R {
183    #[doc = "Bits 0:1 - Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two."]
184    #[inline(always)]
185    pub fn traceportspeed(&self) -> TRACEPORTSPEED_R {
186        TRACEPORTSPEED_R::new((self.bits & 3) as u8)
187    }
188    #[doc = "Bits 16:17 - Pin multiplexing of trace signals. See pin assignment chapter for more details."]
189    #[inline(always)]
190    pub fn tracemux(&self) -> TRACEMUX_R {
191        TRACEMUX_R::new(((self.bits >> 16) & 3) as u8)
192    }
193}
194impl W {
195    #[doc = "Bits 0:1 - Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two."]
196    #[inline(always)]
197    pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<0> {
198        TRACEPORTSPEED_W::new(self)
199    }
200    #[doc = "Bits 16:17 - Pin multiplexing of trace signals. See pin assignment chapter for more details."]
201    #[inline(always)]
202    pub fn tracemux(&mut self) -> TRACEMUX_W<16> {
203        TRACEMUX_W::new(self)
204    }
205    #[doc = "Writes raw bits to the register."]
206    #[inline(always)]
207    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
208        self.0.bits(bits);
209        self
210    }
211}
212#[doc = "Clocking options for the trace port debug interface\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [traceconfig](index.html) module"]
213pub struct TRACECONFIG_SPEC;
214impl crate::RegisterSpec for TRACECONFIG_SPEC {
215    type Ux = u32;
216}
217#[doc = "`read()` method returns [traceconfig::R](R) reader structure"]
218impl crate::Readable for TRACECONFIG_SPEC {
219    type Reader = R;
220}
221#[doc = "`write(|w| ..)` method takes [traceconfig::W](W) writer structure"]
222impl crate::Writable for TRACECONFIG_SPEC {
223    type Writer = W;
224}
225#[doc = "`reset()` method sets TRACECONFIG to value 0"]
226impl crate::Resettable for TRACECONFIG_SPEC {
227    #[inline(always)]
228    fn reset_value() -> Self::Ux {
229        0
230    }
231}
nrf52840_pac/clock/traceconfig.rs

nrf52840_pac/clock/
traceconfig.rs
