rp2040_pac/sio/
interp0_ctrl_lane1.rs

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1#[doc = "Register `INTERP0_CTRL_LANE1` reader"]
2pub type R = crate::R<INTERP0_CTRL_LANE1_SPEC>;
3#[doc = "Register `INTERP0_CTRL_LANE1` writer"]
4pub type W = crate::W<INTERP0_CTRL_LANE1_SPEC>;
5#[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"]
6pub type SHIFT_R = crate::FieldReader;
7#[doc = "Field `SHIFT` writer - Logical right-shift applied to accumulator before masking"]
8pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"]
10pub type MASK_LSB_R = crate::FieldReader;
11#[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"]
12pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive)  
14 Setting MSB &lt; LSB may cause chip to turn inside-out"]
15pub type MASK_MSB_R = crate::FieldReader;
16#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive)  
17 Setting MSB &lt; LSB may cause chip to turn inside-out"]
18pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
19#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
20 before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
21pub type SIGNED_R = crate::BitReader;
22#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
23 before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
24pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
26 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
27pub type CROSS_INPUT_R = crate::BitReader;
28#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
29 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
30pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
32pub type CROSS_RESULT_R = crate::BitReader;
33#[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
34pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
36pub type ADD_RAW_R = crate::BitReader;
37#[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
38pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
40 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
41 of pointers into flash or SRAM."]
42pub type FORCE_MSB_R = crate::FieldReader;
43#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
44 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
45 of pointers into flash or SRAM."]
46pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
47impl R {
48    #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"]
49    #[inline(always)]
50    pub fn shift(&self) -> SHIFT_R {
51        SHIFT_R::new((self.bits & 0x1f) as u8)
52    }
53    #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
54    #[inline(always)]
55    pub fn mask_lsb(&self) -> MASK_LSB_R {
56        MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8)
57    }
58    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)  
59 Setting MSB &lt; LSB may cause chip to turn inside-out"]
60    #[inline(always)]
61    pub fn mask_msb(&self) -> MASK_MSB_R {
62        MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8)
63    }
64    #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
65 before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
66    #[inline(always)]
67    pub fn signed(&self) -> SIGNED_R {
68        SIGNED_R::new(((self.bits >> 15) & 1) != 0)
69    }
70    #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
71 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
72    #[inline(always)]
73    pub fn cross_input(&self) -> CROSS_INPUT_R {
74        CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0)
75    }
76    #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
77    #[inline(always)]
78    pub fn cross_result(&self) -> CROSS_RESULT_R {
79        CROSS_RESULT_R::new(((self.bits >> 17) & 1) != 0)
80    }
81    #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
82    #[inline(always)]
83    pub fn add_raw(&self) -> ADD_RAW_R {
84        ADD_RAW_R::new(((self.bits >> 18) & 1) != 0)
85    }
86    #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
87 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
88 of pointers into flash or SRAM."]
89    #[inline(always)]
90    pub fn force_msb(&self) -> FORCE_MSB_R {
91        FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8)
92    }
93}
94impl W {
95    #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"]
96    #[inline(always)]
97    #[must_use]
98    pub fn shift(&mut self) -> SHIFT_W<INTERP0_CTRL_LANE1_SPEC> {
99        SHIFT_W::new(self, 0)
100    }
101    #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
102    #[inline(always)]
103    #[must_use]
104    pub fn mask_lsb(&mut self) -> MASK_LSB_W<INTERP0_CTRL_LANE1_SPEC> {
105        MASK_LSB_W::new(self, 5)
106    }
107    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)  
108 Setting MSB &lt; LSB may cause chip to turn inside-out"]
109    #[inline(always)]
110    #[must_use]
111    pub fn mask_msb(&mut self) -> MASK_MSB_W<INTERP0_CTRL_LANE1_SPEC> {
112        MASK_MSB_W::new(self, 10)
113    }
114    #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
115 before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
116    #[inline(always)]
117    #[must_use]
118    pub fn signed(&mut self) -> SIGNED_W<INTERP0_CTRL_LANE1_SPEC> {
119        SIGNED_W::new(self, 15)
120    }
121    #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
122 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
123    #[inline(always)]
124    #[must_use]
125    pub fn cross_input(&mut self) -> CROSS_INPUT_W<INTERP0_CTRL_LANE1_SPEC> {
126        CROSS_INPUT_W::new(self, 16)
127    }
128    #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
129    #[inline(always)]
130    #[must_use]
131    pub fn cross_result(&mut self) -> CROSS_RESULT_W<INTERP0_CTRL_LANE1_SPEC> {
132        CROSS_RESULT_W::new(self, 17)
133    }
134    #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
135    #[inline(always)]
136    #[must_use]
137    pub fn add_raw(&mut self) -> ADD_RAW_W<INTERP0_CTRL_LANE1_SPEC> {
138        ADD_RAW_W::new(self, 18)
139    }
140    #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
141 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
142 of pointers into flash or SRAM."]
143    #[inline(always)]
144    #[must_use]
145    pub fn force_msb(&mut self) -> FORCE_MSB_W<INTERP0_CTRL_LANE1_SPEC> {
146        FORCE_MSB_W::new(self, 19)
147    }
148    #[doc = r" Writes raw bits to the register."]
149    #[doc = r""]
150    #[doc = r" # Safety"]
151    #[doc = r""]
152    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.bits = bits;
156        self
157    }
158}
159#[doc = "Control register for lane 1  
160
161You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
162pub struct INTERP0_CTRL_LANE1_SPEC;
163impl crate::RegisterSpec for INTERP0_CTRL_LANE1_SPEC {
164    type Ux = u32;
165}
166#[doc = "`read()` method returns [`interp0_ctrl_lane1::R`](R) reader structure"]
167impl crate::Readable for INTERP0_CTRL_LANE1_SPEC {}
168#[doc = "`write(|w| ..)` method takes [`interp0_ctrl_lane1::W`](W) writer structure"]
169impl crate::Writable for INTERP0_CTRL_LANE1_SPEC {
170    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
171    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
172}
173#[doc = "`reset()` method sets INTERP0_CTRL_LANE1 to value 0"]
174impl crate::Resettable for INTERP0_CTRL_LANE1_SPEC {
175    const RESET_VALUE: u32 = 0;
176}
rp2040_pac/sio/interp0_ctrl_lane1.rs

rp2040_pac/sio/
interp0_ctrl_lane1.rs
