rp2040_pac/
usbctrl_regs.rs

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1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    addr_endp: ADDR_ENDP,
5    host_addr_endp: [HOST_ADDR_ENDP; 15],
6    main_ctrl: MAIN_CTRL,
7    sof_wr: SOF_WR,
8    sof_rd: SOF_RD,
9    sie_ctrl: SIE_CTRL,
10    sie_status: SIE_STATUS,
11    int_ep_ctrl: INT_EP_CTRL,
12    buff_status: BUFF_STATUS,
13    buff_cpu_should_handle: BUFF_CPU_SHOULD_HANDLE,
14    ep_abort: EP_ABORT,
15    ep_abort_done: EP_ABORT_DONE,
16    ep_stall_arm: EP_STALL_ARM,
17    nak_poll: NAK_POLL,
18    ep_status_stall_nak: EP_STATUS_STALL_NAK,
19    usb_muxing: USB_MUXING,
20    usb_pwr: USB_PWR,
21    usbphy_direct: USBPHY_DIRECT,
22    usbphy_direct_override: USBPHY_DIRECT_OVERRIDE,
23    usbphy_trim: USBPHY_TRIM,
24    _reserved20: [u8; 0x04],
25    intr: INTR,
26    inte: INTE,
27    intf: INTF,
28    ints: INTS,
29}
30impl RegisterBlock {
31    #[doc = "0x00 - Device address and endpoint control"]
32    #[inline(always)]
33    pub const fn addr_endp(&self) -> &ADDR_ENDP {
34        &self.addr_endp
35    }
36    #[doc = "0x04..0x40 - Interrupt endpoints. Only valid in HOST mode."]
37    #[inline(always)]
38    pub const fn host_addr_endp(&self, n: usize) -> &HOST_ADDR_ENDP {
39        &self.host_addr_endp[n]
40    }
41    #[doc = "Iterator for array of:"]
42    #[doc = "0x04..0x40 - Interrupt endpoints. Only valid in HOST mode."]
43    #[inline(always)]
44    pub fn host_addr_endp_iter(&self) -> impl Iterator<Item = &HOST_ADDR_ENDP> {
45        self.host_addr_endp.iter()
46    }
47    #[doc = "0x04 - Interrupt endpoints. Only valid in HOST mode."]
48    #[inline(always)]
49    pub const fn host_addr_endp1(&self) -> &HOST_ADDR_ENDP {
50        self.host_addr_endp(0)
51    }
52    #[doc = "0x08 - Interrupt endpoints. Only valid in HOST mode."]
53    #[inline(always)]
54    pub const fn host_addr_endp2(&self) -> &HOST_ADDR_ENDP {
55        self.host_addr_endp(1)
56    }
57    #[doc = "0x0c - Interrupt endpoints. Only valid in HOST mode."]
58    #[inline(always)]
59    pub const fn host_addr_endp3(&self) -> &HOST_ADDR_ENDP {
60        self.host_addr_endp(2)
61    }
62    #[doc = "0x10 - Interrupt endpoints. Only valid in HOST mode."]
63    #[inline(always)]
64    pub const fn host_addr_endp4(&self) -> &HOST_ADDR_ENDP {
65        self.host_addr_endp(3)
66    }
67    #[doc = "0x14 - Interrupt endpoints. Only valid in HOST mode."]
68    #[inline(always)]
69    pub const fn host_addr_endp5(&self) -> &HOST_ADDR_ENDP {
70        self.host_addr_endp(4)
71    }
72    #[doc = "0x18 - Interrupt endpoints. Only valid in HOST mode."]
73    #[inline(always)]
74    pub const fn host_addr_endp6(&self) -> &HOST_ADDR_ENDP {
75        self.host_addr_endp(5)
76    }
77    #[doc = "0x1c - Interrupt endpoints. Only valid in HOST mode."]
78    #[inline(always)]
79    pub const fn host_addr_endp7(&self) -> &HOST_ADDR_ENDP {
80        self.host_addr_endp(6)
81    }
82    #[doc = "0x20 - Interrupt endpoints. Only valid in HOST mode."]
83    #[inline(always)]
84    pub const fn host_addr_endp8(&self) -> &HOST_ADDR_ENDP {
85        self.host_addr_endp(7)
86    }
87    #[doc = "0x24 - Interrupt endpoints. Only valid in HOST mode."]
88    #[inline(always)]
89    pub const fn host_addr_endp9(&self) -> &HOST_ADDR_ENDP {
90        self.host_addr_endp(8)
91    }
92    #[doc = "0x28 - Interrupt endpoints. Only valid in HOST mode."]
93    #[inline(always)]
94    pub const fn host_addr_endp10(&self) -> &HOST_ADDR_ENDP {
95        self.host_addr_endp(9)
96    }
97    #[doc = "0x2c - Interrupt endpoints. Only valid in HOST mode."]
98    #[inline(always)]
99    pub const fn host_addr_endp11(&self) -> &HOST_ADDR_ENDP {
100        self.host_addr_endp(10)
101    }
102    #[doc = "0x30 - Interrupt endpoints. Only valid in HOST mode."]
103    #[inline(always)]
104    pub const fn host_addr_endp12(&self) -> &HOST_ADDR_ENDP {
105        self.host_addr_endp(11)
106    }
107    #[doc = "0x34 - Interrupt endpoints. Only valid in HOST mode."]
108    #[inline(always)]
109    pub const fn host_addr_endp13(&self) -> &HOST_ADDR_ENDP {
110        self.host_addr_endp(12)
111    }
112    #[doc = "0x38 - Interrupt endpoints. Only valid in HOST mode."]
113    #[inline(always)]
114    pub const fn host_addr_endp14(&self) -> &HOST_ADDR_ENDP {
115        self.host_addr_endp(13)
116    }
117    #[doc = "0x3c - Interrupt endpoints. Only valid in HOST mode."]
118    #[inline(always)]
119    pub const fn host_addr_endp15(&self) -> &HOST_ADDR_ENDP {
120        self.host_addr_endp(14)
121    }
122    #[doc = "0x40 - Main control register"]
123    #[inline(always)]
124    pub const fn main_ctrl(&self) -> &MAIN_CTRL {
125        &self.main_ctrl
126    }
127    #[doc = "0x44 - Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."]
128    #[inline(always)]
129    pub const fn sof_wr(&self) -> &SOF_WR {
130        &self.sof_wr
131    }
132    #[doc = "0x48 - Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."]
133    #[inline(always)]
134    pub const fn sof_rd(&self) -> &SOF_RD {
135        &self.sof_rd
136    }
137    #[doc = "0x4c - SIE control register"]
138    #[inline(always)]
139    pub const fn sie_ctrl(&self) -> &SIE_CTRL {
140        &self.sie_ctrl
141    }
142    #[doc = "0x50 - SIE status register"]
143    #[inline(always)]
144    pub const fn sie_status(&self) -> &SIE_STATUS {
145        &self.sie_status
146    }
147    #[doc = "0x54 - interrupt endpoint control register"]
148    #[inline(always)]
149    pub const fn int_ep_ctrl(&self) -> &INT_EP_CTRL {
150        &self.int_ep_ctrl
151    }
152    #[doc = "0x58 - Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."]
153    #[inline(always)]
154    pub const fn buff_status(&self) -> &BUFF_STATUS {
155        &self.buff_status
156    }
157    #[doc = "0x5c - Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."]
158    #[inline(always)]
159    pub const fn buff_cpu_should_handle(&self) -> &BUFF_CPU_SHOULD_HANDLE {
160        &self.buff_cpu_should_handle
161    }
162    #[doc = "0x60 - Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."]
163    #[inline(always)]
164    pub const fn ep_abort(&self) -> &EP_ABORT {
165        &self.ep_abort
166    }
167    #[doc = "0x64 - Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."]
168    #[inline(always)]
169    pub const fn ep_abort_done(&self) -> &EP_ABORT_DONE {
170        &self.ep_abort_done
171    }
172    #[doc = "0x68 - Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."]
173    #[inline(always)]
174    pub const fn ep_stall_arm(&self) -> &EP_STALL_ARM {
175        &self.ep_stall_arm
176    }
177    #[doc = "0x6c - Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."]
178    #[inline(always)]
179    pub const fn nak_poll(&self) -> &NAK_POLL {
180        &self.nak_poll
181    }
182    #[doc = "0x70 - Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."]
183    #[inline(always)]
184    pub const fn ep_status_stall_nak(&self) -> &EP_STATUS_STALL_NAK {
185        &self.ep_status_stall_nak
186    }
187    #[doc = "0x74 - Where to connect the USB controller. Should be to_phy by default."]
188    #[inline(always)]
189    pub const fn usb_muxing(&self) -> &USB_MUXING {
190        &self.usb_muxing
191    }
192    #[doc = "0x78 - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."]
193    #[inline(always)]
194    pub const fn usb_pwr(&self) -> &USB_PWR {
195        &self.usb_pwr
196    }
197    #[doc = "0x7c - This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."]
198    #[inline(always)]
199    pub const fn usbphy_direct(&self) -> &USBPHY_DIRECT {
200        &self.usbphy_direct
201    }
202    #[doc = "0x80 - Override enable for each control in usbphy_direct"]
203    #[inline(always)]
204    pub const fn usbphy_direct_override(&self) -> &USBPHY_DIRECT_OVERRIDE {
205        &self.usbphy_direct_override
206    }
207    #[doc = "0x84 - Used to adjust trim values of USB phy pull down resistors."]
208    #[inline(always)]
209    pub const fn usbphy_trim(&self) -> &USBPHY_TRIM {
210        &self.usbphy_trim
211    }
212    #[doc = "0x8c - Raw Interrupts"]
213    #[inline(always)]
214    pub const fn intr(&self) -> &INTR {
215        &self.intr
216    }
217    #[doc = "0x90 - Interrupt Enable"]
218    #[inline(always)]
219    pub const fn inte(&self) -> &INTE {
220        &self.inte
221    }
222    #[doc = "0x94 - Interrupt Force"]
223    #[inline(always)]
224    pub const fn intf(&self) -> &INTF {
225        &self.intf
226    }
227    #[doc = "0x98 - Interrupt status after masking &amp; forcing"]
228    #[inline(always)]
229    pub const fn ints(&self) -> &INTS {
230        &self.ints
231    }
232}
233#[doc = "ADDR_ENDP (rw) register accessor: Device address and endpoint control  
234
235You can [`read`](crate::generic::Reg::read) this register and get [`addr_endp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr_endp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
236
237For information about available fields see [`mod@addr_endp`]
238module"]
239pub type ADDR_ENDP = crate::Reg<addr_endp::ADDR_ENDP_SPEC>;
240#[doc = "Device address and endpoint control"]
241pub mod addr_endp;
242#[doc = "HOST_ADDR_ENDP (rw) register accessor: Interrupt endpoints. Only valid in HOST mode.  
243
244You can [`read`](crate::generic::Reg::read) this register and get [`host_addr_endp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_addr_endp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
245
246For information about available fields see [`mod@host_addr_endp`]
247module"]
248pub type HOST_ADDR_ENDP = crate::Reg<host_addr_endp::HOST_ADDR_ENDP_SPEC>;
249#[doc = "Interrupt endpoints. Only valid in HOST mode."]
250pub mod host_addr_endp;
251#[doc = "MAIN_CTRL (rw) register accessor: Main control register  
252
253You can [`read`](crate::generic::Reg::read) this register and get [`main_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
254
255For information about available fields see [`mod@main_ctrl`]
256module"]
257pub type MAIN_CTRL = crate::Reg<main_ctrl::MAIN_CTRL_SPEC>;
258#[doc = "Main control register"]
259pub mod main_ctrl;
260#[doc = "SOF_WR (w) register accessor: Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.  
261
262You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
263
264For information about available fields see [`mod@sof_wr`]
265module"]
266pub type SOF_WR = crate::Reg<sof_wr::SOF_WR_SPEC>;
267#[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."]
268pub mod sof_wr;
269#[doc = "SOF_RD (r) register accessor: Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.  
270
271You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
272
273For information about available fields see [`mod@sof_rd`]
274module"]
275pub type SOF_RD = crate::Reg<sof_rd::SOF_RD_SPEC>;
276#[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."]
277pub mod sof_rd;
278#[doc = "SIE_CTRL (rw) register accessor: SIE control register  
279
280You can [`read`](crate::generic::Reg::read) this register and get [`sie_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
281
282For information about available fields see [`mod@sie_ctrl`]
283module"]
284pub type SIE_CTRL = crate::Reg<sie_ctrl::SIE_CTRL_SPEC>;
285#[doc = "SIE control register"]
286pub mod sie_ctrl;
287#[doc = "SIE_STATUS (rw) register accessor: SIE status register  
288
289You can [`read`](crate::generic::Reg::read) this register and get [`sie_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
290
291For information about available fields see [`mod@sie_status`]
292module"]
293pub type SIE_STATUS = crate::Reg<sie_status::SIE_STATUS_SPEC>;
294#[doc = "SIE status register"]
295pub mod sie_status;
296#[doc = "INT_EP_CTRL (rw) register accessor: interrupt endpoint control register  
297
298You can [`read`](crate::generic::Reg::read) this register and get [`int_ep_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ep_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
299
300For information about available fields see [`mod@int_ep_ctrl`]
301module"]
302pub type INT_EP_CTRL = crate::Reg<int_ep_ctrl::INT_EP_CTRL_SPEC>;
303#[doc = "interrupt endpoint control register"]
304pub mod int_ep_ctrl;
305#[doc = "BUFF_STATUS (rw) register accessor: Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.  
306
307You can [`read`](crate::generic::Reg::read) this register and get [`buff_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buff_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
308
309For information about available fields see [`mod@buff_status`]
310module"]
311pub type BUFF_STATUS = crate::Reg<buff_status::BUFF_STATUS_SPEC>;
312#[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."]
313pub mod buff_status;
314#[doc = "BUFF_CPU_SHOULD_HANDLE (r) register accessor: Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.  
315
316You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
317
318For information about available fields see [`mod@buff_cpu_should_handle`]
319module"]
320pub type BUFF_CPU_SHOULD_HANDLE = crate::Reg<buff_cpu_should_handle::BUFF_CPU_SHOULD_HANDLE_SPEC>;
321#[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."]
322pub mod buff_cpu_should_handle;
323#[doc = "EP_ABORT (rw) register accessor: Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.  
324
325You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
326
327For information about available fields see [`mod@ep_abort`]
328module"]
329pub type EP_ABORT = crate::Reg<ep_abort::EP_ABORT_SPEC>;
330#[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."]
331pub mod ep_abort;
332#[doc = "EP_ABORT_DONE (rw) register accessor: Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.  
333
334You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort_done::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
335
336For information about available fields see [`mod@ep_abort_done`]
337module"]
338pub type EP_ABORT_DONE = crate::Reg<ep_abort_done::EP_ABORT_DONE_SPEC>;
339#[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."]
340pub mod ep_abort_done;
341#[doc = "EP_STALL_ARM (rw) register accessor: Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.  
342
343You can [`read`](crate::generic::Reg::read) this register and get [`ep_stall_arm::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_stall_arm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
344
345For information about available fields see [`mod@ep_stall_arm`]
346module"]
347pub type EP_STALL_ARM = crate::Reg<ep_stall_arm::EP_STALL_ARM_SPEC>;
348#[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."]
349pub mod ep_stall_arm;
350#[doc = "NAK_POLL (rw) register accessor: Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.  
351
352You can [`read`](crate::generic::Reg::read) this register and get [`nak_poll::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nak_poll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
353
354For information about available fields see [`mod@nak_poll`]
355module"]
356pub type NAK_POLL = crate::Reg<nak_poll::NAK_POLL_SPEC>;
357#[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."]
358pub mod nak_poll;
359#[doc = "EP_STATUS_STALL_NAK (rw) register accessor: Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.  
360
361You can [`read`](crate::generic::Reg::read) this register and get [`ep_status_stall_nak::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
362
363For information about available fields see [`mod@ep_status_stall_nak`]
364module"]
365pub type EP_STATUS_STALL_NAK = crate::Reg<ep_status_stall_nak::EP_STATUS_STALL_NAK_SPEC>;
366#[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."]
367pub mod ep_status_stall_nak;
368#[doc = "USB_MUXING (rw) register accessor: Where to connect the USB controller. Should be to_phy by default.  
369
370You can [`read`](crate::generic::Reg::read) this register and get [`usb_muxing::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_muxing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
371
372For information about available fields see [`mod@usb_muxing`]
373module"]
374pub type USB_MUXING = crate::Reg<usb_muxing::USB_MUXING_SPEC>;
375#[doc = "Where to connect the USB controller. Should be to_phy by default."]
376pub mod usb_muxing;
377#[doc = "USB_PWR (rw) register accessor: Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.  
378
379You can [`read`](crate::generic::Reg::read) this register and get [`usb_pwr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_pwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
380
381For information about available fields see [`mod@usb_pwr`]
382module"]
383pub type USB_PWR = crate::Reg<usb_pwr::USB_PWR_SPEC>;
384#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."]
385pub mod usb_pwr;
386#[doc = "USBPHY_DIRECT (rw) register accessor: This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.  
387
388You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
389
390For information about available fields see [`mod@usbphy_direct`]
391module"]
392pub type USBPHY_DIRECT = crate::Reg<usbphy_direct::USBPHY_DIRECT_SPEC>;
393#[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."]
394pub mod usbphy_direct;
395#[doc = "USBPHY_DIRECT_OVERRIDE (rw) register accessor: Override enable for each control in usbphy_direct  
396
397You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct_override::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct_override::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
398
399For information about available fields see [`mod@usbphy_direct_override`]
400module"]
401pub type USBPHY_DIRECT_OVERRIDE = crate::Reg<usbphy_direct_override::USBPHY_DIRECT_OVERRIDE_SPEC>;
402#[doc = "Override enable for each control in usbphy_direct"]
403pub mod usbphy_direct_override;
404#[doc = "USBPHY_TRIM (rw) register accessor: Used to adjust trim values of USB phy pull down resistors.  
405
406You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_trim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_trim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
407
408For information about available fields see [`mod@usbphy_trim`]
409module"]
410pub type USBPHY_TRIM = crate::Reg<usbphy_trim::USBPHY_TRIM_SPEC>;
411#[doc = "Used to adjust trim values of USB phy pull down resistors."]
412pub mod usbphy_trim;
413#[doc = "INTR (r) register accessor: Raw Interrupts  
414
415You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
416
417For information about available fields see [`mod@intr`]
418module"]
419pub type INTR = crate::Reg<intr::INTR_SPEC>;
420#[doc = "Raw Interrupts"]
421pub mod intr;
422#[doc = "INTE (rw) register accessor: Interrupt Enable  
423
424You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
425
426For information about available fields see [`mod@inte`]
427module"]
428pub type INTE = crate::Reg<inte::INTE_SPEC>;
429#[doc = "Interrupt Enable"]
430pub mod inte;
431#[doc = "INTF (rw) register accessor: Interrupt Force  
432
433You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
434
435For information about available fields see [`mod@intf`]
436module"]
437pub type INTF = crate::Reg<intf::INTF_SPEC>;
438#[doc = "Interrupt Force"]
439pub mod intf;
440#[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
441
442You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
443
444For information about available fields see [`mod@ints`]
445module"]
446pub type INTS = crate::Reg<ints::INTS_SPEC>;
447#[doc = "Interrupt status after masking &amp; forcing"]
448pub mod ints;
rp2040_pac/usbctrl_regs.rs

rp2040_pac/
usbctrl_regs.rs
