rp2040_pac/rosc/
div.rs

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1#[doc = "Register `DIV` reader"]
2pub type R = crate::R<DIV_SPEC>;
3#[doc = "Register `DIV` writer"]
4pub type W = crate::W<DIV_SPEC>;
5#[doc = "Field `DIV` reader - set to 0xaa0 + div where  
6 div = 0 divides by 32  
7 div = 1-31 divides by div  
8 any other value sets div=31  
9 this register resets to div=16"]
10pub type DIV_R = crate::FieldReader<DIV_A>;
11#[doc = "set to 0xaa0 + div where  
12 div = 0 divides by 32  
13 div = 1-31 divides by div  
14 any other value sets div=31  
15 this register resets to div=16  
16
17Value on reset: 0"]
18#[derive(Clone, Copy, Debug, PartialEq, Eq)]
19#[repr(u16)]
20pub enum DIV_A {
21    #[doc = "2720: `101010100000`"]
22    PASS = 2720,
23}
24impl From<DIV_A> for u16 {
25    #[inline(always)]
26    fn from(variant: DIV_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for DIV_A {
31    type Ux = u16;
32}
33impl DIV_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> Option<DIV_A> {
37        match self.bits {
38            2720 => Some(DIV_A::PASS),
39            _ => None,
40        }
41    }
42    #[doc = "`101010100000`"]
43    #[inline(always)]
44    pub fn is_pass(&self) -> bool {
45        *self == DIV_A::PASS
46    }
47}
48#[doc = "Field `DIV` writer - set to 0xaa0 + div where  
49 div = 0 divides by 32  
50 div = 1-31 divides by div  
51 any other value sets div=31  
52 this register resets to div=16"]
53pub type DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, DIV_A>;
54impl<'a, REG> DIV_W<'a, REG>
55where
56    REG: crate::Writable + crate::RegisterSpec,
57    REG::Ux: From<u16>,
58{
59    #[doc = "`101010100000`"]
60    #[inline(always)]
61    pub fn pass(self) -> &'a mut crate::W<REG> {
62        self.variant(DIV_A::PASS)
63    }
64}
65impl R {
66    #[doc = "Bits 0:11 - set to 0xaa0 + div where  
67 div = 0 divides by 32  
68 div = 1-31 divides by div  
69 any other value sets div=31  
70 this register resets to div=16"]
71    #[inline(always)]
72    pub fn div(&self) -> DIV_R {
73        DIV_R::new((self.bits & 0x0fff) as u16)
74    }
75}
76impl W {
77    #[doc = "Bits 0:11 - set to 0xaa0 + div where  
78 div = 0 divides by 32  
79 div = 1-31 divides by div  
80 any other value sets div=31  
81 this register resets to div=16"]
82    #[inline(always)]
83    #[must_use]
84    pub fn div(&mut self) -> DIV_W<DIV_SPEC> {
85        DIV_W::new(self, 0)
86    }
87    #[doc = r" Writes raw bits to the register."]
88    #[doc = r""]
89    #[doc = r" # Safety"]
90    #[doc = r""]
91    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
92    #[inline(always)]
93    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
94        self.bits = bits;
95        self
96    }
97}
98#[doc = "Controls the output divider  
99
100You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
101pub struct DIV_SPEC;
102impl crate::RegisterSpec for DIV_SPEC {
103    type Ux = u32;
104}
105#[doc = "`read()` method returns [`div::R`](R) reader structure"]
106impl crate::Readable for DIV_SPEC {}
107#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"]
108impl crate::Writable for DIV_SPEC {
109    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
111}
112#[doc = "`reset()` method sets DIV to value 0"]
113impl crate::Resettable for DIV_SPEC {
114    const RESET_VALUE: u32 = 0;
115}
rp2040_pac/rosc/div.rs

rp2040_pac/rosc/
div.rs
