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#[doc = "Register `SCR` reader"]
pub type R = crate::R<SCR_SPEC>;
#[doc = "Register `SCR` writer"]
pub type W = crate::W<SCR_SPEC>;
#[doc = "Field `SLEEPONEXIT` reader - Indicates sleep-on-exit when returning from Handler mode to Thread mode:  
 0 = Do not sleep when returning to Thread mode.  
 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.  
 Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."]
pub type SLEEPONEXIT_R = crate::BitReader;
#[doc = "Field `SLEEPONEXIT` writer - Indicates sleep-on-exit when returning from Handler mode to Thread mode:  
 0 = Do not sleep when returning to Thread mode.  
 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.  
 Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."]
pub type SLEEPONEXIT_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLEEPDEEP` reader - Controls whether the processor uses sleep or deep sleep as its low power mode:  
 0 = Sleep.  
 1 = Deep sleep."]
pub type SLEEPDEEP_R = crate::BitReader;
#[doc = "Field `SLEEPDEEP` writer - Controls whether the processor uses sleep or deep sleep as its low power mode:  
 0 = Sleep.  
 1 = Deep sleep."]
pub type SLEEPDEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit:  
 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.  
 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.  
 When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the  
 processor is not waiting for an event, the event is registered and affects the next WFE.  
 The processor also wakes up on execution of an SEV instruction or an external event."]
pub type SEVONPEND_R = crate::BitReader;
#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit:  
 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.  
 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.  
 When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the  
 processor is not waiting for an event, the event is registered and affects the next WFE.  
 The processor also wakes up on execution of an SEV instruction or an external event."]
pub type SEVONPEND_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode:  
 0 = Do not sleep when returning to Thread mode.  
 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.  
 Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."]
    #[inline(always)]
    pub fn sleeponexit(&self) -> SLEEPONEXIT_R {
        SLEEPONEXIT_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode:  
 0 = Sleep.  
 1 = Deep sleep."]
    #[inline(always)]
    pub fn sleepdeep(&self) -> SLEEPDEEP_R {
        SLEEPDEEP_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 4 - Send Event on Pending bit:  
 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.  
 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.  
 When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the  
 processor is not waiting for an event, the event is registered and affects the next WFE.  
 The processor also wakes up on execution of an SEV instruction or an external event."]
    #[inline(always)]
    pub fn sevonpend(&self) -> SEVONPEND_R {
        SEVONPEND_R::new(((self.bits >> 4) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode:  
 0 = Do not sleep when returning to Thread mode.  
 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.  
 Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."]
    #[inline(always)]
    #[must_use]
    pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W<SCR_SPEC> {
        SLEEPONEXIT_W::new(self, 1)
    }
    #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode:  
 0 = Sleep.  
 1 = Deep sleep."]
    #[inline(always)]
    #[must_use]
    pub fn sleepdeep(&mut self) -> SLEEPDEEP_W<SCR_SPEC> {
        SLEEPDEEP_W::new(self, 2)
    }
    #[doc = "Bit 4 - Send Event on Pending bit:  
 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.  
 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.  
 When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the  
 processor is not waiting for an event, the event is registered and affects the next WFE.  
 The processor also wakes up on execution of an SEV instruction or an external event."]
    #[inline(always)]
    #[must_use]
    pub fn sevonpend(&mut self) -> SEVONPEND_W<SCR_SPEC> {
        SEVONPEND_W::new(self, 4)
    }
    #[doc = r" Writes raw bits to the register."]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
}
#[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.  

You can [`read`](crate::generic::Reg::read) this register and get [`scr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SCR_SPEC;
impl crate::RegisterSpec for SCR_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`scr::R`](R) reader structure"]
impl crate::Readable for SCR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"]
impl crate::Writable for SCR_SPEC {
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SCR to value 0"]
impl crate::Resettable for SCR_SPEC {
    const RESET_VALUE: u32 = 0;
}