rp2040_pac/sio/
interp0_peek_lane0.rs

1#[doc = "Register `INTERP0_PEEK_LANE0` reader"]
2pub type R = crate::R<INTERP0_PEEK_LANE0_SPEC>;
3impl core::fmt::Debug for R {
4    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5        write!(f, "{}", self.bits())
6    }
7}
8impl core::fmt::Debug for crate::generic::Reg<INTERP0_PEEK_LANE0_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        core::fmt::Debug::fmt(&self.read(), f)
11    }
12}
13#[doc = "Read LANE0 result, without altering any internal state (PEEK).  
14
15You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16pub struct INTERP0_PEEK_LANE0_SPEC;
17impl crate::RegisterSpec for INTERP0_PEEK_LANE0_SPEC {
18    type Ux = u32;
19}
20#[doc = "`read()` method returns [`interp0_peek_lane0::R`](R) reader structure"]
21impl crate::Readable for INTERP0_PEEK_LANE0_SPEC {}
22#[doc = "`reset()` method sets INTERP0_PEEK_LANE0 to value 0"]
23impl crate::Resettable for INTERP0_PEEK_LANE0_SPEC {
24    const RESET_VALUE: u32 = 0;
25}