rp2040_pac/i2c0/
ic_dma_cr.rs

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1#[doc = "Register `IC_DMA_CR` reader"]
2pub type R = crate::R<IC_DMA_CR_SPEC>;
3#[doc = "Register `IC_DMA_CR` writer"]
4pub type W = crate::W<IC_DMA_CR_SPEC>;
5#[doc = "Field `RDMAE` reader - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"]
6pub type RDMAE_R = crate::BitReader<RDMAE_A>;
7#[doc = "Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0  
8
9Value on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum RDMAE_A {
12    #[doc = "0: Receive FIFO DMA channel disabled"]
13    DISABLED = 0,
14    #[doc = "1: Receive FIFO DMA channel enabled"]
15    ENABLED = 1,
16}
17impl From<RDMAE_A> for bool {
18    #[inline(always)]
19    fn from(variant: RDMAE_A) -> Self {
20        variant as u8 != 0
21    }
22}
23impl RDMAE_R {
24    #[doc = "Get enumerated values variant"]
25    #[inline(always)]
26    pub const fn variant(&self) -> RDMAE_A {
27        match self.bits {
28            false => RDMAE_A::DISABLED,
29            true => RDMAE_A::ENABLED,
30        }
31    }
32    #[doc = "Receive FIFO DMA channel disabled"]
33    #[inline(always)]
34    pub fn is_disabled(&self) -> bool {
35        *self == RDMAE_A::DISABLED
36    }
37    #[doc = "Receive FIFO DMA channel enabled"]
38    #[inline(always)]
39    pub fn is_enabled(&self) -> bool {
40        *self == RDMAE_A::ENABLED
41    }
42}
43#[doc = "Field `RDMAE` writer - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"]
44pub type RDMAE_W<'a, REG> = crate::BitWriter<'a, REG, RDMAE_A>;
45impl<'a, REG> RDMAE_W<'a, REG>
46where
47    REG: crate::Writable + crate::RegisterSpec,
48{
49    #[doc = "Receive FIFO DMA channel disabled"]
50    #[inline(always)]
51    pub fn disabled(self) -> &'a mut crate::W<REG> {
52        self.variant(RDMAE_A::DISABLED)
53    }
54    #[doc = "Receive FIFO DMA channel enabled"]
55    #[inline(always)]
56    pub fn enabled(self) -> &'a mut crate::W<REG> {
57        self.variant(RDMAE_A::ENABLED)
58    }
59}
60#[doc = "Field `TDMAE` reader - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"]
61pub type TDMAE_R = crate::BitReader<TDMAE_A>;
62#[doc = "Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0  
63
64Value on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum TDMAE_A {
67    #[doc = "0: transmit FIFO DMA channel disabled"]
68    DISABLED = 0,
69    #[doc = "1: Transmit FIFO DMA channel enabled"]
70    ENABLED = 1,
71}
72impl From<TDMAE_A> for bool {
73    #[inline(always)]
74    fn from(variant: TDMAE_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl TDMAE_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> TDMAE_A {
82        match self.bits {
83            false => TDMAE_A::DISABLED,
84            true => TDMAE_A::ENABLED,
85        }
86    }
87    #[doc = "transmit FIFO DMA channel disabled"]
88    #[inline(always)]
89    pub fn is_disabled(&self) -> bool {
90        *self == TDMAE_A::DISABLED
91    }
92    #[doc = "Transmit FIFO DMA channel enabled"]
93    #[inline(always)]
94    pub fn is_enabled(&self) -> bool {
95        *self == TDMAE_A::ENABLED
96    }
97}
98#[doc = "Field `TDMAE` writer - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"]
99pub type TDMAE_W<'a, REG> = crate::BitWriter<'a, REG, TDMAE_A>;
100impl<'a, REG> TDMAE_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "transmit FIFO DMA channel disabled"]
105    #[inline(always)]
106    pub fn disabled(self) -> &'a mut crate::W<REG> {
107        self.variant(TDMAE_A::DISABLED)
108    }
109    #[doc = "Transmit FIFO DMA channel enabled"]
110    #[inline(always)]
111    pub fn enabled(self) -> &'a mut crate::W<REG> {
112        self.variant(TDMAE_A::ENABLED)
113    }
114}
115impl R {
116    #[doc = "Bit 0 - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"]
117    #[inline(always)]
118    pub fn rdmae(&self) -> RDMAE_R {
119        RDMAE_R::new((self.bits & 1) != 0)
120    }
121    #[doc = "Bit 1 - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"]
122    #[inline(always)]
123    pub fn tdmae(&self) -> TDMAE_R {
124        TDMAE_R::new(((self.bits >> 1) & 1) != 0)
125    }
126}
127impl W {
128    #[doc = "Bit 0 - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"]
129    #[inline(always)]
130    #[must_use]
131    pub fn rdmae(&mut self) -> RDMAE_W<IC_DMA_CR_SPEC> {
132        RDMAE_W::new(self, 0)
133    }
134    #[doc = "Bit 1 - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"]
135    #[inline(always)]
136    #[must_use]
137    pub fn tdmae(&mut self) -> TDMAE_W<IC_DMA_CR_SPEC> {
138        TDMAE_W::new(self, 1)
139    }
140    #[doc = r" Writes raw bits to the register."]
141    #[doc = r""]
142    #[doc = r" # Safety"]
143    #[doc = r""]
144    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
145    #[inline(always)]
146    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
147        self.bits = bits;
148        self
149    }
150}
151#[doc = "DMA Control Register  
152
153 The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.  
154
155You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_cr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
156pub struct IC_DMA_CR_SPEC;
157impl crate::RegisterSpec for IC_DMA_CR_SPEC {
158    type Ux = u32;
159}
160#[doc = "`read()` method returns [`ic_dma_cr::R`](R) reader structure"]
161impl crate::Readable for IC_DMA_CR_SPEC {}
162#[doc = "`write(|w| ..)` method takes [`ic_dma_cr::W`](W) writer structure"]
163impl crate::Writable for IC_DMA_CR_SPEC {
164    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
165    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
166}
167#[doc = "`reset()` method sets IC_DMA_CR to value 0"]
168impl crate::Resettable for IC_DMA_CR_SPEC {
169    const RESET_VALUE: u32 = 0;
170}
rp2040_pac/i2c0/ic_dma_cr.rs

rp2040_pac/i2c0/
ic_dma_cr.rs
