imxrt_ral/blocks/imxrt1011/
xtalosc24m.rs
1#[doc = "XTALOSC24M"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x0150],
5 #[doc = "Miscellaneous Register 0"]
6 pub MISC0: crate::RWRegister<u32>,
7 #[doc = "Miscellaneous Register 0"]
8 pub MISC0_SET: crate::RWRegister<u32>,
9 #[doc = "Miscellaneous Register 0"]
10 pub MISC0_CLR: crate::RWRegister<u32>,
11 #[doc = "Miscellaneous Register 0"]
12 pub MISC0_TOG: crate::RWRegister<u32>,
13 _reserved1: [u8; 0x0110],
14 #[doc = "XTAL OSC (LP) Control Register"]
15 pub LOWPWR_CTRL: crate::RWRegister<u32>,
16 #[doc = "XTAL OSC (LP) Control Register"]
17 pub LOWPWR_CTRL_SET: crate::RWRegister<u32>,
18 #[doc = "XTAL OSC (LP) Control Register"]
19 pub LOWPWR_CTRL_CLR: crate::RWRegister<u32>,
20 #[doc = "XTAL OSC (LP) Control Register"]
21 pub LOWPWR_CTRL_TOG: crate::RWRegister<u32>,
22 _reserved2: [u8; 0x20],
23 #[doc = "XTAL OSC Configuration 0 Register"]
24 pub OSC_CONFIG0: crate::RWRegister<u32>,
25 #[doc = "XTAL OSC Configuration 0 Register"]
26 pub OSC_CONFIG0_SET: crate::RWRegister<u32>,
27 #[doc = "XTAL OSC Configuration 0 Register"]
28 pub OSC_CONFIG0_CLR: crate::RWRegister<u32>,
29 #[doc = "XTAL OSC Configuration 0 Register"]
30 pub OSC_CONFIG0_TOG: crate::RWRegister<u32>,
31 #[doc = "XTAL OSC Configuration 1 Register"]
32 pub OSC_CONFIG1: crate::RWRegister<u32>,
33 #[doc = "XTAL OSC Configuration 1 Register"]
34 pub OSC_CONFIG1_SET: crate::RWRegister<u32>,
35 #[doc = "XTAL OSC Configuration 1 Register"]
36 pub OSC_CONFIG1_CLR: crate::RWRegister<u32>,
37 #[doc = "XTAL OSC Configuration 1 Register"]
38 pub OSC_CONFIG1_TOG: crate::RWRegister<u32>,
39 #[doc = "XTAL OSC Configuration 2 Register"]
40 pub OSC_CONFIG2: crate::RWRegister<u32>,
41 #[doc = "XTAL OSC Configuration 2 Register"]
42 pub OSC_CONFIG2_SET: crate::RWRegister<u32>,
43 #[doc = "XTAL OSC Configuration 2 Register"]
44 pub OSC_CONFIG2_CLR: crate::RWRegister<u32>,
45 #[doc = "XTAL OSC Configuration 2 Register"]
46 pub OSC_CONFIG2_TOG: crate::RWRegister<u32>,
47}
48#[doc = "Miscellaneous Register 0"]
49pub mod MISC0 {
50 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
51 pub mod REFTOP_PWD {
52 pub const offset: u32 = 0;
53 pub const mask: u32 = 0x01 << offset;
54 pub mod R {}
55 pub mod W {}
56 pub mod RW {}
57 }
58 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
59 pub mod REFTOP_SELFBIASOFF {
60 pub const offset: u32 = 3;
61 pub const mask: u32 = 0x01 << offset;
62 pub mod R {}
63 pub mod W {}
64 pub mod RW {
65 #[doc = "Uses coarse bias currents for startup"]
66 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
67 #[doc = "Uses bandgap-based bias currents for best performance."]
68 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
69 }
70 }
71 #[doc = "Not related to oscillator."]
72 pub mod REFTOP_VBGADJ {
73 pub const offset: u32 = 4;
74 pub const mask: u32 = 0x07 << offset;
75 pub mod R {}
76 pub mod W {}
77 pub mod RW {
78 #[doc = "Nominal VBG"]
79 pub const REFTOP_VBGADJ_0: u32 = 0;
80 #[doc = "VBG+0.78%"]
81 pub const REFTOP_VBGADJ_1: u32 = 0x01;
82 #[doc = "VBG+1.56%"]
83 pub const REFTOP_VBGADJ_2: u32 = 0x02;
84 #[doc = "VBG+2.34%"]
85 pub const REFTOP_VBGADJ_3: u32 = 0x03;
86 #[doc = "VBG-0.78%"]
87 pub const REFTOP_VBGADJ_4: u32 = 0x04;
88 #[doc = "VBG-1.56%"]
89 pub const REFTOP_VBGADJ_5: u32 = 0x05;
90 #[doc = "VBG-2.34%"]
91 pub const REFTOP_VBGADJ_6: u32 = 0x06;
92 #[doc = "VBG-3.12%"]
93 pub const REFTOP_VBGADJ_7: u32 = 0x07;
94 }
95 }
96 #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
97 pub mod REFTOP_VBGUP {
98 pub const offset: u32 = 7;
99 pub const mask: u32 = 0x01 << offset;
100 pub mod R {}
101 pub mod W {}
102 pub mod RW {}
103 }
104 #[doc = "Configure the analog behavior in stop mode.Not related to oscillator."]
105 pub mod STOP_MODE_CONFIG {
106 pub const offset: u32 = 10;
107 pub const mask: u32 = 0x03 << offset;
108 pub mod R {}
109 pub mod W {}
110 pub mod RW {
111 #[doc = "All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;"]
112 pub const STOP_MODE_CONFIG_0: u32 = 0;
113 #[doc = "Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;"]
114 pub const STOP_MODE_CONFIG_1: u32 = 0x01;
115 #[doc = "XtalOsc=off, RCOsc=on, Old BG=on, New BG=off."]
116 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
117 #[doc = "XtalOsc=off, RCOsc=on, Old BG=off, New BG=on."]
118 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
119 }
120 }
121 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
122 pub mod DISCON_HIGH_SNVS {
123 pub const offset: u32 = 12;
124 pub const mask: u32 = 0x01 << offset;
125 pub mod R {}
126 pub mod W {}
127 pub mod RW {
128 #[doc = "Turn on the switch"]
129 pub const DISCON_HIGH_SNVS_0: u32 = 0;
130 #[doc = "Turn off the switch"]
131 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
132 }
133 }
134 #[doc = "This field determines the bias current in the 24MHz oscillator"]
135 pub mod OSC_I {
136 pub const offset: u32 = 13;
137 pub const mask: u32 = 0x03 << offset;
138 pub mod R {}
139 pub mod W {}
140 pub mod RW {
141 #[doc = "Nominal"]
142 pub const NOMINAL: u32 = 0;
143 #[doc = "Decrease current by 12.5%"]
144 pub const MINUS_12_5_PERCENT: u32 = 0x01;
145 #[doc = "Decrease current by 25.0%"]
146 pub const MINUS_25_PERCENT: u32 = 0x02;
147 #[doc = "Decrease current by 37.5%"]
148 pub const MINUS_37_5_PERCENT: u32 = 0x03;
149 }
150 }
151 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
152 pub mod OSC_XTALOK {
153 pub const offset: u32 = 15;
154 pub const mask: u32 = 0x01 << offset;
155 pub mod R {}
156 pub mod W {}
157 pub mod RW {}
158 }
159 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable."]
160 pub mod OSC_XTALOK_EN {
161 pub const offset: u32 = 16;
162 pub const mask: u32 = 0x01 << offset;
163 pub mod R {}
164 pub mod W {}
165 pub mod RW {}
166 }
167 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
168 pub mod CLKGATE_CTRL {
169 pub const offset: u32 = 25;
170 pub const mask: u32 = 0x01 << offset;
171 pub mod R {}
172 pub mod W {}
173 pub mod RW {
174 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
175 pub const ALLOW_AUTO_GATE: u32 = 0;
176 #[doc = "Prevent the logic from ever gating off the clock."]
177 pub const NO_AUTO_GATE: u32 = 0x01;
178 }
179 }
180 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
181 pub mod CLKGATE_DELAY {
182 pub const offset: u32 = 26;
183 pub const mask: u32 = 0x07 << offset;
184 pub mod R {}
185 pub mod W {}
186 pub mod RW {
187 #[doc = "0.5ms"]
188 pub const CLKGATE_DELAY_0: u32 = 0;
189 #[doc = "1.0ms"]
190 pub const CLKGATE_DELAY_1: u32 = 0x01;
191 #[doc = "2.0ms"]
192 pub const CLKGATE_DELAY_2: u32 = 0x02;
193 #[doc = "3.0ms"]
194 pub const CLKGATE_DELAY_3: u32 = 0x03;
195 #[doc = "4.0ms"]
196 pub const CLKGATE_DELAY_4: u32 = 0x04;
197 #[doc = "5.0ms"]
198 pub const CLKGATE_DELAY_5: u32 = 0x05;
199 #[doc = "6.0ms"]
200 pub const CLKGATE_DELAY_6: u32 = 0x06;
201 #[doc = "7.0ms"]
202 pub const CLKGATE_DELAY_7: u32 = 0x07;
203 }
204 }
205 #[doc = "This field indicates which chip source is being used for the rtc clock."]
206 pub mod RTC_XTAL_SOURCE {
207 pub const offset: u32 = 29;
208 pub const mask: u32 = 0x01 << offset;
209 pub mod R {}
210 pub mod W {}
211 pub mod RW {
212 #[doc = "Internal ring oscillator"]
213 pub const RTC_XTAL_SOURCE_0: u32 = 0;
214 #[doc = "RTC_XTAL"]
215 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
216 }
217 }
218 #[doc = "This field powers down the 24M crystal oscillator if set true."]
219 pub mod XTAL_24M_PWD {
220 pub const offset: u32 = 30;
221 pub const mask: u32 = 0x01 << offset;
222 pub mod R {}
223 pub mod W {}
224 pub mod RW {}
225 }
226 #[doc = "Predivider for the source clock of the PLL's. Not related to oscillator."]
227 pub mod VID_PLL_PREDIV {
228 pub const offset: u32 = 31;
229 pub const mask: u32 = 0x01 << offset;
230 pub mod R {}
231 pub mod W {}
232 pub mod RW {
233 #[doc = "Divide by 1"]
234 pub const VID_PLL_PREDIV_0: u32 = 0;
235 #[doc = "Divide by 2"]
236 pub const VID_PLL_PREDIV_1: u32 = 0x01;
237 }
238 }
239}
240#[doc = "Miscellaneous Register 0"]
241pub mod MISC0_SET {
242 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
243 pub mod REFTOP_PWD {
244 pub const offset: u32 = 0;
245 pub const mask: u32 = 0x01 << offset;
246 pub mod R {}
247 pub mod W {}
248 pub mod RW {}
249 }
250 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
251 pub mod REFTOP_SELFBIASOFF {
252 pub const offset: u32 = 3;
253 pub const mask: u32 = 0x01 << offset;
254 pub mod R {}
255 pub mod W {}
256 pub mod RW {
257 #[doc = "Uses coarse bias currents for startup"]
258 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
259 #[doc = "Uses bandgap-based bias currents for best performance."]
260 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
261 }
262 }
263 #[doc = "Not related to oscillator."]
264 pub mod REFTOP_VBGADJ {
265 pub const offset: u32 = 4;
266 pub const mask: u32 = 0x07 << offset;
267 pub mod R {}
268 pub mod W {}
269 pub mod RW {
270 #[doc = "Nominal VBG"]
271 pub const REFTOP_VBGADJ_0: u32 = 0;
272 #[doc = "VBG+0.78%"]
273 pub const REFTOP_VBGADJ_1: u32 = 0x01;
274 #[doc = "VBG+1.56%"]
275 pub const REFTOP_VBGADJ_2: u32 = 0x02;
276 #[doc = "VBG+2.34%"]
277 pub const REFTOP_VBGADJ_3: u32 = 0x03;
278 #[doc = "VBG-0.78%"]
279 pub const REFTOP_VBGADJ_4: u32 = 0x04;
280 #[doc = "VBG-1.56%"]
281 pub const REFTOP_VBGADJ_5: u32 = 0x05;
282 #[doc = "VBG-2.34%"]
283 pub const REFTOP_VBGADJ_6: u32 = 0x06;
284 #[doc = "VBG-3.12%"]
285 pub const REFTOP_VBGADJ_7: u32 = 0x07;
286 }
287 }
288 #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
289 pub mod REFTOP_VBGUP {
290 pub const offset: u32 = 7;
291 pub const mask: u32 = 0x01 << offset;
292 pub mod R {}
293 pub mod W {}
294 pub mod RW {}
295 }
296 #[doc = "Configure the analog behavior in stop mode.Not related to oscillator."]
297 pub mod STOP_MODE_CONFIG {
298 pub const offset: u32 = 10;
299 pub const mask: u32 = 0x03 << offset;
300 pub mod R {}
301 pub mod W {}
302 pub mod RW {
303 #[doc = "All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;"]
304 pub const STOP_MODE_CONFIG_0: u32 = 0;
305 #[doc = "Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;"]
306 pub const STOP_MODE_CONFIG_1: u32 = 0x01;
307 #[doc = "XtalOsc=off, RCOsc=on, Old BG=on, New BG=off."]
308 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
309 #[doc = "XtalOsc=off, RCOsc=on, Old BG=off, New BG=on."]
310 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
311 }
312 }
313 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
314 pub mod DISCON_HIGH_SNVS {
315 pub const offset: u32 = 12;
316 pub const mask: u32 = 0x01 << offset;
317 pub mod R {}
318 pub mod W {}
319 pub mod RW {
320 #[doc = "Turn on the switch"]
321 pub const DISCON_HIGH_SNVS_0: u32 = 0;
322 #[doc = "Turn off the switch"]
323 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
324 }
325 }
326 #[doc = "This field determines the bias current in the 24MHz oscillator"]
327 pub mod OSC_I {
328 pub const offset: u32 = 13;
329 pub const mask: u32 = 0x03 << offset;
330 pub mod R {}
331 pub mod W {}
332 pub mod RW {
333 #[doc = "Nominal"]
334 pub const NOMINAL: u32 = 0;
335 #[doc = "Decrease current by 12.5%"]
336 pub const MINUS_12_5_PERCENT: u32 = 0x01;
337 #[doc = "Decrease current by 25.0%"]
338 pub const MINUS_25_PERCENT: u32 = 0x02;
339 #[doc = "Decrease current by 37.5%"]
340 pub const MINUS_37_5_PERCENT: u32 = 0x03;
341 }
342 }
343 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
344 pub mod OSC_XTALOK {
345 pub const offset: u32 = 15;
346 pub const mask: u32 = 0x01 << offset;
347 pub mod R {}
348 pub mod W {}
349 pub mod RW {}
350 }
351 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable."]
352 pub mod OSC_XTALOK_EN {
353 pub const offset: u32 = 16;
354 pub const mask: u32 = 0x01 << offset;
355 pub mod R {}
356 pub mod W {}
357 pub mod RW {}
358 }
359 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
360 pub mod CLKGATE_CTRL {
361 pub const offset: u32 = 25;
362 pub const mask: u32 = 0x01 << offset;
363 pub mod R {}
364 pub mod W {}
365 pub mod RW {
366 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
367 pub const ALLOW_AUTO_GATE: u32 = 0;
368 #[doc = "Prevent the logic from ever gating off the clock."]
369 pub const NO_AUTO_GATE: u32 = 0x01;
370 }
371 }
372 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
373 pub mod CLKGATE_DELAY {
374 pub const offset: u32 = 26;
375 pub const mask: u32 = 0x07 << offset;
376 pub mod R {}
377 pub mod W {}
378 pub mod RW {
379 #[doc = "0.5ms"]
380 pub const CLKGATE_DELAY_0: u32 = 0;
381 #[doc = "1.0ms"]
382 pub const CLKGATE_DELAY_1: u32 = 0x01;
383 #[doc = "2.0ms"]
384 pub const CLKGATE_DELAY_2: u32 = 0x02;
385 #[doc = "3.0ms"]
386 pub const CLKGATE_DELAY_3: u32 = 0x03;
387 #[doc = "4.0ms"]
388 pub const CLKGATE_DELAY_4: u32 = 0x04;
389 #[doc = "5.0ms"]
390 pub const CLKGATE_DELAY_5: u32 = 0x05;
391 #[doc = "6.0ms"]
392 pub const CLKGATE_DELAY_6: u32 = 0x06;
393 #[doc = "7.0ms"]
394 pub const CLKGATE_DELAY_7: u32 = 0x07;
395 }
396 }
397 #[doc = "This field indicates which chip source is being used for the rtc clock."]
398 pub mod RTC_XTAL_SOURCE {
399 pub const offset: u32 = 29;
400 pub const mask: u32 = 0x01 << offset;
401 pub mod R {}
402 pub mod W {}
403 pub mod RW {
404 #[doc = "Internal ring oscillator"]
405 pub const RTC_XTAL_SOURCE_0: u32 = 0;
406 #[doc = "RTC_XTAL"]
407 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
408 }
409 }
410 #[doc = "This field powers down the 24M crystal oscillator if set true."]
411 pub mod XTAL_24M_PWD {
412 pub const offset: u32 = 30;
413 pub const mask: u32 = 0x01 << offset;
414 pub mod R {}
415 pub mod W {}
416 pub mod RW {}
417 }
418 #[doc = "Predivider for the source clock of the PLL's. Not related to oscillator."]
419 pub mod VID_PLL_PREDIV {
420 pub const offset: u32 = 31;
421 pub const mask: u32 = 0x01 << offset;
422 pub mod R {}
423 pub mod W {}
424 pub mod RW {
425 #[doc = "Divide by 1"]
426 pub const VID_PLL_PREDIV_0: u32 = 0;
427 #[doc = "Divide by 2"]
428 pub const VID_PLL_PREDIV_1: u32 = 0x01;
429 }
430 }
431}
432#[doc = "Miscellaneous Register 0"]
433pub mod MISC0_CLR {
434 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
435 pub mod REFTOP_PWD {
436 pub const offset: u32 = 0;
437 pub const mask: u32 = 0x01 << offset;
438 pub mod R {}
439 pub mod W {}
440 pub mod RW {}
441 }
442 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
443 pub mod REFTOP_SELFBIASOFF {
444 pub const offset: u32 = 3;
445 pub const mask: u32 = 0x01 << offset;
446 pub mod R {}
447 pub mod W {}
448 pub mod RW {
449 #[doc = "Uses coarse bias currents for startup"]
450 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
451 #[doc = "Uses bandgap-based bias currents for best performance."]
452 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
453 }
454 }
455 #[doc = "Not related to oscillator."]
456 pub mod REFTOP_VBGADJ {
457 pub const offset: u32 = 4;
458 pub const mask: u32 = 0x07 << offset;
459 pub mod R {}
460 pub mod W {}
461 pub mod RW {
462 #[doc = "Nominal VBG"]
463 pub const REFTOP_VBGADJ_0: u32 = 0;
464 #[doc = "VBG+0.78%"]
465 pub const REFTOP_VBGADJ_1: u32 = 0x01;
466 #[doc = "VBG+1.56%"]
467 pub const REFTOP_VBGADJ_2: u32 = 0x02;
468 #[doc = "VBG+2.34%"]
469 pub const REFTOP_VBGADJ_3: u32 = 0x03;
470 #[doc = "VBG-0.78%"]
471 pub const REFTOP_VBGADJ_4: u32 = 0x04;
472 #[doc = "VBG-1.56%"]
473 pub const REFTOP_VBGADJ_5: u32 = 0x05;
474 #[doc = "VBG-2.34%"]
475 pub const REFTOP_VBGADJ_6: u32 = 0x06;
476 #[doc = "VBG-3.12%"]
477 pub const REFTOP_VBGADJ_7: u32 = 0x07;
478 }
479 }
480 #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
481 pub mod REFTOP_VBGUP {
482 pub const offset: u32 = 7;
483 pub const mask: u32 = 0x01 << offset;
484 pub mod R {}
485 pub mod W {}
486 pub mod RW {}
487 }
488 #[doc = "Configure the analog behavior in stop mode.Not related to oscillator."]
489 pub mod STOP_MODE_CONFIG {
490 pub const offset: u32 = 10;
491 pub const mask: u32 = 0x03 << offset;
492 pub mod R {}
493 pub mod W {}
494 pub mod RW {
495 #[doc = "All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;"]
496 pub const STOP_MODE_CONFIG_0: u32 = 0;
497 #[doc = "Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;"]
498 pub const STOP_MODE_CONFIG_1: u32 = 0x01;
499 #[doc = "XtalOsc=off, RCOsc=on, Old BG=on, New BG=off."]
500 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
501 #[doc = "XtalOsc=off, RCOsc=on, Old BG=off, New BG=on."]
502 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
503 }
504 }
505 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
506 pub mod DISCON_HIGH_SNVS {
507 pub const offset: u32 = 12;
508 pub const mask: u32 = 0x01 << offset;
509 pub mod R {}
510 pub mod W {}
511 pub mod RW {
512 #[doc = "Turn on the switch"]
513 pub const DISCON_HIGH_SNVS_0: u32 = 0;
514 #[doc = "Turn off the switch"]
515 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
516 }
517 }
518 #[doc = "This field determines the bias current in the 24MHz oscillator"]
519 pub mod OSC_I {
520 pub const offset: u32 = 13;
521 pub const mask: u32 = 0x03 << offset;
522 pub mod R {}
523 pub mod W {}
524 pub mod RW {
525 #[doc = "Nominal"]
526 pub const NOMINAL: u32 = 0;
527 #[doc = "Decrease current by 12.5%"]
528 pub const MINUS_12_5_PERCENT: u32 = 0x01;
529 #[doc = "Decrease current by 25.0%"]
530 pub const MINUS_25_PERCENT: u32 = 0x02;
531 #[doc = "Decrease current by 37.5%"]
532 pub const MINUS_37_5_PERCENT: u32 = 0x03;
533 }
534 }
535 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
536 pub mod OSC_XTALOK {
537 pub const offset: u32 = 15;
538 pub const mask: u32 = 0x01 << offset;
539 pub mod R {}
540 pub mod W {}
541 pub mod RW {}
542 }
543 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable."]
544 pub mod OSC_XTALOK_EN {
545 pub const offset: u32 = 16;
546 pub const mask: u32 = 0x01 << offset;
547 pub mod R {}
548 pub mod W {}
549 pub mod RW {}
550 }
551 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
552 pub mod CLKGATE_CTRL {
553 pub const offset: u32 = 25;
554 pub const mask: u32 = 0x01 << offset;
555 pub mod R {}
556 pub mod W {}
557 pub mod RW {
558 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
559 pub const ALLOW_AUTO_GATE: u32 = 0;
560 #[doc = "Prevent the logic from ever gating off the clock."]
561 pub const NO_AUTO_GATE: u32 = 0x01;
562 }
563 }
564 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
565 pub mod CLKGATE_DELAY {
566 pub const offset: u32 = 26;
567 pub const mask: u32 = 0x07 << offset;
568 pub mod R {}
569 pub mod W {}
570 pub mod RW {
571 #[doc = "0.5ms"]
572 pub const CLKGATE_DELAY_0: u32 = 0;
573 #[doc = "1.0ms"]
574 pub const CLKGATE_DELAY_1: u32 = 0x01;
575 #[doc = "2.0ms"]
576 pub const CLKGATE_DELAY_2: u32 = 0x02;
577 #[doc = "3.0ms"]
578 pub const CLKGATE_DELAY_3: u32 = 0x03;
579 #[doc = "4.0ms"]
580 pub const CLKGATE_DELAY_4: u32 = 0x04;
581 #[doc = "5.0ms"]
582 pub const CLKGATE_DELAY_5: u32 = 0x05;
583 #[doc = "6.0ms"]
584 pub const CLKGATE_DELAY_6: u32 = 0x06;
585 #[doc = "7.0ms"]
586 pub const CLKGATE_DELAY_7: u32 = 0x07;
587 }
588 }
589 #[doc = "This field indicates which chip source is being used for the rtc clock."]
590 pub mod RTC_XTAL_SOURCE {
591 pub const offset: u32 = 29;
592 pub const mask: u32 = 0x01 << offset;
593 pub mod R {}
594 pub mod W {}
595 pub mod RW {
596 #[doc = "Internal ring oscillator"]
597 pub const RTC_XTAL_SOURCE_0: u32 = 0;
598 #[doc = "RTC_XTAL"]
599 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
600 }
601 }
602 #[doc = "This field powers down the 24M crystal oscillator if set true."]
603 pub mod XTAL_24M_PWD {
604 pub const offset: u32 = 30;
605 pub const mask: u32 = 0x01 << offset;
606 pub mod R {}
607 pub mod W {}
608 pub mod RW {}
609 }
610 #[doc = "Predivider for the source clock of the PLL's. Not related to oscillator."]
611 pub mod VID_PLL_PREDIV {
612 pub const offset: u32 = 31;
613 pub const mask: u32 = 0x01 << offset;
614 pub mod R {}
615 pub mod W {}
616 pub mod RW {
617 #[doc = "Divide by 1"]
618 pub const VID_PLL_PREDIV_0: u32 = 0;
619 #[doc = "Divide by 2"]
620 pub const VID_PLL_PREDIV_1: u32 = 0x01;
621 }
622 }
623}
624#[doc = "Miscellaneous Register 0"]
625pub mod MISC0_TOG {
626 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
627 pub mod REFTOP_PWD {
628 pub const offset: u32 = 0;
629 pub const mask: u32 = 0x01 << offset;
630 pub mod R {}
631 pub mod W {}
632 pub mod RW {}
633 }
634 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
635 pub mod REFTOP_SELFBIASOFF {
636 pub const offset: u32 = 3;
637 pub const mask: u32 = 0x01 << offset;
638 pub mod R {}
639 pub mod W {}
640 pub mod RW {
641 #[doc = "Uses coarse bias currents for startup"]
642 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
643 #[doc = "Uses bandgap-based bias currents for best performance."]
644 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
645 }
646 }
647 #[doc = "Not related to oscillator."]
648 pub mod REFTOP_VBGADJ {
649 pub const offset: u32 = 4;
650 pub const mask: u32 = 0x07 << offset;
651 pub mod R {}
652 pub mod W {}
653 pub mod RW {
654 #[doc = "Nominal VBG"]
655 pub const REFTOP_VBGADJ_0: u32 = 0;
656 #[doc = "VBG+0.78%"]
657 pub const REFTOP_VBGADJ_1: u32 = 0x01;
658 #[doc = "VBG+1.56%"]
659 pub const REFTOP_VBGADJ_2: u32 = 0x02;
660 #[doc = "VBG+2.34%"]
661 pub const REFTOP_VBGADJ_3: u32 = 0x03;
662 #[doc = "VBG-0.78%"]
663 pub const REFTOP_VBGADJ_4: u32 = 0x04;
664 #[doc = "VBG-1.56%"]
665 pub const REFTOP_VBGADJ_5: u32 = 0x05;
666 #[doc = "VBG-2.34%"]
667 pub const REFTOP_VBGADJ_6: u32 = 0x06;
668 #[doc = "VBG-3.12%"]
669 pub const REFTOP_VBGADJ_7: u32 = 0x07;
670 }
671 }
672 #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
673 pub mod REFTOP_VBGUP {
674 pub const offset: u32 = 7;
675 pub const mask: u32 = 0x01 << offset;
676 pub mod R {}
677 pub mod W {}
678 pub mod RW {}
679 }
680 #[doc = "Configure the analog behavior in stop mode.Not related to oscillator."]
681 pub mod STOP_MODE_CONFIG {
682 pub const offset: u32 = 10;
683 pub const mask: u32 = 0x03 << offset;
684 pub mod R {}
685 pub mod W {}
686 pub mod RW {
687 #[doc = "All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;"]
688 pub const STOP_MODE_CONFIG_0: u32 = 0;
689 #[doc = "Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;"]
690 pub const STOP_MODE_CONFIG_1: u32 = 0x01;
691 #[doc = "XtalOsc=off, RCOsc=on, Old BG=on, New BG=off."]
692 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
693 #[doc = "XtalOsc=off, RCOsc=on, Old BG=off, New BG=on."]
694 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
695 }
696 }
697 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
698 pub mod DISCON_HIGH_SNVS {
699 pub const offset: u32 = 12;
700 pub const mask: u32 = 0x01 << offset;
701 pub mod R {}
702 pub mod W {}
703 pub mod RW {
704 #[doc = "Turn on the switch"]
705 pub const DISCON_HIGH_SNVS_0: u32 = 0;
706 #[doc = "Turn off the switch"]
707 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
708 }
709 }
710 #[doc = "This field determines the bias current in the 24MHz oscillator"]
711 pub mod OSC_I {
712 pub const offset: u32 = 13;
713 pub const mask: u32 = 0x03 << offset;
714 pub mod R {}
715 pub mod W {}
716 pub mod RW {
717 #[doc = "Nominal"]
718 pub const NOMINAL: u32 = 0;
719 #[doc = "Decrease current by 12.5%"]
720 pub const MINUS_12_5_PERCENT: u32 = 0x01;
721 #[doc = "Decrease current by 25.0%"]
722 pub const MINUS_25_PERCENT: u32 = 0x02;
723 #[doc = "Decrease current by 37.5%"]
724 pub const MINUS_37_5_PERCENT: u32 = 0x03;
725 }
726 }
727 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
728 pub mod OSC_XTALOK {
729 pub const offset: u32 = 15;
730 pub const mask: u32 = 0x01 << offset;
731 pub mod R {}
732 pub mod W {}
733 pub mod RW {}
734 }
735 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable."]
736 pub mod OSC_XTALOK_EN {
737 pub const offset: u32 = 16;
738 pub const mask: u32 = 0x01 << offset;
739 pub mod R {}
740 pub mod W {}
741 pub mod RW {}
742 }
743 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
744 pub mod CLKGATE_CTRL {
745 pub const offset: u32 = 25;
746 pub const mask: u32 = 0x01 << offset;
747 pub mod R {}
748 pub mod W {}
749 pub mod RW {
750 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
751 pub const ALLOW_AUTO_GATE: u32 = 0;
752 #[doc = "Prevent the logic from ever gating off the clock."]
753 pub const NO_AUTO_GATE: u32 = 0x01;
754 }
755 }
756 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
757 pub mod CLKGATE_DELAY {
758 pub const offset: u32 = 26;
759 pub const mask: u32 = 0x07 << offset;
760 pub mod R {}
761 pub mod W {}
762 pub mod RW {
763 #[doc = "0.5ms"]
764 pub const CLKGATE_DELAY_0: u32 = 0;
765 #[doc = "1.0ms"]
766 pub const CLKGATE_DELAY_1: u32 = 0x01;
767 #[doc = "2.0ms"]
768 pub const CLKGATE_DELAY_2: u32 = 0x02;
769 #[doc = "3.0ms"]
770 pub const CLKGATE_DELAY_3: u32 = 0x03;
771 #[doc = "4.0ms"]
772 pub const CLKGATE_DELAY_4: u32 = 0x04;
773 #[doc = "5.0ms"]
774 pub const CLKGATE_DELAY_5: u32 = 0x05;
775 #[doc = "6.0ms"]
776 pub const CLKGATE_DELAY_6: u32 = 0x06;
777 #[doc = "7.0ms"]
778 pub const CLKGATE_DELAY_7: u32 = 0x07;
779 }
780 }
781 #[doc = "This field indicates which chip source is being used for the rtc clock."]
782 pub mod RTC_XTAL_SOURCE {
783 pub const offset: u32 = 29;
784 pub const mask: u32 = 0x01 << offset;
785 pub mod R {}
786 pub mod W {}
787 pub mod RW {
788 #[doc = "Internal ring oscillator"]
789 pub const RTC_XTAL_SOURCE_0: u32 = 0;
790 #[doc = "RTC_XTAL"]
791 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
792 }
793 }
794 #[doc = "This field powers down the 24M crystal oscillator if set true."]
795 pub mod XTAL_24M_PWD {
796 pub const offset: u32 = 30;
797 pub const mask: u32 = 0x01 << offset;
798 pub mod R {}
799 pub mod W {}
800 pub mod RW {}
801 }
802 #[doc = "Predivider for the source clock of the PLL's. Not related to oscillator."]
803 pub mod VID_PLL_PREDIV {
804 pub const offset: u32 = 31;
805 pub const mask: u32 = 0x01 << offset;
806 pub mod R {}
807 pub mod W {}
808 pub mod RW {
809 #[doc = "Divide by 1"]
810 pub const VID_PLL_PREDIV_0: u32 = 0;
811 #[doc = "Divide by 2"]
812 pub const VID_PLL_PREDIV_1: u32 = 0x01;
813 }
814 }
815}
816#[doc = "XTAL OSC (LP) Control Register"]
817pub mod LOWPWR_CTRL {
818 #[doc = "RC Osc. enable control."]
819 pub mod RC_OSC_EN {
820 pub const offset: u32 = 0;
821 pub const mask: u32 = 0x01 << offset;
822 pub mod R {}
823 pub mod W {}
824 pub mod RW {
825 #[doc = "Use XTAL OSC to source the 24MHz clock"]
826 pub const RC_OSC_EN_0: u32 = 0;
827 #[doc = "Use RC OSC"]
828 pub const RC_OSC_EN_1: u32 = 0x01;
829 }
830 }
831 #[doc = "Select the source for the 24MHz clock."]
832 pub mod OSC_SEL {
833 pub const offset: u32 = 4;
834 pub const mask: u32 = 0x01 << offset;
835 pub mod R {}
836 pub mod W {}
837 pub mod RW {
838 #[doc = "XTAL OSC"]
839 pub const OSC_SEL_0: u32 = 0;
840 #[doc = "RC OSC"]
841 pub const OSC_SEL_1: u32 = 0x01;
842 }
843 }
844 #[doc = "Bandgap select. Not related to oscillator."]
845 pub mod LPBG_SEL {
846 pub const offset: u32 = 5;
847 pub const mask: u32 = 0x01 << offset;
848 pub mod R {}
849 pub mod W {}
850 pub mod RW {
851 #[doc = "Normal power bandgap"]
852 pub const LPBG_SEL_0: u32 = 0;
853 #[doc = "Low power bandgap"]
854 pub const LPBG_SEL_1: u32 = 0x01;
855 }
856 }
857 #[doc = "Low power bandgap test bit. Not related to oscillator."]
858 pub mod LPBG_TEST {
859 pub const offset: u32 = 6;
860 pub const mask: u32 = 0x01 << offset;
861 pub mod R {}
862 pub mod W {}
863 pub mod RW {}
864 }
865 #[doc = "Low power reftop ibias disable. Not related to oscillator."]
866 pub mod REFTOP_IBIAS_OFF {
867 pub const offset: u32 = 7;
868 pub const mask: u32 = 0x01 << offset;
869 pub mod R {}
870 pub mod W {}
871 pub mod RW {}
872 }
873 #[doc = "L1 power gate control. Used as software override. Not related to oscillator."]
874 pub mod L1_PWRGATE {
875 pub const offset: u32 = 8;
876 pub const mask: u32 = 0x01 << offset;
877 pub mod R {}
878 pub mod W {}
879 pub mod RW {}
880 }
881 #[doc = "L2 power gate control. Used as software override. Not related to oscillator."]
882 pub mod L2_PWRGATE {
883 pub const offset: u32 = 9;
884 pub const mask: u32 = 0x01 << offset;
885 pub mod R {}
886 pub mod W {}
887 pub mod RW {}
888 }
889 #[doc = "CPU power gate control. Used as software override. Test purpose only Not related to oscillator."]
890 pub mod CPU_PWRGATE {
891 pub const offset: u32 = 10;
892 pub const mask: u32 = 0x01 << offset;
893 pub mod R {}
894 pub mod W {}
895 pub mod RW {}
896 }
897 #[doc = "Display logic power gate control. Used as software override. Not related to oscillator."]
898 pub mod DISPLAY_PWRGATE {
899 pub const offset: u32 = 11;
900 pub const mask: u32 = 0x01 << offset;
901 pub mod R {}
902 pub mod W {}
903 pub mod RW {}
904 }
905 #[doc = "For debug purposes only"]
906 pub mod RCOSC_CG_OVERRIDE {
907 pub const offset: u32 = 13;
908 pub const mask: u32 = 0x01 << offset;
909 pub mod R {}
910 pub mod W {}
911 pub mod RW {}
912 }
913 #[doc = "Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use"]
914 pub mod XTALOSC_PWRUP_DELAY {
915 pub const offset: u32 = 14;
916 pub const mask: u32 = 0x03 << offset;
917 pub mod R {}
918 pub mod W {}
919 pub mod RW {
920 #[doc = "0.25ms"]
921 pub const XTALOSC_PWRUP_DELAY_0: u32 = 0;
922 #[doc = "0.5ms"]
923 pub const XTALOSC_PWRUP_DELAY_1: u32 = 0x01;
924 #[doc = "1ms"]
925 pub const XTALOSC_PWRUP_DELAY_2: u32 = 0x02;
926 #[doc = "2ms"]
927 pub const XTALOSC_PWRUP_DELAY_3: u32 = 0x03;
928 }
929 }
930 #[doc = "Status of the 24MHz xtal oscillator."]
931 pub mod XTALOSC_PWRUP_STAT {
932 pub const offset: u32 = 16;
933 pub const mask: u32 = 0x01 << offset;
934 pub mod R {}
935 pub mod W {}
936 pub mod RW {
937 #[doc = "Not stable"]
938 pub const XTALOSC_PWRUP_STAT_0: u32 = 0;
939 #[doc = "Stable and ready to use"]
940 pub const XTALOSC_PWRUP_STAT_1: u32 = 0x01;
941 }
942 }
943 #[doc = "Display power gate control. Used as software mask. Set to zero to force ungated."]
944 pub mod MIX_PWRGATE {
945 pub const offset: u32 = 17;
946 pub const mask: u32 = 0x01 << offset;
947 pub mod R {}
948 pub mod W {}
949 pub mod RW {}
950 }
951 #[doc = "GPU power gate control. Used as software mask. Set to zero to force ungated."]
952 pub mod GPU_PWRGATE {
953 pub const offset: u32 = 18;
954 pub const mask: u32 = 0x01 << offset;
955 pub mod R {}
956 pub mod W {}
957 pub mod RW {}
958 }
959}
960#[doc = "XTAL OSC (LP) Control Register"]
961pub mod LOWPWR_CTRL_SET {
962 #[doc = "RC Osc. enable control."]
963 pub mod RC_OSC_EN {
964 pub const offset: u32 = 0;
965 pub const mask: u32 = 0x01 << offset;
966 pub mod R {}
967 pub mod W {}
968 pub mod RW {
969 #[doc = "Use XTAL OSC to source the 24MHz clock"]
970 pub const RC_OSC_EN_0: u32 = 0;
971 #[doc = "Use RC OSC"]
972 pub const RC_OSC_EN_1: u32 = 0x01;
973 }
974 }
975 #[doc = "Select the source for the 24MHz clock."]
976 pub mod OSC_SEL {
977 pub const offset: u32 = 4;
978 pub const mask: u32 = 0x01 << offset;
979 pub mod R {}
980 pub mod W {}
981 pub mod RW {
982 #[doc = "XTAL OSC"]
983 pub const OSC_SEL_0: u32 = 0;
984 #[doc = "RC OSC"]
985 pub const OSC_SEL_1: u32 = 0x01;
986 }
987 }
988 #[doc = "Bandgap select. Not related to oscillator."]
989 pub mod LPBG_SEL {
990 pub const offset: u32 = 5;
991 pub const mask: u32 = 0x01 << offset;
992 pub mod R {}
993 pub mod W {}
994 pub mod RW {
995 #[doc = "Normal power bandgap"]
996 pub const LPBG_SEL_0: u32 = 0;
997 #[doc = "Low power bandgap"]
998 pub const LPBG_SEL_1: u32 = 0x01;
999 }
1000 }
1001 #[doc = "Low power bandgap test bit. Not related to oscillator."]
1002 pub mod LPBG_TEST {
1003 pub const offset: u32 = 6;
1004 pub const mask: u32 = 0x01 << offset;
1005 pub mod R {}
1006 pub mod W {}
1007 pub mod RW {}
1008 }
1009 #[doc = "Low power reftop ibias disable. Not related to oscillator."]
1010 pub mod REFTOP_IBIAS_OFF {
1011 pub const offset: u32 = 7;
1012 pub const mask: u32 = 0x01 << offset;
1013 pub mod R {}
1014 pub mod W {}
1015 pub mod RW {}
1016 }
1017 #[doc = "L1 power gate control. Used as software override. Not related to oscillator."]
1018 pub mod L1_PWRGATE {
1019 pub const offset: u32 = 8;
1020 pub const mask: u32 = 0x01 << offset;
1021 pub mod R {}
1022 pub mod W {}
1023 pub mod RW {}
1024 }
1025 #[doc = "L2 power gate control. Used as software override. Not related to oscillator."]
1026 pub mod L2_PWRGATE {
1027 pub const offset: u32 = 9;
1028 pub const mask: u32 = 0x01 << offset;
1029 pub mod R {}
1030 pub mod W {}
1031 pub mod RW {}
1032 }
1033 #[doc = "CPU power gate control. Used as software override. Test purpose only Not related to oscillator."]
1034 pub mod CPU_PWRGATE {
1035 pub const offset: u32 = 10;
1036 pub const mask: u32 = 0x01 << offset;
1037 pub mod R {}
1038 pub mod W {}
1039 pub mod RW {}
1040 }
1041 #[doc = "Display logic power gate control. Used as software override. Not related to oscillator."]
1042 pub mod DISPLAY_PWRGATE {
1043 pub const offset: u32 = 11;
1044 pub const mask: u32 = 0x01 << offset;
1045 pub mod R {}
1046 pub mod W {}
1047 pub mod RW {}
1048 }
1049 #[doc = "For debug purposes only"]
1050 pub mod RCOSC_CG_OVERRIDE {
1051 pub const offset: u32 = 13;
1052 pub const mask: u32 = 0x01 << offset;
1053 pub mod R {}
1054 pub mod W {}
1055 pub mod RW {}
1056 }
1057 #[doc = "Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use"]
1058 pub mod XTALOSC_PWRUP_DELAY {
1059 pub const offset: u32 = 14;
1060 pub const mask: u32 = 0x03 << offset;
1061 pub mod R {}
1062 pub mod W {}
1063 pub mod RW {
1064 #[doc = "0.25ms"]
1065 pub const XTALOSC_PWRUP_DELAY_0: u32 = 0;
1066 #[doc = "0.5ms"]
1067 pub const XTALOSC_PWRUP_DELAY_1: u32 = 0x01;
1068 #[doc = "1ms"]
1069 pub const XTALOSC_PWRUP_DELAY_2: u32 = 0x02;
1070 #[doc = "2ms"]
1071 pub const XTALOSC_PWRUP_DELAY_3: u32 = 0x03;
1072 }
1073 }
1074 #[doc = "Status of the 24MHz xtal oscillator."]
1075 pub mod XTALOSC_PWRUP_STAT {
1076 pub const offset: u32 = 16;
1077 pub const mask: u32 = 0x01 << offset;
1078 pub mod R {}
1079 pub mod W {}
1080 pub mod RW {
1081 #[doc = "Not stable"]
1082 pub const XTALOSC_PWRUP_STAT_0: u32 = 0;
1083 #[doc = "Stable and ready to use"]
1084 pub const XTALOSC_PWRUP_STAT_1: u32 = 0x01;
1085 }
1086 }
1087 #[doc = "Display power gate control. Used as software mask. Set to zero to force ungated."]
1088 pub mod MIX_PWRGATE {
1089 pub const offset: u32 = 17;
1090 pub const mask: u32 = 0x01 << offset;
1091 pub mod R {}
1092 pub mod W {}
1093 pub mod RW {}
1094 }
1095 #[doc = "GPU power gate control. Used as software mask. Set to zero to force ungated."]
1096 pub mod GPU_PWRGATE {
1097 pub const offset: u32 = 18;
1098 pub const mask: u32 = 0x01 << offset;
1099 pub mod R {}
1100 pub mod W {}
1101 pub mod RW {}
1102 }
1103}
1104#[doc = "XTAL OSC (LP) Control Register"]
1105pub mod LOWPWR_CTRL_CLR {
1106 #[doc = "RC Osc. enable control."]
1107 pub mod RC_OSC_EN {
1108 pub const offset: u32 = 0;
1109 pub const mask: u32 = 0x01 << offset;
1110 pub mod R {}
1111 pub mod W {}
1112 pub mod RW {
1113 #[doc = "Use XTAL OSC to source the 24MHz clock"]
1114 pub const RC_OSC_EN_0: u32 = 0;
1115 #[doc = "Use RC OSC"]
1116 pub const RC_OSC_EN_1: u32 = 0x01;
1117 }
1118 }
1119 #[doc = "Select the source for the 24MHz clock."]
1120 pub mod OSC_SEL {
1121 pub const offset: u32 = 4;
1122 pub const mask: u32 = 0x01 << offset;
1123 pub mod R {}
1124 pub mod W {}
1125 pub mod RW {
1126 #[doc = "XTAL OSC"]
1127 pub const OSC_SEL_0: u32 = 0;
1128 #[doc = "RC OSC"]
1129 pub const OSC_SEL_1: u32 = 0x01;
1130 }
1131 }
1132 #[doc = "Bandgap select. Not related to oscillator."]
1133 pub mod LPBG_SEL {
1134 pub const offset: u32 = 5;
1135 pub const mask: u32 = 0x01 << offset;
1136 pub mod R {}
1137 pub mod W {}
1138 pub mod RW {
1139 #[doc = "Normal power bandgap"]
1140 pub const LPBG_SEL_0: u32 = 0;
1141 #[doc = "Low power bandgap"]
1142 pub const LPBG_SEL_1: u32 = 0x01;
1143 }
1144 }
1145 #[doc = "Low power bandgap test bit. Not related to oscillator."]
1146 pub mod LPBG_TEST {
1147 pub const offset: u32 = 6;
1148 pub const mask: u32 = 0x01 << offset;
1149 pub mod R {}
1150 pub mod W {}
1151 pub mod RW {}
1152 }
1153 #[doc = "Low power reftop ibias disable. Not related to oscillator."]
1154 pub mod REFTOP_IBIAS_OFF {
1155 pub const offset: u32 = 7;
1156 pub const mask: u32 = 0x01 << offset;
1157 pub mod R {}
1158 pub mod W {}
1159 pub mod RW {}
1160 }
1161 #[doc = "L1 power gate control. Used as software override. Not related to oscillator."]
1162 pub mod L1_PWRGATE {
1163 pub const offset: u32 = 8;
1164 pub const mask: u32 = 0x01 << offset;
1165 pub mod R {}
1166 pub mod W {}
1167 pub mod RW {}
1168 }
1169 #[doc = "L2 power gate control. Used as software override. Not related to oscillator."]
1170 pub mod L2_PWRGATE {
1171 pub const offset: u32 = 9;
1172 pub const mask: u32 = 0x01 << offset;
1173 pub mod R {}
1174 pub mod W {}
1175 pub mod RW {}
1176 }
1177 #[doc = "CPU power gate control. Used as software override. Test purpose only Not related to oscillator."]
1178 pub mod CPU_PWRGATE {
1179 pub const offset: u32 = 10;
1180 pub const mask: u32 = 0x01 << offset;
1181 pub mod R {}
1182 pub mod W {}
1183 pub mod RW {}
1184 }
1185 #[doc = "Display logic power gate control. Used as software override. Not related to oscillator."]
1186 pub mod DISPLAY_PWRGATE {
1187 pub const offset: u32 = 11;
1188 pub const mask: u32 = 0x01 << offset;
1189 pub mod R {}
1190 pub mod W {}
1191 pub mod RW {}
1192 }
1193 #[doc = "For debug purposes only"]
1194 pub mod RCOSC_CG_OVERRIDE {
1195 pub const offset: u32 = 13;
1196 pub const mask: u32 = 0x01 << offset;
1197 pub mod R {}
1198 pub mod W {}
1199 pub mod RW {}
1200 }
1201 #[doc = "Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use"]
1202 pub mod XTALOSC_PWRUP_DELAY {
1203 pub const offset: u32 = 14;
1204 pub const mask: u32 = 0x03 << offset;
1205 pub mod R {}
1206 pub mod W {}
1207 pub mod RW {
1208 #[doc = "0.25ms"]
1209 pub const XTALOSC_PWRUP_DELAY_0: u32 = 0;
1210 #[doc = "0.5ms"]
1211 pub const XTALOSC_PWRUP_DELAY_1: u32 = 0x01;
1212 #[doc = "1ms"]
1213 pub const XTALOSC_PWRUP_DELAY_2: u32 = 0x02;
1214 #[doc = "2ms"]
1215 pub const XTALOSC_PWRUP_DELAY_3: u32 = 0x03;
1216 }
1217 }
1218 #[doc = "Status of the 24MHz xtal oscillator."]
1219 pub mod XTALOSC_PWRUP_STAT {
1220 pub const offset: u32 = 16;
1221 pub const mask: u32 = 0x01 << offset;
1222 pub mod R {}
1223 pub mod W {}
1224 pub mod RW {
1225 #[doc = "Not stable"]
1226 pub const XTALOSC_PWRUP_STAT_0: u32 = 0;
1227 #[doc = "Stable and ready to use"]
1228 pub const XTALOSC_PWRUP_STAT_1: u32 = 0x01;
1229 }
1230 }
1231 #[doc = "Display power gate control. Used as software mask. Set to zero to force ungated."]
1232 pub mod MIX_PWRGATE {
1233 pub const offset: u32 = 17;
1234 pub const mask: u32 = 0x01 << offset;
1235 pub mod R {}
1236 pub mod W {}
1237 pub mod RW {}
1238 }
1239 #[doc = "GPU power gate control. Used as software mask. Set to zero to force ungated."]
1240 pub mod GPU_PWRGATE {
1241 pub const offset: u32 = 18;
1242 pub const mask: u32 = 0x01 << offset;
1243 pub mod R {}
1244 pub mod W {}
1245 pub mod RW {}
1246 }
1247}
1248#[doc = "XTAL OSC (LP) Control Register"]
1249pub mod LOWPWR_CTRL_TOG {
1250 #[doc = "RC Osc. enable control."]
1251 pub mod RC_OSC_EN {
1252 pub const offset: u32 = 0;
1253 pub const mask: u32 = 0x01 << offset;
1254 pub mod R {}
1255 pub mod W {}
1256 pub mod RW {
1257 #[doc = "Use XTAL OSC to source the 24MHz clock"]
1258 pub const RC_OSC_EN_0: u32 = 0;
1259 #[doc = "Use RC OSC"]
1260 pub const RC_OSC_EN_1: u32 = 0x01;
1261 }
1262 }
1263 #[doc = "Select the source for the 24MHz clock."]
1264 pub mod OSC_SEL {
1265 pub const offset: u32 = 4;
1266 pub const mask: u32 = 0x01 << offset;
1267 pub mod R {}
1268 pub mod W {}
1269 pub mod RW {
1270 #[doc = "XTAL OSC"]
1271 pub const OSC_SEL_0: u32 = 0;
1272 #[doc = "RC OSC"]
1273 pub const OSC_SEL_1: u32 = 0x01;
1274 }
1275 }
1276 #[doc = "Bandgap select. Not related to oscillator."]
1277 pub mod LPBG_SEL {
1278 pub const offset: u32 = 5;
1279 pub const mask: u32 = 0x01 << offset;
1280 pub mod R {}
1281 pub mod W {}
1282 pub mod RW {
1283 #[doc = "Normal power bandgap"]
1284 pub const LPBG_SEL_0: u32 = 0;
1285 #[doc = "Low power bandgap"]
1286 pub const LPBG_SEL_1: u32 = 0x01;
1287 }
1288 }
1289 #[doc = "Low power bandgap test bit. Not related to oscillator."]
1290 pub mod LPBG_TEST {
1291 pub const offset: u32 = 6;
1292 pub const mask: u32 = 0x01 << offset;
1293 pub mod R {}
1294 pub mod W {}
1295 pub mod RW {}
1296 }
1297 #[doc = "Low power reftop ibias disable. Not related to oscillator."]
1298 pub mod REFTOP_IBIAS_OFF {
1299 pub const offset: u32 = 7;
1300 pub const mask: u32 = 0x01 << offset;
1301 pub mod R {}
1302 pub mod W {}
1303 pub mod RW {}
1304 }
1305 #[doc = "L1 power gate control. Used as software override. Not related to oscillator."]
1306 pub mod L1_PWRGATE {
1307 pub const offset: u32 = 8;
1308 pub const mask: u32 = 0x01 << offset;
1309 pub mod R {}
1310 pub mod W {}
1311 pub mod RW {}
1312 }
1313 #[doc = "L2 power gate control. Used as software override. Not related to oscillator."]
1314 pub mod L2_PWRGATE {
1315 pub const offset: u32 = 9;
1316 pub const mask: u32 = 0x01 << offset;
1317 pub mod R {}
1318 pub mod W {}
1319 pub mod RW {}
1320 }
1321 #[doc = "CPU power gate control. Used as software override. Test purpose only Not related to oscillator."]
1322 pub mod CPU_PWRGATE {
1323 pub const offset: u32 = 10;
1324 pub const mask: u32 = 0x01 << offset;
1325 pub mod R {}
1326 pub mod W {}
1327 pub mod RW {}
1328 }
1329 #[doc = "Display logic power gate control. Used as software override. Not related to oscillator."]
1330 pub mod DISPLAY_PWRGATE {
1331 pub const offset: u32 = 11;
1332 pub const mask: u32 = 0x01 << offset;
1333 pub mod R {}
1334 pub mod W {}
1335 pub mod RW {}
1336 }
1337 #[doc = "For debug purposes only"]
1338 pub mod RCOSC_CG_OVERRIDE {
1339 pub const offset: u32 = 13;
1340 pub const mask: u32 = 0x01 << offset;
1341 pub mod R {}
1342 pub mod W {}
1343 pub mod RW {}
1344 }
1345 #[doc = "Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use"]
1346 pub mod XTALOSC_PWRUP_DELAY {
1347 pub const offset: u32 = 14;
1348 pub const mask: u32 = 0x03 << offset;
1349 pub mod R {}
1350 pub mod W {}
1351 pub mod RW {
1352 #[doc = "0.25ms"]
1353 pub const XTALOSC_PWRUP_DELAY_0: u32 = 0;
1354 #[doc = "0.5ms"]
1355 pub const XTALOSC_PWRUP_DELAY_1: u32 = 0x01;
1356 #[doc = "1ms"]
1357 pub const XTALOSC_PWRUP_DELAY_2: u32 = 0x02;
1358 #[doc = "2ms"]
1359 pub const XTALOSC_PWRUP_DELAY_3: u32 = 0x03;
1360 }
1361 }
1362 #[doc = "Status of the 24MHz xtal oscillator."]
1363 pub mod XTALOSC_PWRUP_STAT {
1364 pub const offset: u32 = 16;
1365 pub const mask: u32 = 0x01 << offset;
1366 pub mod R {}
1367 pub mod W {}
1368 pub mod RW {
1369 #[doc = "Not stable"]
1370 pub const XTALOSC_PWRUP_STAT_0: u32 = 0;
1371 #[doc = "Stable and ready to use"]
1372 pub const XTALOSC_PWRUP_STAT_1: u32 = 0x01;
1373 }
1374 }
1375 #[doc = "Display power gate control. Used as software mask. Set to zero to force ungated."]
1376 pub mod MIX_PWRGATE {
1377 pub const offset: u32 = 17;
1378 pub const mask: u32 = 0x01 << offset;
1379 pub mod R {}
1380 pub mod W {}
1381 pub mod RW {}
1382 }
1383 #[doc = "GPU power gate control. Used as software mask. Set to zero to force ungated."]
1384 pub mod GPU_PWRGATE {
1385 pub const offset: u32 = 18;
1386 pub const mask: u32 = 0x01 << offset;
1387 pub mod R {}
1388 pub mod W {}
1389 pub mod RW {}
1390 }
1391}
1392#[doc = "XTAL OSC Configuration 0 Register"]
1393pub mod OSC_CONFIG0 {
1394 #[doc = "Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset."]
1395 pub mod START {
1396 pub const offset: u32 = 0;
1397 pub const mask: u32 = 0x01 << offset;
1398 pub mod R {}
1399 pub mod W {}
1400 pub mod RW {}
1401 }
1402 #[doc = "Enables the tuning logic to calculate new RC tuning values"]
1403 pub mod ENABLE {
1404 pub const offset: u32 = 1;
1405 pub const mask: u32 = 0x01 << offset;
1406 pub mod R {}
1407 pub mod W {}
1408 pub mod RW {}
1409 }
1410 #[doc = "Bypasses any calculated RC tuning value and uses the programmed register value."]
1411 pub mod BYPASS {
1412 pub const offset: u32 = 2;
1413 pub const mask: u32 = 0x01 << offset;
1414 pub mod R {}
1415 pub mod W {}
1416 pub mod RW {}
1417 }
1418 #[doc = "Invert the stepping of the calculated RC tuning value."]
1419 pub mod INVERT {
1420 pub const offset: u32 = 3;
1421 pub const mask: u32 = 0x01 << offset;
1422 pub mod R {}
1423 pub mod W {}
1424 pub mod RW {}
1425 }
1426 #[doc = "RC osc. tuning values."]
1427 pub mod RC_OSC_PROG {
1428 pub const offset: u32 = 4;
1429 pub const mask: u32 = 0xff << offset;
1430 pub mod R {}
1431 pub mod W {}
1432 pub mod RW {}
1433 }
1434 #[doc = "Positive hysteresis value"]
1435 pub mod HYST_PLUS {
1436 pub const offset: u32 = 12;
1437 pub const mask: u32 = 0x0f << offset;
1438 pub mod R {}
1439 pub mod W {}
1440 pub mod RW {}
1441 }
1442 #[doc = "Negative hysteresis value"]
1443 pub mod HYST_MINUS {
1444 pub const offset: u32 = 16;
1445 pub const mask: u32 = 0x0f << offset;
1446 pub mod R {}
1447 pub mod W {}
1448 pub mod RW {}
1449 }
1450 #[doc = "The current tuning value in use."]
1451 pub mod RC_OSC_PROG_CUR {
1452 pub const offset: u32 = 24;
1453 pub const mask: u32 = 0xff << offset;
1454 pub mod R {}
1455 pub mod W {}
1456 pub mod RW {}
1457 }
1458}
1459#[doc = "XTAL OSC Configuration 0 Register"]
1460pub mod OSC_CONFIG0_SET {
1461 #[doc = "Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset."]
1462 pub mod START {
1463 pub const offset: u32 = 0;
1464 pub const mask: u32 = 0x01 << offset;
1465 pub mod R {}
1466 pub mod W {}
1467 pub mod RW {}
1468 }
1469 #[doc = "Enables the tuning logic to calculate new RC tuning values"]
1470 pub mod ENABLE {
1471 pub const offset: u32 = 1;
1472 pub const mask: u32 = 0x01 << offset;
1473 pub mod R {}
1474 pub mod W {}
1475 pub mod RW {}
1476 }
1477 #[doc = "Bypasses any calculated RC tuning value and uses the programmed register value."]
1478 pub mod BYPASS {
1479 pub const offset: u32 = 2;
1480 pub const mask: u32 = 0x01 << offset;
1481 pub mod R {}
1482 pub mod W {}
1483 pub mod RW {}
1484 }
1485 #[doc = "Invert the stepping of the calculated RC tuning value."]
1486 pub mod INVERT {
1487 pub const offset: u32 = 3;
1488 pub const mask: u32 = 0x01 << offset;
1489 pub mod R {}
1490 pub mod W {}
1491 pub mod RW {}
1492 }
1493 #[doc = "RC osc. tuning values."]
1494 pub mod RC_OSC_PROG {
1495 pub const offset: u32 = 4;
1496 pub const mask: u32 = 0xff << offset;
1497 pub mod R {}
1498 pub mod W {}
1499 pub mod RW {}
1500 }
1501 #[doc = "Positive hysteresis value"]
1502 pub mod HYST_PLUS {
1503 pub const offset: u32 = 12;
1504 pub const mask: u32 = 0x0f << offset;
1505 pub mod R {}
1506 pub mod W {}
1507 pub mod RW {}
1508 }
1509 #[doc = "Negative hysteresis value"]
1510 pub mod HYST_MINUS {
1511 pub const offset: u32 = 16;
1512 pub const mask: u32 = 0x0f << offset;
1513 pub mod R {}
1514 pub mod W {}
1515 pub mod RW {}
1516 }
1517 #[doc = "The current tuning value in use."]
1518 pub mod RC_OSC_PROG_CUR {
1519 pub const offset: u32 = 24;
1520 pub const mask: u32 = 0xff << offset;
1521 pub mod R {}
1522 pub mod W {}
1523 pub mod RW {}
1524 }
1525}
1526#[doc = "XTAL OSC Configuration 0 Register"]
1527pub mod OSC_CONFIG0_CLR {
1528 #[doc = "Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset."]
1529 pub mod START {
1530 pub const offset: u32 = 0;
1531 pub const mask: u32 = 0x01 << offset;
1532 pub mod R {}
1533 pub mod W {}
1534 pub mod RW {}
1535 }
1536 #[doc = "Enables the tuning logic to calculate new RC tuning values"]
1537 pub mod ENABLE {
1538 pub const offset: u32 = 1;
1539 pub const mask: u32 = 0x01 << offset;
1540 pub mod R {}
1541 pub mod W {}
1542 pub mod RW {}
1543 }
1544 #[doc = "Bypasses any calculated RC tuning value and uses the programmed register value."]
1545 pub mod BYPASS {
1546 pub const offset: u32 = 2;
1547 pub const mask: u32 = 0x01 << offset;
1548 pub mod R {}
1549 pub mod W {}
1550 pub mod RW {}
1551 }
1552 #[doc = "Invert the stepping of the calculated RC tuning value."]
1553 pub mod INVERT {
1554 pub const offset: u32 = 3;
1555 pub const mask: u32 = 0x01 << offset;
1556 pub mod R {}
1557 pub mod W {}
1558 pub mod RW {}
1559 }
1560 #[doc = "RC osc. tuning values."]
1561 pub mod RC_OSC_PROG {
1562 pub const offset: u32 = 4;
1563 pub const mask: u32 = 0xff << offset;
1564 pub mod R {}
1565 pub mod W {}
1566 pub mod RW {}
1567 }
1568 #[doc = "Positive hysteresis value"]
1569 pub mod HYST_PLUS {
1570 pub const offset: u32 = 12;
1571 pub const mask: u32 = 0x0f << offset;
1572 pub mod R {}
1573 pub mod W {}
1574 pub mod RW {}
1575 }
1576 #[doc = "Negative hysteresis value"]
1577 pub mod HYST_MINUS {
1578 pub const offset: u32 = 16;
1579 pub const mask: u32 = 0x0f << offset;
1580 pub mod R {}
1581 pub mod W {}
1582 pub mod RW {}
1583 }
1584 #[doc = "The current tuning value in use."]
1585 pub mod RC_OSC_PROG_CUR {
1586 pub const offset: u32 = 24;
1587 pub const mask: u32 = 0xff << offset;
1588 pub mod R {}
1589 pub mod W {}
1590 pub mod RW {}
1591 }
1592}
1593#[doc = "XTAL OSC Configuration 0 Register"]
1594pub mod OSC_CONFIG0_TOG {
1595 #[doc = "Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset."]
1596 pub mod START {
1597 pub const offset: u32 = 0;
1598 pub const mask: u32 = 0x01 << offset;
1599 pub mod R {}
1600 pub mod W {}
1601 pub mod RW {}
1602 }
1603 #[doc = "Enables the tuning logic to calculate new RC tuning values"]
1604 pub mod ENABLE {
1605 pub const offset: u32 = 1;
1606 pub const mask: u32 = 0x01 << offset;
1607 pub mod R {}
1608 pub mod W {}
1609 pub mod RW {}
1610 }
1611 #[doc = "Bypasses any calculated RC tuning value and uses the programmed register value."]
1612 pub mod BYPASS {
1613 pub const offset: u32 = 2;
1614 pub const mask: u32 = 0x01 << offset;
1615 pub mod R {}
1616 pub mod W {}
1617 pub mod RW {}
1618 }
1619 #[doc = "Invert the stepping of the calculated RC tuning value."]
1620 pub mod INVERT {
1621 pub const offset: u32 = 3;
1622 pub const mask: u32 = 0x01 << offset;
1623 pub mod R {}
1624 pub mod W {}
1625 pub mod RW {}
1626 }
1627 #[doc = "RC osc. tuning values."]
1628 pub mod RC_OSC_PROG {
1629 pub const offset: u32 = 4;
1630 pub const mask: u32 = 0xff << offset;
1631 pub mod R {}
1632 pub mod W {}
1633 pub mod RW {}
1634 }
1635 #[doc = "Positive hysteresis value"]
1636 pub mod HYST_PLUS {
1637 pub const offset: u32 = 12;
1638 pub const mask: u32 = 0x0f << offset;
1639 pub mod R {}
1640 pub mod W {}
1641 pub mod RW {}
1642 }
1643 #[doc = "Negative hysteresis value"]
1644 pub mod HYST_MINUS {
1645 pub const offset: u32 = 16;
1646 pub const mask: u32 = 0x0f << offset;
1647 pub mod R {}
1648 pub mod W {}
1649 pub mod RW {}
1650 }
1651 #[doc = "The current tuning value in use."]
1652 pub mod RC_OSC_PROG_CUR {
1653 pub const offset: u32 = 24;
1654 pub const mask: u32 = 0xff << offset;
1655 pub mod R {}
1656 pub mod W {}
1657 pub mod RW {}
1658 }
1659}
1660#[doc = "XTAL OSC Configuration 1 Register"]
1661pub mod OSC_CONFIG1 {
1662 #[doc = "The target count used to tune the RC OSC frequency"]
1663 pub mod COUNT_RC_TRG {
1664 pub const offset: u32 = 0;
1665 pub const mask: u32 = 0x0fff << offset;
1666 pub mod R {}
1667 pub mod W {}
1668 pub mod RW {}
1669 }
1670 #[doc = "The current tuning value in use."]
1671 pub mod COUNT_RC_CUR {
1672 pub const offset: u32 = 20;
1673 pub const mask: u32 = 0x0fff << offset;
1674 pub mod R {}
1675 pub mod W {}
1676 pub mod RW {}
1677 }
1678}
1679#[doc = "XTAL OSC Configuration 1 Register"]
1680pub mod OSC_CONFIG1_SET {
1681 #[doc = "The target count used to tune the RC OSC frequency"]
1682 pub mod COUNT_RC_TRG {
1683 pub const offset: u32 = 0;
1684 pub const mask: u32 = 0x0fff << offset;
1685 pub mod R {}
1686 pub mod W {}
1687 pub mod RW {}
1688 }
1689 #[doc = "The current tuning value in use."]
1690 pub mod COUNT_RC_CUR {
1691 pub const offset: u32 = 20;
1692 pub const mask: u32 = 0x0fff << offset;
1693 pub mod R {}
1694 pub mod W {}
1695 pub mod RW {}
1696 }
1697}
1698#[doc = "XTAL OSC Configuration 1 Register"]
1699pub mod OSC_CONFIG1_CLR {
1700 #[doc = "The target count used to tune the RC OSC frequency"]
1701 pub mod COUNT_RC_TRG {
1702 pub const offset: u32 = 0;
1703 pub const mask: u32 = 0x0fff << offset;
1704 pub mod R {}
1705 pub mod W {}
1706 pub mod RW {}
1707 }
1708 #[doc = "The current tuning value in use."]
1709 pub mod COUNT_RC_CUR {
1710 pub const offset: u32 = 20;
1711 pub const mask: u32 = 0x0fff << offset;
1712 pub mod R {}
1713 pub mod W {}
1714 pub mod RW {}
1715 }
1716}
1717#[doc = "XTAL OSC Configuration 1 Register"]
1718pub mod OSC_CONFIG1_TOG {
1719 #[doc = "The target count used to tune the RC OSC frequency"]
1720 pub mod COUNT_RC_TRG {
1721 pub const offset: u32 = 0;
1722 pub const mask: u32 = 0x0fff << offset;
1723 pub mod R {}
1724 pub mod W {}
1725 pub mod RW {}
1726 }
1727 #[doc = "The current tuning value in use."]
1728 pub mod COUNT_RC_CUR {
1729 pub const offset: u32 = 20;
1730 pub const mask: u32 = 0x0fff << offset;
1731 pub mod R {}
1732 pub mod W {}
1733 pub mod RW {}
1734 }
1735}
1736#[doc = "XTAL OSC Configuration 2 Register"]
1737pub mod OSC_CONFIG2 {
1738 #[doc = "The target count used to tune the 1MHz clock frequency"]
1739 pub mod COUNT_1M_TRG {
1740 pub const offset: u32 = 0;
1741 pub const mask: u32 = 0x0fff << offset;
1742 pub mod R {}
1743 pub mod W {}
1744 pub mod RW {}
1745 }
1746 #[doc = "Enable the 1MHz clock output. 0 - disabled; 1 - enabled."]
1747 pub mod ENABLE_1M {
1748 pub const offset: u32 = 16;
1749 pub const mask: u32 = 0x01 << offset;
1750 pub mod R {}
1751 pub mod W {}
1752 pub mod RW {}
1753 }
1754 #[doc = "Mux the corrected or uncorrected 1MHz clock to the output"]
1755 pub mod MUX_1M {
1756 pub const offset: u32 = 17;
1757 pub const mask: u32 = 0x01 << offset;
1758 pub mod R {}
1759 pub mod W {}
1760 pub mod RW {}
1761 }
1762 #[doc = "Flag indicates that the count_1m count wasn't reached within 1 32kHz period"]
1763 pub mod CLK_1M_ERR_FL {
1764 pub const offset: u32 = 31;
1765 pub const mask: u32 = 0x01 << offset;
1766 pub mod R {}
1767 pub mod W {}
1768 pub mod RW {}
1769 }
1770}
1771#[doc = "XTAL OSC Configuration 2 Register"]
1772pub mod OSC_CONFIG2_SET {
1773 #[doc = "The target count used to tune the 1MHz clock frequency"]
1774 pub mod COUNT_1M_TRG {
1775 pub const offset: u32 = 0;
1776 pub const mask: u32 = 0x0fff << offset;
1777 pub mod R {}
1778 pub mod W {}
1779 pub mod RW {}
1780 }
1781 #[doc = "Enable the 1MHz clock output. 0 - disabled; 1 - enabled."]
1782 pub mod ENABLE_1M {
1783 pub const offset: u32 = 16;
1784 pub const mask: u32 = 0x01 << offset;
1785 pub mod R {}
1786 pub mod W {}
1787 pub mod RW {}
1788 }
1789 #[doc = "Mux the corrected or uncorrected 1MHz clock to the output"]
1790 pub mod MUX_1M {
1791 pub const offset: u32 = 17;
1792 pub const mask: u32 = 0x01 << offset;
1793 pub mod R {}
1794 pub mod W {}
1795 pub mod RW {}
1796 }
1797 #[doc = "Flag indicates that the count_1m count wasn't reached within 1 32kHz period"]
1798 pub mod CLK_1M_ERR_FL {
1799 pub const offset: u32 = 31;
1800 pub const mask: u32 = 0x01 << offset;
1801 pub mod R {}
1802 pub mod W {}
1803 pub mod RW {}
1804 }
1805}
1806#[doc = "XTAL OSC Configuration 2 Register"]
1807pub mod OSC_CONFIG2_CLR {
1808 #[doc = "The target count used to tune the 1MHz clock frequency"]
1809 pub mod COUNT_1M_TRG {
1810 pub const offset: u32 = 0;
1811 pub const mask: u32 = 0x0fff << offset;
1812 pub mod R {}
1813 pub mod W {}
1814 pub mod RW {}
1815 }
1816 #[doc = "Enable the 1MHz clock output. 0 - disabled; 1 - enabled."]
1817 pub mod ENABLE_1M {
1818 pub const offset: u32 = 16;
1819 pub const mask: u32 = 0x01 << offset;
1820 pub mod R {}
1821 pub mod W {}
1822 pub mod RW {}
1823 }
1824 #[doc = "Mux the corrected or uncorrected 1MHz clock to the output"]
1825 pub mod MUX_1M {
1826 pub const offset: u32 = 17;
1827 pub const mask: u32 = 0x01 << offset;
1828 pub mod R {}
1829 pub mod W {}
1830 pub mod RW {}
1831 }
1832 #[doc = "Flag indicates that the count_1m count wasn't reached within 1 32kHz period"]
1833 pub mod CLK_1M_ERR_FL {
1834 pub const offset: u32 = 31;
1835 pub const mask: u32 = 0x01 << offset;
1836 pub mod R {}
1837 pub mod W {}
1838 pub mod RW {}
1839 }
1840}
1841#[doc = "XTAL OSC Configuration 2 Register"]
1842pub mod OSC_CONFIG2_TOG {
1843 #[doc = "The target count used to tune the 1MHz clock frequency"]
1844 pub mod COUNT_1M_TRG {
1845 pub const offset: u32 = 0;
1846 pub const mask: u32 = 0x0fff << offset;
1847 pub mod R {}
1848 pub mod W {}
1849 pub mod RW {}
1850 }
1851 #[doc = "Enable the 1MHz clock output. 0 - disabled; 1 - enabled."]
1852 pub mod ENABLE_1M {
1853 pub const offset: u32 = 16;
1854 pub const mask: u32 = 0x01 << offset;
1855 pub mod R {}
1856 pub mod W {}
1857 pub mod RW {}
1858 }
1859 #[doc = "Mux the corrected or uncorrected 1MHz clock to the output"]
1860 pub mod MUX_1M {
1861 pub const offset: u32 = 17;
1862 pub const mask: u32 = 0x01 << offset;
1863 pub mod R {}
1864 pub mod W {}
1865 pub mod RW {}
1866 }
1867 #[doc = "Flag indicates that the count_1m count wasn't reached within 1 32kHz period"]
1868 pub mod CLK_1M_ERR_FL {
1869 pub const offset: u32 = 31;
1870 pub const mask: u32 = 0x01 << offset;
1871 pub mod R {}
1872 pub mod W {}
1873 pub mod RW {}
1874 }
1875}