rp2040_pac/ppb/
aircr.rs

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1#[doc = "Register `AIRCR` reader"]
2pub type R = crate::R<AIRCR_SPEC>;
3#[doc = "Register `AIRCR` writer"]
4pub type W = crate::W<AIRCR_SPEC>;
5#[doc = "Field `VECTCLRACTIVE` reader - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."]
6pub type VECTCLRACTIVE_R = crate::BitReader;
7#[doc = "Field `VECTCLRACTIVE` writer - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."]
8pub type VECTCLRACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SYSRESETREQ` reader - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."]
10pub type SYSRESETREQ_R = crate::BitReader;
11#[doc = "Field `SYSRESETREQ` writer - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."]
12pub type SYSRESETREQ_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ENDIANESS` reader - Data endianness implemented:  
14 0 = Little-endian."]
15pub type ENDIANESS_R = crate::BitReader;
16#[doc = "Field `VECTKEY` reader - Register key:  
17 Reads as Unknown  
18 On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."]
19pub type VECTKEY_R = crate::FieldReader<u16>;
20#[doc = "Field `VECTKEY` writer - Register key:  
21 Reads as Unknown  
22 On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."]
23pub type VECTKEY_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
24impl R {
25    #[doc = "Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."]
26    #[inline(always)]
27    pub fn vectclractive(&self) -> VECTCLRACTIVE_R {
28        VECTCLRACTIVE_R::new(((self.bits >> 1) & 1) != 0)
29    }
30    #[doc = "Bit 2 - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."]
31    #[inline(always)]
32    pub fn sysresetreq(&self) -> SYSRESETREQ_R {
33        SYSRESETREQ_R::new(((self.bits >> 2) & 1) != 0)
34    }
35    #[doc = "Bit 15 - Data endianness implemented:  
36 0 = Little-endian."]
37    #[inline(always)]
38    pub fn endianess(&self) -> ENDIANESS_R {
39        ENDIANESS_R::new(((self.bits >> 15) & 1) != 0)
40    }
41    #[doc = "Bits 16:31 - Register key:  
42 Reads as Unknown  
43 On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."]
44    #[inline(always)]
45    pub fn vectkey(&self) -> VECTKEY_R {
46        VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16)
47    }
48}
49impl W {
50    #[doc = "Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."]
51    #[inline(always)]
52    #[must_use]
53    pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W<AIRCR_SPEC> {
54        VECTCLRACTIVE_W::new(self, 1)
55    }
56    #[doc = "Bit 2 - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."]
57    #[inline(always)]
58    #[must_use]
59    pub fn sysresetreq(&mut self) -> SYSRESETREQ_W<AIRCR_SPEC> {
60        SYSRESETREQ_W::new(self, 2)
61    }
62    #[doc = "Bits 16:31 - Register key:  
63 Reads as Unknown  
64 On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."]
65    #[inline(always)]
66    #[must_use]
67    pub fn vectkey(&mut self) -> VECTKEY_W<AIRCR_SPEC> {
68        VECTKEY_W::new(self, 16)
69    }
70    #[doc = r" Writes raw bits to the register."]
71    #[doc = r""]
72    #[doc = r" # Safety"]
73    #[doc = r""]
74    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
75    #[inline(always)]
76    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
77        self.bits = bits;
78        self
79    }
80}
81#[doc = "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.  
82
83You can [`read`](crate::generic::Reg::read) this register and get [`aircr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aircr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct AIRCR_SPEC;
85impl crate::RegisterSpec for AIRCR_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [`aircr::R`](R) reader structure"]
89impl crate::Readable for AIRCR_SPEC {}
90#[doc = "`write(|w| ..)` method takes [`aircr::W`](W) writer structure"]
91impl crate::Writable for AIRCR_SPEC {
92    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
93    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
94}
95#[doc = "`reset()` method sets AIRCR to value 0"]
96impl crate::Resettable for AIRCR_SPEC {
97    const RESET_VALUE: u32 = 0;
98}
rp2040_pac/ppb/aircr.rs

rp2040_pac/ppb/
aircr.rs
