1#[doc = "Register `IC_DATA_CMD` reader"]
2pub type R = crate::R<IC_DATA_CMD_SPEC>;
3#[doc = "Register `IC_DATA_CMD` writer"]
4pub type W = crate::W<IC_DATA_CMD_SPEC>;
5#[doc = "Field `DAT` reader - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
6
7 Reset value: 0x0"]
8pub type DAT_R = crate::FieldReader;
9#[doc = "Field `DAT` writer - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
10
11 Reset value: 0x0"]
12pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `CMD` reader - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
14
15 When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.
16
17 When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
18
19 Reset value: 0x0"]
20pub type CMD_R = crate::BitReader<CMD_A>;
21#[doc = "This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
22
23 When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.
24
25 When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
26
27 Reset value: 0x0
28
29Value on reset: 0"]
30#[derive(Clone, Copy, Debug, PartialEq, Eq)]
31pub enum CMD_A {
32 #[doc = "0: Master Write Command"]
33 WRITE = 0,
34 #[doc = "1: Master Read Command"]
35 READ = 1,
36}
37impl From<CMD_A> for bool {
38 #[inline(always)]
39 fn from(variant: CMD_A) -> Self {
40 variant as u8 != 0
41 }
42}
43impl CMD_R {
44 #[doc = "Get enumerated values variant"]
45 #[inline(always)]
46 pub const fn variant(&self) -> CMD_A {
47 match self.bits {
48 false => CMD_A::WRITE,
49 true => CMD_A::READ,
50 }
51 }
52 #[doc = "Master Write Command"]
53 #[inline(always)]
54 pub fn is_write(&self) -> bool {
55 *self == CMD_A::WRITE
56 }
57 #[doc = "Master Read Command"]
58 #[inline(always)]
59 pub fn is_read(&self) -> bool {
60 *self == CMD_A::READ
61 }
62}
63#[doc = "Field `CMD` writer - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
64
65 When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.
66
67 When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
68
69 Reset value: 0x0"]
70pub type CMD_W<'a, REG> = crate::BitWriter<'a, REG, CMD_A>;
71impl<'a, REG> CMD_W<'a, REG>
72where
73 REG: crate::Writable + crate::RegisterSpec,
74{
75 #[doc = "Master Write Command"]
76 #[inline(always)]
77 pub fn write(self) -> &'a mut crate::W<REG> {
78 self.variant(CMD_A::WRITE)
79 }
80 #[doc = "Master Read Command"]
81 #[inline(always)]
82 pub fn read(self) -> &'a mut crate::W<REG> {
83 self.variant(CMD_A::READ)
84 }
85}
86#[doc = "Field `STOP` reader - This bit controls whether a STOP is issued after the byte is sent or received.
87
88 - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"]
89pub type STOP_R = crate::BitReader<STOP_A>;
90#[doc = "This bit controls whether a STOP is issued after the byte is sent or received.
91
92 - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0
93
94Value on reset: 0"]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum STOP_A {
97 #[doc = "0: Don't Issue STOP after this command"]
98 DISABLE = 0,
99 #[doc = "1: Issue STOP after this command"]
100 ENABLE = 1,
101}
102impl From<STOP_A> for bool {
103 #[inline(always)]
104 fn from(variant: STOP_A) -> Self {
105 variant as u8 != 0
106 }
107}
108impl STOP_R {
109 #[doc = "Get enumerated values variant"]
110 #[inline(always)]
111 pub const fn variant(&self) -> STOP_A {
112 match self.bits {
113 false => STOP_A::DISABLE,
114 true => STOP_A::ENABLE,
115 }
116 }
117 #[doc = "Don't Issue STOP after this command"]
118 #[inline(always)]
119 pub fn is_disable(&self) -> bool {
120 *self == STOP_A::DISABLE
121 }
122 #[doc = "Issue STOP after this command"]
123 #[inline(always)]
124 pub fn is_enable(&self) -> bool {
125 *self == STOP_A::ENABLE
126 }
127}
128#[doc = "Field `STOP` writer - This bit controls whether a STOP is issued after the byte is sent or received.
129
130 - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"]
131pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG, STOP_A>;
132impl<'a, REG> STOP_W<'a, REG>
133where
134 REG: crate::Writable + crate::RegisterSpec,
135{
136 #[doc = "Don't Issue STOP after this command"]
137 #[inline(always)]
138 pub fn disable(self) -> &'a mut crate::W<REG> {
139 self.variant(STOP_A::DISABLE)
140 }
141 #[doc = "Issue STOP after this command"]
142 #[inline(always)]
143 pub fn enable(self) -> &'a mut crate::W<REG> {
144 self.variant(STOP_A::ENABLE)
145 }
146}
147#[doc = "Field `RESTART` reader - This bit controls whether a RESTART is issued before the byte is sent or received.
148
149 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
150
151 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
152
153 Reset value: 0x0"]
154pub type RESTART_R = crate::BitReader<RESTART_A>;
155#[doc = "This bit controls whether a RESTART is issued before the byte is sent or received.
156
157 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
158
159 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
160
161 Reset value: 0x0
162
163Value on reset: 0"]
164#[derive(Clone, Copy, Debug, PartialEq, Eq)]
165pub enum RESTART_A {
166 #[doc = "0: Don't Issue RESTART before this command"]
167 DISABLE = 0,
168 #[doc = "1: Issue RESTART before this command"]
169 ENABLE = 1,
170}
171impl From<RESTART_A> for bool {
172 #[inline(always)]
173 fn from(variant: RESTART_A) -> Self {
174 variant as u8 != 0
175 }
176}
177impl RESTART_R {
178 #[doc = "Get enumerated values variant"]
179 #[inline(always)]
180 pub const fn variant(&self) -> RESTART_A {
181 match self.bits {
182 false => RESTART_A::DISABLE,
183 true => RESTART_A::ENABLE,
184 }
185 }
186 #[doc = "Don't Issue RESTART before this command"]
187 #[inline(always)]
188 pub fn is_disable(&self) -> bool {
189 *self == RESTART_A::DISABLE
190 }
191 #[doc = "Issue RESTART before this command"]
192 #[inline(always)]
193 pub fn is_enable(&self) -> bool {
194 *self == RESTART_A::ENABLE
195 }
196}
197#[doc = "Field `RESTART` writer - This bit controls whether a RESTART is issued before the byte is sent or received.
198
199 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
200
201 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
202
203 Reset value: 0x0"]
204pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG, RESTART_A>;
205impl<'a, REG> RESTART_W<'a, REG>
206where
207 REG: crate::Writable + crate::RegisterSpec,
208{
209 #[doc = "Don't Issue RESTART before this command"]
210 #[inline(always)]
211 pub fn disable(self) -> &'a mut crate::W<REG> {
212 self.variant(RESTART_A::DISABLE)
213 }
214 #[doc = "Issue RESTART before this command"]
215 #[inline(always)]
216 pub fn enable(self) -> &'a mut crate::W<REG> {
217 self.variant(RESTART_A::ENABLE)
218 }
219}
220#[doc = "Field `FIRST_DATA_BYTE` reader - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
221
222 Reset value : 0x0
223
224 NOTE: In case of APB_DATA_WIDTH=8,
225
226 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.
227
228 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\]
229(offset 0x10) and then perform the second read \\[15:8\\]
230(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).
231
232 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\]
233(offset 0x11) if not interested in FIRST_DATA_BYTE status."]
234pub type FIRST_DATA_BYTE_R = crate::BitReader<FIRST_DATA_BYTE_A>;
235#[doc = "Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
236
237 Reset value : 0x0
238
239 NOTE: In case of APB_DATA_WIDTH=8,
240
241 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.
242
243 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\]
244(offset 0x10) and then perform the second read \\[15:8\\]
245(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).
246
247 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\]
248(offset 0x11) if not interested in FIRST_DATA_BYTE status.
249
250Value on reset: 0"]
251#[derive(Clone, Copy, Debug, PartialEq, Eq)]
252pub enum FIRST_DATA_BYTE_A {
253 #[doc = "0: Sequential data byte received"]
254 INACTIVE = 0,
255 #[doc = "1: Non sequential data byte received"]
256 ACTIVE = 1,
257}
258impl From<FIRST_DATA_BYTE_A> for bool {
259 #[inline(always)]
260 fn from(variant: FIRST_DATA_BYTE_A) -> Self {
261 variant as u8 != 0
262 }
263}
264impl FIRST_DATA_BYTE_R {
265 #[doc = "Get enumerated values variant"]
266 #[inline(always)]
267 pub const fn variant(&self) -> FIRST_DATA_BYTE_A {
268 match self.bits {
269 false => FIRST_DATA_BYTE_A::INACTIVE,
270 true => FIRST_DATA_BYTE_A::ACTIVE,
271 }
272 }
273 #[doc = "Sequential data byte received"]
274 #[inline(always)]
275 pub fn is_inactive(&self) -> bool {
276 *self == FIRST_DATA_BYTE_A::INACTIVE
277 }
278 #[doc = "Non sequential data byte received"]
279 #[inline(always)]
280 pub fn is_active(&self) -> bool {
281 *self == FIRST_DATA_BYTE_A::ACTIVE
282 }
283}
284impl R {
285 #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
286
287 Reset value: 0x0"]
288 #[inline(always)]
289 pub fn dat(&self) -> DAT_R {
290 DAT_R::new((self.bits & 0xff) as u8)
291 }
292 #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
293
294 When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.
295
296 When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
297
298 Reset value: 0x0"]
299 #[inline(always)]
300 pub fn cmd(&self) -> CMD_R {
301 CMD_R::new(((self.bits >> 8) & 1) != 0)
302 }
303 #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received.
304
305 - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"]
306 #[inline(always)]
307 pub fn stop(&self) -> STOP_R {
308 STOP_R::new(((self.bits >> 9) & 1) != 0)
309 }
310 #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received.
311
312 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
313
314 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
315
316 Reset value: 0x0"]
317 #[inline(always)]
318 pub fn restart(&self) -> RESTART_R {
319 RESTART_R::new(((self.bits >> 10) & 1) != 0)
320 }
321 #[doc = "Bit 11 - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
322
323 Reset value : 0x0
324
325 NOTE: In case of APB_DATA_WIDTH=8,
326
327 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.
328
329 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\]
330(offset 0x10) and then perform the second read \\[15:8\\]
331(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).
332
333 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\]
334(offset 0x11) if not interested in FIRST_DATA_BYTE status."]
335 #[inline(always)]
336 pub fn first_data_byte(&self) -> FIRST_DATA_BYTE_R {
337 FIRST_DATA_BYTE_R::new(((self.bits >> 11) & 1) != 0)
338 }
339}
340impl W {
341 #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
342
343 Reset value: 0x0"]
344 #[inline(always)]
345 #[must_use]
346 pub fn dat(&mut self) -> DAT_W<IC_DATA_CMD_SPEC> {
347 DAT_W::new(self, 0)
348 }
349 #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
350
351 When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.
352
353 When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
354
355 Reset value: 0x0"]
356 #[inline(always)]
357 #[must_use]
358 pub fn cmd(&mut self) -> CMD_W<IC_DATA_CMD_SPEC> {
359 CMD_W::new(self, 8)
360 }
361 #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received.
362
363 - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"]
364 #[inline(always)]
365 #[must_use]
366 pub fn stop(&mut self) -> STOP_W<IC_DATA_CMD_SPEC> {
367 STOP_W::new(self, 9)
368 }
369 #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received.
370
371 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
372
373 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
374
375 Reset value: 0x0"]
376 #[inline(always)]
377 #[must_use]
378 pub fn restart(&mut self) -> RESTART_W<IC_DATA_CMD_SPEC> {
379 RESTART_W::new(self, 10)
380 }
381 #[doc = r" Writes raw bits to the register."]
382 #[doc = r""]
383 #[doc = r" # Safety"]
384 #[doc = r""]
385 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
386 #[inline(always)]
387 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
388 self.bits = bits;
389 self
390 }
391}
392#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
393
394 The size of the register changes as follows:
395
396 Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.
397
398You can [`read`](crate::generic::Reg::read) this register and get [`ic_data_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_data_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
399pub struct IC_DATA_CMD_SPEC;
400impl crate::RegisterSpec for IC_DATA_CMD_SPEC {
401 type Ux = u32;
402}
403#[doc = "`read()` method returns [`ic_data_cmd::R`](R) reader structure"]
404impl crate::Readable for IC_DATA_CMD_SPEC {}
405#[doc = "`write(|w| ..)` method takes [`ic_data_cmd::W`](W) writer structure"]
406impl crate::Writable for IC_DATA_CMD_SPEC {
407 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
408 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
409}
410#[doc = "`reset()` method sets IC_DATA_CMD to value 0"]
411impl crate::Resettable for IC_DATA_CMD_SPEC {
412 const RESET_VALUE: u32 = 0;
413}