rp2040_pac/i2c0/
ic_ss_scl_lcnt.rs

Help
1#[doc = "Register `IC_SS_SCL_LCNT` reader"]
2pub type R = crate::R<IC_SS_SCL_LCNT_SPEC>;
3#[doc = "Register `IC_SS_SCL_LCNT` writer"]
4pub type W = crate::W<IC_SS_SCL_LCNT_SPEC>;
5#[doc = "Field `IC_SS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'  
6
7 This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
8register being set to 0. Writes at other times have no effect.  
9
10 The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."]
11pub type IC_SS_SCL_LCNT_R = crate::FieldReader<u16>;
12#[doc = "Field `IC_SS_SCL_LCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'  
13
14 This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
15register being set to 0. Writes at other times have no effect.  
16
17 The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."]
18pub type IC_SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
19impl R {
20    #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'  
21
22 This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
23register being set to 0. Writes at other times have no effect.  
24
25 The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."]
26    #[inline(always)]
27    pub fn ic_ss_scl_lcnt(&self) -> IC_SS_SCL_LCNT_R {
28        IC_SS_SCL_LCNT_R::new((self.bits & 0xffff) as u16)
29    }
30}
31impl W {
32    #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'  
33
34 This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
35register being set to 0. Writes at other times have no effect.  
36
37 The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."]
38    #[inline(always)]
39    #[must_use]
40    pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W<IC_SS_SCL_LCNT_SPEC> {
41        IC_SS_SCL_LCNT_W::new(self, 0)
42    }
43    #[doc = r" Writes raw bits to the register."]
44    #[doc = r""]
45    #[doc = r" # Safety"]
46    #[doc = r""]
47    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
48    #[inline(always)]
49    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
50        self.bits = bits;
51        self
52    }
53}
54#[doc = "Standard Speed I2C Clock SCL Low Count Register  
55
56You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_lcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
57pub struct IC_SS_SCL_LCNT_SPEC;
58impl crate::RegisterSpec for IC_SS_SCL_LCNT_SPEC {
59    type Ux = u32;
60}
61#[doc = "`read()` method returns [`ic_ss_scl_lcnt::R`](R) reader structure"]
62impl crate::Readable for IC_SS_SCL_LCNT_SPEC {}
63#[doc = "`write(|w| ..)` method takes [`ic_ss_scl_lcnt::W`](W) writer structure"]
64impl crate::Writable for IC_SS_SCL_LCNT_SPEC {
65    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
67}
68#[doc = "`reset()` method sets IC_SS_SCL_LCNT to value 0x2f"]
69impl crate::Resettable for IC_SS_SCL_LCNT_SPEC {
70    const RESET_VALUE: u32 = 0x2f;
71}
rp2040_pac/i2c0/ic_ss_scl_lcnt.rs

rp2040_pac/i2c0/
ic_ss_scl_lcnt.rs
