imxrt_ral/blocks/imxrt1011/
ocotp.rs1#[doc = "no description available"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "OTP Controller Control Register"]
5 pub CTRL: crate::RWRegister<u32>,
6 #[doc = "OTP Controller Control Register"]
7 pub CTRL_SET: crate::RWRegister<u32>,
8 #[doc = "OTP Controller Control Register"]
9 pub CTRL_CLR: crate::RWRegister<u32>,
10 #[doc = "OTP Controller Control Register"]
11 pub CTRL_TOG: crate::RWRegister<u32>,
12 #[doc = "OTP Controller Timing Register"]
13 pub TIMING: crate::RWRegister<u32>,
14 _reserved0: [u8; 0x0c],
15 #[doc = "OTP Controller Write Data Register"]
16 pub DATA: crate::RWRegister<u32>,
17 _reserved1: [u8; 0x0c],
18 #[doc = "OTP Controller Write Data Register"]
19 pub READ_CTRL: crate::RWRegister<u32>,
20 _reserved2: [u8; 0x0c],
21 #[doc = "OTP Controller Read Data Register"]
22 pub READ_FUSE_DATA: crate::RWRegister<u32>,
23 _reserved3: [u8; 0x0c],
24 #[doc = "Sticky bit Register"]
25 pub SW_STICKY: crate::RWRegister<u32>,
26 _reserved4: [u8; 0x0c],
27 #[doc = "Software Controllable Signals Register"]
28 pub SCS: crate::RWRegister<u32>,
29 #[doc = "Software Controllable Signals Register"]
30 pub SCS_SET: crate::RWRegister<u32>,
31 #[doc = "Software Controllable Signals Register"]
32 pub SCS_CLR: crate::RWRegister<u32>,
33 #[doc = "Software Controllable Signals Register"]
34 pub SCS_TOG: crate::RWRegister<u32>,
35 _reserved5: [u8; 0x20],
36 #[doc = "OTP Controller Version Register"]
37 pub VERSION: crate::RORegister<u32>,
38 _reserved6: [u8; 0x6c],
39 #[doc = "OTP Controller Timing Register 2"]
40 pub TIMING2: crate::RWRegister<u32>,
41 _reserved7: [u8; 0x02fc],
42 #[doc = "Value of OTP Bank0 Word0 (Lock controls)"]
43 pub LOCK: crate::RWRegister<u32>,
44 _reserved8: [u8; 0x0c],
45 #[doc = "Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)"]
46 pub CFG0: crate::RWRegister<u32>,
47 _reserved9: [u8; 0x0c],
48 #[doc = "Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)"]
49 pub CFG1: crate::RWRegister<u32>,
50 _reserved10: [u8; 0x0c],
51 #[doc = "Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)"]
52 pub CFG2: crate::RWRegister<u32>,
53 _reserved11: [u8; 0x0c],
54 #[doc = "Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)"]
55 pub CFG3: crate::RWRegister<u32>,
56 _reserved12: [u8; 0x0c],
57 #[doc = "Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)"]
58 pub CFG4: crate::RWRegister<u32>,
59 _reserved13: [u8; 0x0c],
60 #[doc = "Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)"]
61 pub CFG5: crate::RWRegister<u32>,
62 _reserved14: [u8; 0x0c],
63 #[doc = "Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)"]
64 pub CFG6: crate::RWRegister<u32>,
65 _reserved15: [u8; 0x0c],
66 #[doc = "Value of OTP Bank1 Word0 (Memory Related Info.)"]
67 pub MEM0: crate::RWRegister<u32>,
68 _reserved16: [u8; 0x0c],
69 #[doc = "Value of OTP Bank1 Word1 (Memory Related Info.)"]
70 pub MEM1: crate::RWRegister<u32>,
71 _reserved17: [u8; 0x0c],
72 #[doc = "Value of OTP Bank1 Word2 (Memory Related Info.)"]
73 pub MEM2: crate::RWRegister<u32>,
74 _reserved18: [u8; 0x0c],
75 #[doc = "Value of OTP Bank1 Word3 (Memory Related Info.)"]
76 pub MEM3: crate::RWRegister<u32>,
77 _reserved19: [u8; 0x0c],
78 #[doc = "Value of OTP Bank1 Word4 (Memory Related Info.)"]
79 pub MEM4: crate::RWRegister<u32>,
80 _reserved20: [u8; 0x0c],
81 #[doc = "Value of OTP Bank1 Word5 (Analog Info.)"]
82 pub ANA0: crate::RWRegister<u32>,
83 _reserved21: [u8; 0x0c],
84 #[doc = "Value of OTP Bank1 Word6 (Analog Info.)"]
85 pub ANA1: crate::RWRegister<u32>,
86 _reserved22: [u8; 0x0c],
87 #[doc = "Value of OTP Bank1 Word7 (Analog Info.)"]
88 pub ANA2: crate::RWRegister<u32>,
89 _reserved23: [u8; 0x8c],
90 #[doc = "Shadow Register for OTP Bank3 Word0 (SRK Hash)"]
91 pub SRK0: crate::RWRegister<u32>,
92 _reserved24: [u8; 0x0c],
93 #[doc = "Shadow Register for OTP Bank3 Word1 (SRK Hash)"]
94 pub SRK1: crate::RWRegister<u32>,
95 _reserved25: [u8; 0x0c],
96 #[doc = "Shadow Register for OTP Bank3 Word2 (SRK Hash)"]
97 pub SRK2: crate::RWRegister<u32>,
98 _reserved26: [u8; 0x0c],
99 #[doc = "Shadow Register for OTP Bank3 Word3 (SRK Hash)"]
100 pub SRK3: crate::RWRegister<u32>,
101 _reserved27: [u8; 0x0c],
102 #[doc = "Shadow Register for OTP Bank3 Word4 (SRK Hash)"]
103 pub SRK4: crate::RWRegister<u32>,
104 _reserved28: [u8; 0x0c],
105 #[doc = "Shadow Register for OTP Bank3 Word5 (SRK Hash)"]
106 pub SRK5: crate::RWRegister<u32>,
107 _reserved29: [u8; 0x0c],
108 #[doc = "Shadow Register for OTP Bank3 Word6 (SRK Hash)"]
109 pub SRK6: crate::RWRegister<u32>,
110 _reserved30: [u8; 0x0c],
111 #[doc = "Shadow Register for OTP Bank3 Word7 (SRK Hash)"]
112 pub SRK7: crate::RWRegister<u32>,
113 _reserved31: [u8; 0x0c],
114 #[doc = "Value of OTP Bank4 Word0 (Secure JTAG Response Field)"]
115 pub SJC_RESP0: crate::RWRegister<u32>,
116 _reserved32: [u8; 0x0c],
117 #[doc = "Value of OTP Bank4 Word1 (Secure JTAG Response Field)"]
118 pub SJC_RESP1: crate::RWRegister<u32>,
119 _reserved33: [u8; 0x0c],
120 #[doc = "Value of OTP Bank4 Word2 (MAC Address)"]
121 pub MAC0: crate::RWRegister<u32>,
122 _reserved34: [u8; 0x0c],
123 #[doc = "Value of OTP Bank4 Word3 (MAC Address)"]
124 pub MAC1: crate::RWRegister<u32>,
125 _reserved35: [u8; 0x0c],
126 #[doc = "Value of OTP Bank4 Word4 (MAC Address)"]
127 pub GP3: crate::RWRegister<u32>,
128 _reserved36: [u8; 0x1c],
129 #[doc = "Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)"]
130 pub GP1: crate::RWRegister<u32>,
131 _reserved37: [u8; 0x0c],
132 #[doc = "Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)"]
133 pub GP2: crate::RWRegister<u32>,
134 _reserved38: [u8; 0x0c],
135 #[doc = "Value of OTP Bank5 Word0 (SW GP1)"]
136 pub SW_GP1: crate::RWRegister<u32>,
137 _reserved39: [u8; 0x0c],
138 #[doc = "Value of OTP Bank5 Word1 (SW GP2)"]
139 pub SW_GP20: crate::RWRegister<u32>,
140 _reserved40: [u8; 0x0c],
141 #[doc = "Value of OTP Bank5 Word2 (SW GP2)"]
142 pub SW_GP21: crate::RWRegister<u32>,
143 _reserved41: [u8; 0x0c],
144 #[doc = "Value of OTP Bank5 Word3 (SW GP2)"]
145 pub SW_GP22: crate::RWRegister<u32>,
146 _reserved42: [u8; 0x0c],
147 #[doc = "Value of OTP Bank5 Word4 (SW GP2)"]
148 pub SW_GP23: crate::RWRegister<u32>,
149 _reserved43: [u8; 0x0c],
150 #[doc = "Value of OTP Bank5 Word5 (Misc Conf)"]
151 pub MISC_CONF0: crate::RWRegister<u32>,
152 _reserved44: [u8; 0x0c],
153 #[doc = "Value of OTP Bank5 Word6 (Misc Conf)"]
154 pub MISC_CONF1: crate::RWRegister<u32>,
155 _reserved45: [u8; 0x0c],
156 #[doc = "Value of OTP Bank5 Word7 (SRK Revoke)"]
157 pub SRK_REVOKE: crate::RWRegister<u32>,
158}
159#[doc = "OTP Controller Control Register"]
160pub mod CTRL {
161 #[doc = "OTP write and read access address register"]
162 pub mod ADDR {
163 pub const offset: u32 = 0;
164 pub const mask: u32 = 0x3f << offset;
165 pub mod R {}
166 pub mod W {}
167 pub mod RW {}
168 }
169 #[doc = "OTP controller status bit"]
170 pub mod BUSY {
171 pub const offset: u32 = 8;
172 pub const mask: u32 = 0x01 << offset;
173 pub mod R {}
174 pub mod W {}
175 pub mod RW {}
176 }
177 #[doc = "Set by the controller when an access to a locked region(OTP or shadow register) is requested"]
178 pub mod ERROR {
179 pub const offset: u32 = 9;
180 pub const mask: u32 = 0x01 << offset;
181 pub mod R {}
182 pub mod W {}
183 pub mod RW {}
184 }
185 #[doc = "Set to force re-loading the shadow registers (HW/SW capability and LOCK)"]
186 pub mod RELOAD_SHADOWS {
187 pub const offset: u32 = 10;
188 pub const mask: u32 = 0x01 << offset;
189 pub mod R {}
190 pub mod W {}
191 pub mod RW {}
192 }
193 #[doc = "Write 0x3E77 to enable OTP write accesses"]
194 pub mod WR_UNLOCK {
195 pub const offset: u32 = 16;
196 pub const mask: u32 = 0xffff << offset;
197 pub mod R {}
198 pub mod W {}
199 pub mod RW {}
200 }
201}
202#[doc = "OTP Controller Control Register"]
203pub mod CTRL_SET {
204 #[doc = "OTP write and read access address register"]
205 pub mod ADDR {
206 pub const offset: u32 = 0;
207 pub const mask: u32 = 0x3f << offset;
208 pub mod R {}
209 pub mod W {}
210 pub mod RW {}
211 }
212 #[doc = "OTP controller status bit"]
213 pub mod BUSY {
214 pub const offset: u32 = 8;
215 pub const mask: u32 = 0x01 << offset;
216 pub mod R {}
217 pub mod W {}
218 pub mod RW {}
219 }
220 #[doc = "Set by the controller when an access to a locked region(OTP or shadow register) is requested"]
221 pub mod ERROR {
222 pub const offset: u32 = 9;
223 pub const mask: u32 = 0x01 << offset;
224 pub mod R {}
225 pub mod W {}
226 pub mod RW {}
227 }
228 #[doc = "Set to force re-loading the shadow registers (HW/SW capability and LOCK)"]
229 pub mod RELOAD_SHADOWS {
230 pub const offset: u32 = 10;
231 pub const mask: u32 = 0x01 << offset;
232 pub mod R {}
233 pub mod W {}
234 pub mod RW {}
235 }
236 #[doc = "Write 0x3E77 to enable OTP write accesses"]
237 pub mod WR_UNLOCK {
238 pub const offset: u32 = 16;
239 pub const mask: u32 = 0xffff << offset;
240 pub mod R {}
241 pub mod W {}
242 pub mod RW {}
243 }
244}
245#[doc = "OTP Controller Control Register"]
246pub mod CTRL_CLR {
247 #[doc = "OTP write and read access address register"]
248 pub mod ADDR {
249 pub const offset: u32 = 0;
250 pub const mask: u32 = 0x3f << offset;
251 pub mod R {}
252 pub mod W {}
253 pub mod RW {}
254 }
255 #[doc = "OTP controller status bit"]
256 pub mod BUSY {
257 pub const offset: u32 = 8;
258 pub const mask: u32 = 0x01 << offset;
259 pub mod R {}
260 pub mod W {}
261 pub mod RW {}
262 }
263 #[doc = "Set by the controller when an access to a locked region(OTP or shadow register) is requested"]
264 pub mod ERROR {
265 pub const offset: u32 = 9;
266 pub const mask: u32 = 0x01 << offset;
267 pub mod R {}
268 pub mod W {}
269 pub mod RW {}
270 }
271 #[doc = "Set to force re-loading the shadow registers (HW/SW capability and LOCK)"]
272 pub mod RELOAD_SHADOWS {
273 pub const offset: u32 = 10;
274 pub const mask: u32 = 0x01 << offset;
275 pub mod R {}
276 pub mod W {}
277 pub mod RW {}
278 }
279 #[doc = "Write 0x3E77 to enable OTP write accesses"]
280 pub mod WR_UNLOCK {
281 pub const offset: u32 = 16;
282 pub const mask: u32 = 0xffff << offset;
283 pub mod R {}
284 pub mod W {}
285 pub mod RW {}
286 }
287}
288#[doc = "OTP Controller Control Register"]
289pub mod CTRL_TOG {
290 #[doc = "OTP write and read access address register"]
291 pub mod ADDR {
292 pub const offset: u32 = 0;
293 pub const mask: u32 = 0x3f << offset;
294 pub mod R {}
295 pub mod W {}
296 pub mod RW {}
297 }
298 #[doc = "OTP controller status bit"]
299 pub mod BUSY {
300 pub const offset: u32 = 8;
301 pub const mask: u32 = 0x01 << offset;
302 pub mod R {}
303 pub mod W {}
304 pub mod RW {}
305 }
306 #[doc = "Set by the controller when an access to a locked region(OTP or shadow register) is requested"]
307 pub mod ERROR {
308 pub const offset: u32 = 9;
309 pub const mask: u32 = 0x01 << offset;
310 pub mod R {}
311 pub mod W {}
312 pub mod RW {}
313 }
314 #[doc = "Set to force re-loading the shadow registers (HW/SW capability and LOCK)"]
315 pub mod RELOAD_SHADOWS {
316 pub const offset: u32 = 10;
317 pub const mask: u32 = 0x01 << offset;
318 pub mod R {}
319 pub mod W {}
320 pub mod RW {}
321 }
322 #[doc = "Write 0x3E77 to enable OTP write accesses"]
323 pub mod WR_UNLOCK {
324 pub const offset: u32 = 16;
325 pub const mask: u32 = 0xffff << offset;
326 pub mod R {}
327 pub mod W {}
328 pub mod RW {}
329 }
330}
331#[doc = "OTP Controller Timing Register"]
332pub mod TIMING {
333 #[doc = "This count value specifies the strobe period in one time write OTP"]
334 pub mod STROBE_PROG {
335 pub const offset: u32 = 0;
336 pub const mask: u32 = 0x0fff << offset;
337 pub mod R {}
338 pub mod W {}
339 pub mod RW {}
340 }
341 #[doc = "This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd"]
342 pub mod RELAX {
343 pub const offset: u32 = 12;
344 pub const mask: u32 = 0x0f << offset;
345 pub mod R {}
346 pub mod W {}
347 pub mod RW {}
348 }
349 #[doc = "This count value specifies the strobe period in one time read OTP"]
350 pub mod STROBE_READ {
351 pub const offset: u32 = 16;
352 pub const mask: u32 = 0x3f << offset;
353 pub mod R {}
354 pub mod W {}
355 pub mod RW {}
356 }
357 #[doc = "This count value specifies time interval between auto read and write access in one time program"]
358 pub mod WAIT {
359 pub const offset: u32 = 22;
360 pub const mask: u32 = 0x3f << offset;
361 pub mod R {}
362 pub mod W {}
363 pub mod RW {}
364 }
365}
366#[doc = "OTP Controller Write Data Register"]
367pub mod DATA {
368 #[doc = "Used to initiate a write to OTP"]
369 pub mod DATA {
370 pub const offset: u32 = 0;
371 pub const mask: u32 = 0xffff_ffff << offset;
372 pub mod R {}
373 pub mod W {}
374 pub mod RW {}
375 }
376}
377#[doc = "OTP Controller Write Data Register"]
378pub mod READ_CTRL {
379 #[doc = "Used to initiate a read to OTP"]
380 pub mod READ_FUSE {
381 pub const offset: u32 = 0;
382 pub const mask: u32 = 0x01 << offset;
383 pub mod R {}
384 pub mod W {}
385 pub mod RW {}
386 }
387}
388#[doc = "OTP Controller Read Data Register"]
389pub mod READ_FUSE_DATA {
390 #[doc = "The data read from OTP"]
391 pub mod DATA {
392 pub const offset: u32 = 0;
393 pub const mask: u32 = 0xffff_ffff << offset;
394 pub mod R {}
395 pub mod W {}
396 pub mod RW {}
397 }
398}
399#[doc = "Sticky bit Register"]
400pub mod SW_STICKY {
401 #[doc = "Shadow register write and OTP write lock for SRK_REVOKE region"]
402 pub mod SRK_REVOKE_LOCK {
403 pub const offset: u32 = 1;
404 pub const mask: u32 = 0x01 << offset;
405 pub mod R {}
406 pub mod W {}
407 pub mod RW {}
408 }
409 #[doc = "Shadow register write and OTP write lock for FIELD_RETURN region"]
410 pub mod FIELD_RETURN_LOCK {
411 pub const offset: u32 = 2;
412 pub const mask: u32 = 0x01 << offset;
413 pub mod R {}
414 pub mod W {}
415 pub mod RW {}
416 }
417}
418#[doc = "Software Controllable Signals Register"]
419pub mod SCS {
420 #[doc = "HAB JTAG Debug Enable"]
421 pub mod HAB_JDE {
422 pub const offset: u32 = 0;
423 pub const mask: u32 = 0x01 << offset;
424 pub mod R {}
425 pub mod W {}
426 pub mod RW {}
427 }
428 #[doc = "Unallocated read/write bits for implementation specific software use."]
429 pub mod SPARE {
430 pub const offset: u32 = 1;
431 pub const mask: u32 = 0x3fff_ffff << offset;
432 pub mod R {}
433 pub mod W {}
434 pub mod RW {}
435 }
436 #[doc = "When set, all of the bits in this register are locked and can not be changed through SW programming"]
437 pub mod LOCK {
438 pub const offset: u32 = 31;
439 pub const mask: u32 = 0x01 << offset;
440 pub mod R {}
441 pub mod W {}
442 pub mod RW {}
443 }
444}
445#[doc = "Software Controllable Signals Register"]
446pub mod SCS_SET {
447 #[doc = "HAB JTAG Debug Enable"]
448 pub mod HAB_JDE {
449 pub const offset: u32 = 0;
450 pub const mask: u32 = 0x01 << offset;
451 pub mod R {}
452 pub mod W {}
453 pub mod RW {}
454 }
455 #[doc = "Unallocated read/write bits for implementation specific software use."]
456 pub mod SPARE {
457 pub const offset: u32 = 1;
458 pub const mask: u32 = 0x3fff_ffff << offset;
459 pub mod R {}
460 pub mod W {}
461 pub mod RW {}
462 }
463 #[doc = "When set, all of the bits in this register are locked and can not be changed through SW programming"]
464 pub mod LOCK {
465 pub const offset: u32 = 31;
466 pub const mask: u32 = 0x01 << offset;
467 pub mod R {}
468 pub mod W {}
469 pub mod RW {}
470 }
471}
472#[doc = "Software Controllable Signals Register"]
473pub mod SCS_CLR {
474 #[doc = "HAB JTAG Debug Enable"]
475 pub mod HAB_JDE {
476 pub const offset: u32 = 0;
477 pub const mask: u32 = 0x01 << offset;
478 pub mod R {}
479 pub mod W {}
480 pub mod RW {}
481 }
482 #[doc = "Unallocated read/write bits for implementation specific software use."]
483 pub mod SPARE {
484 pub const offset: u32 = 1;
485 pub const mask: u32 = 0x3fff_ffff << offset;
486 pub mod R {}
487 pub mod W {}
488 pub mod RW {}
489 }
490 #[doc = "When set, all of the bits in this register are locked and can not be changed through SW programming"]
491 pub mod LOCK {
492 pub const offset: u32 = 31;
493 pub const mask: u32 = 0x01 << offset;
494 pub mod R {}
495 pub mod W {}
496 pub mod RW {}
497 }
498}
499#[doc = "Software Controllable Signals Register"]
500pub mod SCS_TOG {
501 #[doc = "HAB JTAG Debug Enable"]
502 pub mod HAB_JDE {
503 pub const offset: u32 = 0;
504 pub const mask: u32 = 0x01 << offset;
505 pub mod R {}
506 pub mod W {}
507 pub mod RW {}
508 }
509 #[doc = "Unallocated read/write bits for implementation specific software use."]
510 pub mod SPARE {
511 pub const offset: u32 = 1;
512 pub const mask: u32 = 0x3fff_ffff << offset;
513 pub mod R {}
514 pub mod W {}
515 pub mod RW {}
516 }
517 #[doc = "When set, all of the bits in this register are locked and can not be changed through SW programming"]
518 pub mod LOCK {
519 pub const offset: u32 = 31;
520 pub const mask: u32 = 0x01 << offset;
521 pub mod R {}
522 pub mod W {}
523 pub mod RW {}
524 }
525}
526#[doc = "OTP Controller Version Register"]
527pub mod VERSION {
528 #[doc = "Fixed read-only value reflecting the stepping of the RTL version."]
529 pub mod STEP {
530 pub const offset: u32 = 0;
531 pub const mask: u32 = 0xffff << offset;
532 pub mod R {}
533 pub mod W {}
534 pub mod RW {}
535 }
536 #[doc = "Fixed read-only value reflecting the MINOR field of the RTL version."]
537 pub mod MINOR {
538 pub const offset: u32 = 16;
539 pub const mask: u32 = 0xff << offset;
540 pub mod R {}
541 pub mod W {}
542 pub mod RW {}
543 }
544 #[doc = "Fixed read-only value reflecting the MAJOR field of the RTL version."]
545 pub mod MAJOR {
546 pub const offset: u32 = 24;
547 pub const mask: u32 = 0xff << offset;
548 pub mod R {}
549 pub mod W {}
550 pub mod RW {}
551 }
552}
553#[doc = "OTP Controller Timing Register 2"]
554pub mod TIMING2 {
555 #[doc = "This count value specifies the strobe period in one time write OTP"]
556 pub mod RELAX_PROG {
557 pub const offset: u32 = 0;
558 pub const mask: u32 = 0x0fff << offset;
559 pub mod R {}
560 pub mod W {}
561 pub mod RW {}
562 }
563 #[doc = "This count value specifies the strobe period in one time read OTP"]
564 pub mod RELAX_READ {
565 pub const offset: u32 = 16;
566 pub const mask: u32 = 0x3f << offset;
567 pub mod R {}
568 pub mod W {}
569 pub mod RW {}
570 }
571 #[doc = "This count value specifies time interval between auto read and write access in one time program"]
572 pub mod RELAX1 {
573 pub const offset: u32 = 22;
574 pub const mask: u32 = 0xff << offset;
575 pub mod R {}
576 pub mod W {}
577 pub mod RW {}
578 }
579}
580#[doc = "Value of OTP Bank0 Word0 (Lock controls)"]
581pub mod LOCK {
582 #[doc = "Status of shadow register and OTP write lock for tester region"]
583 pub mod TESTER {
584 pub const offset: u32 = 0;
585 pub const mask: u32 = 0x03 << offset;
586 pub mod R {}
587 pub mod W {}
588 pub mod RW {}
589 }
590 #[doc = "Status of shadow register and OTP write lock for boot_cfg region"]
591 pub mod BOOT_CFG {
592 pub const offset: u32 = 2;
593 pub const mask: u32 = 0x03 << offset;
594 pub mod R {}
595 pub mod W {}
596 pub mod RW {}
597 }
598 #[doc = "Status of shadow register and OTP write lock for mem_trim region"]
599 pub mod MEM_TRIM {
600 pub const offset: u32 = 4;
601 pub const mask: u32 = 0x03 << offset;
602 pub mod R {}
603 pub mod W {}
604 pub mod RW {}
605 }
606 #[doc = "Status of shadow register read and write, OTP read and write lock for sjc_resp region"]
607 pub mod SJC_RESP {
608 pub const offset: u32 = 6;
609 pub const mask: u32 = 0x01 << offset;
610 pub mod R {}
611 pub mod W {}
612 pub mod RW {}
613 }
614 #[doc = "Status of shadow register and OTP write lock for mac_addr region"]
615 pub mod MAC_ADDR {
616 pub const offset: u32 = 8;
617 pub const mask: u32 = 0x03 << offset;
618 pub mod R {}
619 pub mod W {}
620 pub mod RW {}
621 }
622 #[doc = "Status of shadow register and OTP write lock for gp1 region"]
623 pub mod GP1 {
624 pub const offset: u32 = 10;
625 pub const mask: u32 = 0x03 << offset;
626 pub mod R {}
627 pub mod W {}
628 pub mod RW {}
629 }
630 #[doc = "Status of shadow register and OTP write lock for gp2 region"]
631 pub mod GP2 {
632 pub const offset: u32 = 12;
633 pub const mask: u32 = 0x03 << offset;
634 pub mod R {}
635 pub mod W {}
636 pub mod RW {}
637 }
638 #[doc = "Status of shadow register read and write, OTP read and write lock for otpmk region (MSB)"]
639 pub mod OTPMK_MSB {
640 pub const offset: u32 = 15;
641 pub const mask: u32 = 0x01 << offset;
642 pub mod R {}
643 pub mod W {}
644 pub mod RW {}
645 }
646 #[doc = "Status of shadow register and OTP write lock for sw_gp1 region"]
647 pub mod SW_GP1 {
648 pub const offset: u32 = 16;
649 pub const mask: u32 = 0x01 << offset;
650 pub mod R {}
651 pub mod W {}
652 pub mod RW {}
653 }
654 #[doc = "Status of shadow register read and write, OTP read and write lock for otpmk region (LSB)"]
655 pub mod OTPMK_LSB {
656 pub const offset: u32 = 17;
657 pub const mask: u32 = 0x01 << offset;
658 pub mod R {}
659 pub mod W {}
660 pub mod RW {}
661 }
662 #[doc = "Status of shadow register and OTP write lock for analog region"]
663 pub mod ANALOG {
664 pub const offset: u32 = 18;
665 pub const mask: u32 = 0x03 << offset;
666 pub mod R {}
667 pub mod W {}
668 pub mod RW {}
669 }
670 #[doc = "Status of shadow register and OTP write lock for otpmk_crc region"]
671 pub mod OTPMK_CRC {
672 pub const offset: u32 = 20;
673 pub const mask: u32 = 0x01 << offset;
674 pub mod R {}
675 pub mod W {}
676 pub mod RW {}
677 }
678 #[doc = "Status of shadow register and OTP write lock for sw_gp2 region"]
679 pub mod SW_GP2_LOCK {
680 pub const offset: u32 = 21;
681 pub const mask: u32 = 0x01 << offset;
682 pub mod R {}
683 pub mod W {}
684 pub mod RW {}
685 }
686 #[doc = "Status of shadow register and OTP write lock for misc_conf region"]
687 pub mod MISC_CONF {
688 pub const offset: u32 = 22;
689 pub const mask: u32 = 0x01 << offset;
690 pub mod R {}
691 pub mod W {}
692 pub mod RW {}
693 }
694 #[doc = "Status of shadow register and OTP read lock for sw_gp2 region"]
695 pub mod SW_GP2_RLOCK {
696 pub const offset: u32 = 23;
697 pub const mask: u32 = 0x01 << offset;
698 pub mod R {}
699 pub mod W {}
700 pub mod RW {}
701 }
702 #[doc = "Status of shadow register and OTP write lock for gp3 region"]
703 pub mod GP3 {
704 pub const offset: u32 = 26;
705 pub const mask: u32 = 0x03 << offset;
706 pub mod R {}
707 pub mod W {}
708 pub mod RW {}
709 }
710}
711#[doc = "Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)"]
712pub mod CFG0 {
713 #[doc = "This register contains 32 bits of the Unique ID and SJC_CHALLENGE field"]
714 pub mod BITS {
715 pub const offset: u32 = 0;
716 pub const mask: u32 = 0xffff_ffff << offset;
717 pub mod R {}
718 pub mod W {}
719 pub mod RW {}
720 }
721}
722#[doc = "Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)"]
723pub mod CFG1 {
724 #[doc = "This register contains 32 bits of the Unique ID and SJC_CHALLENGE field"]
725 pub mod BITS {
726 pub const offset: u32 = 0;
727 pub const mask: u32 = 0xffff_ffff << offset;
728 pub mod R {}
729 pub mod W {}
730 pub mod RW {}
731 }
732}
733#[doc = "Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)"]
734pub mod CFG2 {
735 #[doc = "Reflects value of OTP Bank 0, word 3 (ADDR = 0x03)"]
736 pub mod BITS {
737 pub const offset: u32 = 0;
738 pub const mask: u32 = 0xffff_ffff << offset;
739 pub mod R {}
740 pub mod W {}
741 pub mod RW {}
742 }
743}
744#[doc = "Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)"]
745pub mod CFG3 {
746 #[doc = "Reflects value of OTP Bank 0, word 4 (ADDR = 0x04)"]
747 pub mod BITS {
748 pub const offset: u32 = 0;
749 pub const mask: u32 = 0xffff_ffff << offset;
750 pub mod R {}
751 pub mod W {}
752 pub mod RW {}
753 }
754}
755#[doc = "Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)"]
756pub mod CFG4 {
757 #[doc = "Reflects value of OTP Bank 0, word 5 (ADDR = 0x05)"]
758 pub mod BITS {
759 pub const offset: u32 = 0;
760 pub const mask: u32 = 0xffff_ffff << offset;
761 pub mod R {}
762 pub mod W {}
763 pub mod RW {}
764 }
765}
766#[doc = "Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)"]
767pub mod CFG5 {
768 #[doc = "Reflects value of OTP Bank 0, word 6 (ADDR = 0x06)"]
769 pub mod BITS {
770 pub const offset: u32 = 0;
771 pub const mask: u32 = 0xffff_ffff << offset;
772 pub mod R {}
773 pub mod W {}
774 pub mod RW {}
775 }
776}
777#[doc = "Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)"]
778pub mod CFG6 {
779 #[doc = "Reflects value of OTP Bank 0, word 7 (ADDR = 0x07)"]
780 pub mod BITS {
781 pub const offset: u32 = 0;
782 pub const mask: u32 = 0xffff_ffff << offset;
783 pub mod R {}
784 pub mod W {}
785 pub mod RW {}
786 }
787}
788#[doc = "Value of OTP Bank1 Word0 (Memory Related Info.)"]
789pub mod MEM0 {
790 #[doc = "Reflects value of OTP bank 1, word 0 (ADDR = 0x08)"]
791 pub mod BITS {
792 pub const offset: u32 = 0;
793 pub const mask: u32 = 0xffff_ffff << offset;
794 pub mod R {}
795 pub mod W {}
796 pub mod RW {}
797 }
798}
799#[doc = "Value of OTP Bank1 Word1 (Memory Related Info.)"]
800pub mod MEM1 {
801 #[doc = "Reflects value of OTP bank 1, word 1 (ADDR = 0x09)"]
802 pub mod BITS {
803 pub const offset: u32 = 0;
804 pub const mask: u32 = 0xffff_ffff << offset;
805 pub mod R {}
806 pub mod W {}
807 pub mod RW {}
808 }
809}
810#[doc = "Value of OTP Bank1 Word2 (Memory Related Info.)"]
811pub mod MEM2 {
812 #[doc = "Reflects value of OTP bank 1, word 2 (ADDR = 0x0A)"]
813 pub mod BITS {
814 pub const offset: u32 = 0;
815 pub const mask: u32 = 0xffff_ffff << offset;
816 pub mod R {}
817 pub mod W {}
818 pub mod RW {}
819 }
820}
821#[doc = "Value of OTP Bank1 Word3 (Memory Related Info.)"]
822pub mod MEM3 {
823 #[doc = "Reflects value of OTP bank 1, word 3 (ADDR = 0x0B)"]
824 pub mod BITS {
825 pub const offset: u32 = 0;
826 pub const mask: u32 = 0xffff_ffff << offset;
827 pub mod R {}
828 pub mod W {}
829 pub mod RW {}
830 }
831}
832#[doc = "Value of OTP Bank1 Word4 (Memory Related Info.)"]
833pub mod MEM4 {
834 #[doc = "Reflects value of OTP bank 1, word 4 (ADDR = 0x0C)"]
835 pub mod BITS {
836 pub const offset: u32 = 0;
837 pub const mask: u32 = 0xffff_ffff << offset;
838 pub mod R {}
839 pub mod W {}
840 pub mod RW {}
841 }
842}
843#[doc = "Value of OTP Bank1 Word5 (Analog Info.)"]
844pub mod ANA0 {
845 #[doc = "Reflects value of OTP bank 1, word 5 (ADDR = 0x0D)"]
846 pub mod BITS {
847 pub const offset: u32 = 0;
848 pub const mask: u32 = 0xffff_ffff << offset;
849 pub mod R {}
850 pub mod W {}
851 pub mod RW {}
852 }
853}
854#[doc = "Value of OTP Bank1 Word6 (Analog Info.)"]
855pub mod ANA1 {
856 #[doc = "Reflects value of OTP bank 1, word 6 (ADDR = 0x0E)"]
857 pub mod BITS {
858 pub const offset: u32 = 0;
859 pub const mask: u32 = 0xffff_ffff << offset;
860 pub mod R {}
861 pub mod W {}
862 pub mod RW {}
863 }
864}
865#[doc = "Value of OTP Bank1 Word7 (Analog Info.)"]
866pub mod ANA2 {
867 #[doc = "Reflects value of OTP bank 1, word 7 (ADDR = 0x0F)"]
868 pub mod BITS {
869 pub const offset: u32 = 0;
870 pub const mask: u32 = 0xffff_ffff << offset;
871 pub mod R {}
872 pub mod W {}
873 pub mod RW {}
874 }
875}
876#[doc = "Shadow Register for OTP Bank3 Word0 (SRK Hash)"]
877pub mod SRK0 {
878 #[doc = "Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x1C))"]
879 pub mod BITS {
880 pub const offset: u32 = 0;
881 pub const mask: u32 = 0xffff_ffff << offset;
882 pub mod R {}
883 pub mod W {}
884 pub mod RW {}
885 }
886}
887#[doc = "Shadow Register for OTP Bank3 Word1 (SRK Hash)"]
888pub mod SRK1 {
889 #[doc = "Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x1D))"]
890 pub mod BITS {
891 pub const offset: u32 = 0;
892 pub const mask: u32 = 0xffff_ffff << offset;
893 pub mod R {}
894 pub mod W {}
895 pub mod RW {}
896 }
897}
898#[doc = "Shadow Register for OTP Bank3 Word2 (SRK Hash)"]
899pub mod SRK2 {
900 #[doc = "Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1E))"]
901 pub mod BITS {
902 pub const offset: u32 = 0;
903 pub const mask: u32 = 0xffff_ffff << offset;
904 pub mod R {}
905 pub mod W {}
906 pub mod RW {}
907 }
908}
909#[doc = "Shadow Register for OTP Bank3 Word3 (SRK Hash)"]
910pub mod SRK3 {
911 #[doc = "Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1F))"]
912 pub mod BITS {
913 pub const offset: u32 = 0;
914 pub const mask: u32 = 0xffff_ffff << offset;
915 pub mod R {}
916 pub mod W {}
917 pub mod RW {}
918 }
919}
920#[doc = "Shadow Register for OTP Bank3 Word4 (SRK Hash)"]
921pub mod SRK4 {
922 #[doc = "Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x20))"]
923 pub mod BITS {
924 pub const offset: u32 = 0;
925 pub const mask: u32 = 0xffff_ffff << offset;
926 pub mod R {}
927 pub mod W {}
928 pub mod RW {}
929 }
930}
931#[doc = "Shadow Register for OTP Bank3 Word5 (SRK Hash)"]
932pub mod SRK5 {
933 #[doc = "Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x21))"]
934 pub mod BITS {
935 pub const offset: u32 = 0;
936 pub const mask: u32 = 0xffff_ffff << offset;
937 pub mod R {}
938 pub mod W {}
939 pub mod RW {}
940 }
941}
942#[doc = "Shadow Register for OTP Bank3 Word6 (SRK Hash)"]
943pub mod SRK6 {
944 #[doc = "Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x22))"]
945 pub mod BITS {
946 pub const offset: u32 = 0;
947 pub const mask: u32 = 0xffff_ffff << offset;
948 pub mod R {}
949 pub mod W {}
950 pub mod RW {}
951 }
952}
953#[doc = "Shadow Register for OTP Bank3 Word7 (SRK Hash)"]
954pub mod SRK7 {
955 #[doc = "Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x23))"]
956 pub mod BITS {
957 pub const offset: u32 = 0;
958 pub const mask: u32 = 0xffff_ffff << offset;
959 pub mod R {}
960 pub mod W {}
961 pub mod RW {}
962 }
963}
964#[doc = "Value of OTP Bank4 Word0 (Secure JTAG Response Field)"]
965pub mod SJC_RESP0 {
966 #[doc = "Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20))"]
967 pub mod BITS {
968 pub const offset: u32 = 0;
969 pub const mask: u32 = 0xffff_ffff << offset;
970 pub mod R {}
971 pub mod W {}
972 pub mod RW {}
973 }
974}
975#[doc = "Value of OTP Bank4 Word1 (Secure JTAG Response Field)"]
976pub mod SJC_RESP1 {
977 #[doc = "Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21))"]
978 pub mod BITS {
979 pub const offset: u32 = 0;
980 pub const mask: u32 = 0xffff_ffff << offset;
981 pub mod R {}
982 pub mod W {}
983 pub mod RW {}
984 }
985}
986#[doc = "Value of OTP Bank4 Word2 (MAC Address)"]
987pub mod MAC0 {
988 #[doc = "Reflects value of OTP Bank 4, word 2 (ADDR = 0x22)."]
989 pub mod BITS {
990 pub const offset: u32 = 0;
991 pub const mask: u32 = 0xffff_ffff << offset;
992 pub mod R {}
993 pub mod W {}
994 pub mod RW {}
995 }
996}
997#[doc = "Value of OTP Bank4 Word3 (MAC Address)"]
998pub mod MAC1 {
999 #[doc = "Reflects value of OTP Bank 4, word 3 (ADDR = 0x23)."]
1000 pub mod BITS {
1001 pub const offset: u32 = 0;
1002 pub const mask: u32 = 0xffff_ffff << offset;
1003 pub mod R {}
1004 pub mod W {}
1005 pub mod RW {}
1006 }
1007}
1008#[doc = "Value of OTP Bank4 Word4 (MAC Address)"]
1009pub mod GP3 {
1010 #[doc = "Reflects value of OTP Bank 4, word 4 (ADDR = 0x24)."]
1011 pub mod BITS {
1012 pub const offset: u32 = 0;
1013 pub const mask: u32 = 0xffff_ffff << offset;
1014 pub mod R {}
1015 pub mod W {}
1016 pub mod RW {}
1017 }
1018}
1019#[doc = "Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)"]
1020pub mod GP1 {
1021 #[doc = "Reflects value of OTP Bank 4, word 6 (ADDR = 0x26)."]
1022 pub mod BITS {
1023 pub const offset: u32 = 0;
1024 pub const mask: u32 = 0xffff_ffff << offset;
1025 pub mod R {}
1026 pub mod W {}
1027 pub mod RW {}
1028 }
1029}
1030#[doc = "Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)"]
1031pub mod GP2 {
1032 #[doc = "Reflects value of OTP Bank 4, word 7 (ADDR = 0x27)."]
1033 pub mod BITS {
1034 pub const offset: u32 = 0;
1035 pub const mask: u32 = 0xffff_ffff << offset;
1036 pub mod R {}
1037 pub mod W {}
1038 pub mod RW {}
1039 }
1040}
1041#[doc = "Value of OTP Bank5 Word0 (SW GP1)"]
1042pub mod SW_GP1 {
1043 #[doc = "Reflects value of OTP Bank 5, word 0 (ADDR = 0x28)."]
1044 pub mod BITS {
1045 pub const offset: u32 = 0;
1046 pub const mask: u32 = 0xffff_ffff << offset;
1047 pub mod R {}
1048 pub mod W {}
1049 pub mod RW {}
1050 }
1051}
1052#[doc = "Value of OTP Bank5 Word1 (SW GP2)"]
1053pub mod SW_GP20 {
1054 #[doc = "Reflects value of OTP Bank 5, word 1 (ADDR = 0x29)."]
1055 pub mod BITS {
1056 pub const offset: u32 = 0;
1057 pub const mask: u32 = 0xffff_ffff << offset;
1058 pub mod R {}
1059 pub mod W {}
1060 pub mod RW {}
1061 }
1062}
1063#[doc = "Value of OTP Bank5 Word2 (SW GP2)"]
1064pub mod SW_GP21 {
1065 #[doc = "Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a)."]
1066 pub mod BITS {
1067 pub const offset: u32 = 0;
1068 pub const mask: u32 = 0xffff_ffff << offset;
1069 pub mod R {}
1070 pub mod W {}
1071 pub mod RW {}
1072 }
1073}
1074#[doc = "Value of OTP Bank5 Word3 (SW GP2)"]
1075pub mod SW_GP22 {
1076 #[doc = "Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b)."]
1077 pub mod BITS {
1078 pub const offset: u32 = 0;
1079 pub const mask: u32 = 0xffff_ffff << offset;
1080 pub mod R {}
1081 pub mod W {}
1082 pub mod RW {}
1083 }
1084}
1085#[doc = "Value of OTP Bank5 Word4 (SW GP2)"]
1086pub mod SW_GP23 {
1087 #[doc = "Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c)."]
1088 pub mod BITS {
1089 pub const offset: u32 = 0;
1090 pub const mask: u32 = 0xffff_ffff << offset;
1091 pub mod R {}
1092 pub mod W {}
1093 pub mod RW {}
1094 }
1095}
1096#[doc = "Value of OTP Bank5 Word5 (Misc Conf)"]
1097pub mod MISC_CONF0 {
1098 #[doc = "Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d)."]
1099 pub mod BITS {
1100 pub const offset: u32 = 0;
1101 pub const mask: u32 = 0xffff_ffff << offset;
1102 pub mod R {}
1103 pub mod W {}
1104 pub mod RW {}
1105 }
1106}
1107#[doc = "Value of OTP Bank5 Word6 (Misc Conf)"]
1108pub mod MISC_CONF1 {
1109 #[doc = "Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e)."]
1110 pub mod BITS {
1111 pub const offset: u32 = 0;
1112 pub const mask: u32 = 0xffff_ffff << offset;
1113 pub mod R {}
1114 pub mod W {}
1115 pub mod RW {}
1116 }
1117}
1118#[doc = "Value of OTP Bank5 Word7 (SRK Revoke)"]
1119pub mod SRK_REVOKE {
1120 #[doc = "Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f)."]
1121 pub mod BITS {
1122 pub const offset: u32 = 0;
1123 pub const mask: u32 = 0xffff_ffff << offset;
1124 pub mod R {}
1125 pub mod W {}
1126 pub mod RW {}
1127 }
1128}