imxrt_ral/blocks/imxrt1011/
gpt.rs

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1#[doc = "GPT"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "GPT Control Register"]
5    pub CR: crate::RWRegister<u32>,
6    #[doc = "GPT Prescaler Register"]
7    pub PR: crate::RWRegister<u32>,
8    #[doc = "GPT Status Register"]
9    pub SR: crate::RWRegister<u32>,
10    #[doc = "GPT Interrupt Register"]
11    pub IR: crate::RWRegister<u32>,
12    #[doc = "GPT Output Compare Register 1"]
13    pub OCR: [crate::RWRegister<u32>; 3usize],
14    #[doc = "GPT Input Capture Register 1"]
15    pub ICR: [crate::RORegister<u32>; 2usize],
16    #[doc = "GPT Counter Register"]
17    pub CNT: crate::RORegister<u32>,
18}
19#[doc = "GPT Control Register"]
20pub mod CR {
21    #[doc = "GPT Enable"]
22    pub mod EN {
23        pub const offset: u32 = 0;
24        pub const mask: u32 = 0x01 << offset;
25        pub mod R {}
26        pub mod W {}
27        pub mod RW {
28            #[doc = "GPT is disabled."]
29            pub const EN_0: u32 = 0;
30            #[doc = "GPT is enabled."]
31            pub const EN_1: u32 = 0x01;
32        }
33    }
34    #[doc = "GPT Enable mode"]
35    pub mod ENMOD {
36        pub const offset: u32 = 1;
37        pub const mask: u32 = 0x01 << offset;
38        pub mod R {}
39        pub mod W {}
40        pub mod RW {
41            #[doc = "GPT counter will retain its value when it is disabled."]
42            pub const ENMOD_0: u32 = 0;
43            #[doc = "GPT counter value is reset to 0 when it is disabled."]
44            pub const ENMOD_1: u32 = 0x01;
45        }
46    }
47    #[doc = "GPT debug mode enable"]
48    pub mod DBGEN {
49        pub const offset: u32 = 2;
50        pub const mask: u32 = 0x01 << offset;
51        pub mod R {}
52        pub mod W {}
53        pub mod RW {
54            #[doc = "GPT is disabled in debug mode."]
55            pub const DBGEN_0: u32 = 0;
56            #[doc = "GPT is enabled in debug mode."]
57            pub const DBGEN_1: u32 = 0x01;
58        }
59    }
60    #[doc = "GPT Wait Mode enable"]
61    pub mod WAITEN {
62        pub const offset: u32 = 3;
63        pub const mask: u32 = 0x01 << offset;
64        pub mod R {}
65        pub mod W {}
66        pub mod RW {
67            #[doc = "GPT is disabled in wait mode."]
68            pub const WAITEN_0: u32 = 0;
69            #[doc = "GPT is enabled in wait mode."]
70            pub const WAITEN_1: u32 = 0x01;
71        }
72    }
73    #[doc = "GPT Doze Mode Enable"]
74    pub mod DOZEEN {
75        pub const offset: u32 = 4;
76        pub const mask: u32 = 0x01 << offset;
77        pub mod R {}
78        pub mod W {}
79        pub mod RW {
80            #[doc = "GPT is disabled in doze mode."]
81            pub const DOZEEN_0: u32 = 0;
82            #[doc = "GPT is enabled in doze mode."]
83            pub const DOZEEN_1: u32 = 0x01;
84        }
85    }
86    #[doc = "GPT Stop Mode enable"]
87    pub mod STOPEN {
88        pub const offset: u32 = 5;
89        pub const mask: u32 = 0x01 << offset;
90        pub mod R {}
91        pub mod W {}
92        pub mod RW {
93            #[doc = "GPT is disabled in Stop mode."]
94            pub const STOPEN_0: u32 = 0;
95            #[doc = "GPT is enabled in Stop mode."]
96            pub const STOPEN_1: u32 = 0x01;
97        }
98    }
99    #[doc = "Clock Source select"]
100    pub mod CLKSRC {
101        pub const offset: u32 = 6;
102        pub const mask: u32 = 0x07 << offset;
103        pub mod R {}
104        pub mod W {}
105        pub mod RW {
106            #[doc = "No clock"]
107            pub const CLKSRC_0: u32 = 0;
108            #[doc = "Peripheral Clock (ipg_clk)"]
109            pub const CLKSRC_1: u32 = 0x01;
110            #[doc = "High Frequency Reference Clock (ipg_clk_highfreq)"]
111            pub const CLKSRC_2: u32 = 0x02;
112            #[doc = "External Clock"]
113            pub const CLKSRC_3: u32 = 0x03;
114            #[doc = "Low Frequency Reference Clock (ipg_clk_32k)"]
115            pub const CLKSRC_4: u32 = 0x04;
116            #[doc = "Crystal oscillator as Reference Clock (ipg_clk_24M)"]
117            pub const CLKSRC_5: u32 = 0x05;
118        }
119    }
120    #[doc = "Free-Run or Restart mode"]
121    pub mod FRR {
122        pub const offset: u32 = 9;
123        pub const mask: u32 = 0x01 << offset;
124        pub mod R {}
125        pub mod W {}
126        pub mod RW {
127            #[doc = "Restart mode"]
128            pub const FRR_0: u32 = 0;
129            #[doc = "Free-Run mode"]
130            pub const FRR_1: u32 = 0x01;
131        }
132    }
133    #[doc = "Enable 24 MHz clock input from crystal"]
134    pub mod EN_24M {
135        pub const offset: u32 = 10;
136        pub const mask: u32 = 0x01 << offset;
137        pub mod R {}
138        pub mod W {}
139        pub mod RW {
140            #[doc = "24M clock disabled"]
141            pub const EN_24M_0: u32 = 0;
142            #[doc = "24M clock enabled"]
143            pub const EN_24M_1: u32 = 0x01;
144        }
145    }
146    #[doc = "Software reset"]
147    pub mod SWR {
148        pub const offset: u32 = 15;
149        pub const mask: u32 = 0x01 << offset;
150        pub mod R {}
151        pub mod W {}
152        pub mod RW {
153            #[doc = "GPT is not in reset state"]
154            pub const SWR_0: u32 = 0;
155            #[doc = "GPT is in reset state"]
156            pub const SWR_1: u32 = 0x01;
157        }
158    }
159    #[doc = "See IM2"]
160    pub mod IM1 {
161        pub const offset: u32 = 16;
162        pub const mask: u32 = 0x03 << offset;
163        pub mod R {}
164        pub mod W {}
165        pub mod RW {}
166    }
167    #[doc = "IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event"]
168    pub mod IM2 {
169        pub const offset: u32 = 18;
170        pub const mask: u32 = 0x03 << offset;
171        pub mod R {}
172        pub mod W {}
173        pub mod RW {}
174    }
175    #[doc = "See OM3"]
176    pub mod OM1 {
177        pub const offset: u32 = 20;
178        pub const mask: u32 = 0x07 << offset;
179        pub mod R {}
180        pub mod W {}
181        pub mod RW {}
182    }
183    #[doc = "See OM3"]
184    pub mod OM2 {
185        pub const offset: u32 = 23;
186        pub const mask: u32 = 0x07 << offset;
187        pub mod R {}
188        pub mod W {}
189        pub mod RW {}
190    }
191    #[doc = "OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode"]
192    pub mod OM3 {
193        pub const offset: u32 = 26;
194        pub const mask: u32 = 0x07 << offset;
195        pub mod R {}
196        pub mod W {}
197        pub mod RW {}
198    }
199    #[doc = "See F03"]
200    pub mod FO1 {
201        pub const offset: u32 = 29;
202        pub const mask: u32 = 0x01 << offset;
203        pub mod R {}
204        pub mod W {}
205        pub mod RW {}
206    }
207    #[doc = "See F03"]
208    pub mod FO2 {
209        pub const offset: u32 = 30;
210        pub const mask: u32 = 0x01 << offset;
211        pub mod R {}
212        pub mod W {}
213        pub mod RW {}
214    }
215    #[doc = "FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register)"]
216    pub mod FO3 {
217        pub const offset: u32 = 31;
218        pub const mask: u32 = 0x01 << offset;
219        pub mod R {}
220        pub mod W {}
221        pub mod RW {}
222    }
223}
224#[doc = "GPT Prescaler Register"]
225pub mod PR {
226    #[doc = "Prescaler bits"]
227    pub mod PRESCALER {
228        pub const offset: u32 = 0;
229        pub const mask: u32 = 0x0fff << offset;
230        pub mod R {}
231        pub mod W {}
232        pub mod RW {
233            #[doc = "Divide by 1"]
234            pub const PRESCALER_0: u32 = 0;
235            #[doc = "Divide by 2"]
236            pub const PRESCALER_1: u32 = 0x01;
237            #[doc = "Divide by 4096"]
238            pub const PRESCALER_4095: u32 = 0x0fff;
239        }
240    }
241    #[doc = "Prescaler bits"]
242    pub mod PRESCALER24M {
243        pub const offset: u32 = 12;
244        pub const mask: u32 = 0x0f << offset;
245        pub mod R {}
246        pub mod W {}
247        pub mod RW {
248            #[doc = "Divide by 1"]
249            pub const PRESCALER24M_0: u32 = 0;
250            #[doc = "Divide by 2"]
251            pub const PRESCALER24M_1: u32 = 0x01;
252            #[doc = "Divide by 16"]
253            pub const PRESCALER24M_15: u32 = 0x0f;
254        }
255    }
256}
257#[doc = "GPT Status Register"]
258pub mod SR {
259    #[doc = "See OF3"]
260    pub mod OF1 {
261        pub const offset: u32 = 0;
262        pub const mask: u32 = 0x01 << offset;
263        pub mod R {}
264        pub mod W {}
265        pub mod RW {}
266    }
267    #[doc = "See OF3"]
268    pub mod OF2 {
269        pub const offset: u32 = 1;
270        pub const mask: u32 = 0x01 << offset;
271        pub mod R {}
272        pub mod W {}
273        pub mod RW {}
274    }
275    #[doc = "OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n"]
276    pub mod OF3 {
277        pub const offset: u32 = 2;
278        pub const mask: u32 = 0x01 << offset;
279        pub mod R {}
280        pub mod W {}
281        pub mod RW {}
282    }
283    #[doc = "See IF2"]
284    pub mod IF1 {
285        pub const offset: u32 = 3;
286        pub const mask: u32 = 0x01 << offset;
287        pub mod R {}
288        pub mod W {}
289        pub mod RW {}
290    }
291    #[doc = "IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n"]
292    pub mod IF2 {
293        pub const offset: u32 = 4;
294        pub const mask: u32 = 0x01 << offset;
295        pub mod R {}
296        pub mod W {}
297        pub mod RW {}
298    }
299    #[doc = "Rollover Flag"]
300    pub mod ROV {
301        pub const offset: u32 = 5;
302        pub const mask: u32 = 0x01 << offset;
303        pub mod R {}
304        pub mod W {}
305        pub mod RW {
306            #[doc = "Rollover has not occurred."]
307            pub const ROV_0: u32 = 0;
308            #[doc = "Rollover has occurred."]
309            pub const ROV_1: u32 = 0x01;
310        }
311    }
312}
313#[doc = "GPT Interrupt Register"]
314pub mod IR {
315    #[doc = "See OF3IE"]
316    pub mod OF1IE {
317        pub const offset: u32 = 0;
318        pub const mask: u32 = 0x01 << offset;
319        pub mod R {}
320        pub mod W {}
321        pub mod RW {}
322    }
323    #[doc = "See OF3IE"]
324    pub mod OF2IE {
325        pub const offset: u32 = 1;
326        pub const mask: u32 = 0x01 << offset;
327        pub mod R {}
328        pub mod W {}
329        pub mod RW {}
330    }
331    #[doc = "OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt"]
332    pub mod OF3IE {
333        pub const offset: u32 = 2;
334        pub const mask: u32 = 0x01 << offset;
335        pub mod R {}
336        pub mod W {}
337        pub mod RW {}
338    }
339    #[doc = "See IF2IE"]
340    pub mod IF1IE {
341        pub const offset: u32 = 3;
342        pub const mask: u32 = 0x01 << offset;
343        pub mod R {}
344        pub mod W {}
345        pub mod RW {}
346    }
347    #[doc = "IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable"]
348    pub mod IF2IE {
349        pub const offset: u32 = 4;
350        pub const mask: u32 = 0x01 << offset;
351        pub mod R {}
352        pub mod W {}
353        pub mod RW {}
354    }
355    #[doc = "Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt."]
356    pub mod ROVIE {
357        pub const offset: u32 = 5;
358        pub const mask: u32 = 0x01 << offset;
359        pub mod R {}
360        pub mod W {}
361        pub mod RW {
362            #[doc = "Rollover interrupt is disabled."]
363            pub const ROVIE_0: u32 = 0;
364            #[doc = "Rollover interrupt enabled."]
365            pub const ROVIE_1: u32 = 0x01;
366        }
367    }
368}
369#[doc = "GPT Output Compare Register 1"]
370pub mod OCR {
371    #[doc = "Compare Value"]
372    pub mod COMP {
373        pub const offset: u32 = 0;
374        pub const mask: u32 = 0xffff_ffff << offset;
375        pub mod R {}
376        pub mod W {}
377        pub mod RW {}
378    }
379}
380#[doc = "GPT Input Capture Register 1"]
381pub mod ICR {
382    #[doc = "Capture Value"]
383    pub mod CAPT {
384        pub const offset: u32 = 0;
385        pub const mask: u32 = 0xffff_ffff << offset;
386        pub mod R {}
387        pub mod W {}
388        pub mod RW {}
389    }
390}
391#[doc = "GPT Counter Register"]
392pub mod CNT {
393    #[doc = "Counter Value. The COUNT bits show the current count value of the GPT counter."]
394    pub mod COUNT {
395        pub const offset: u32 = 0;
396        pub const mask: u32 = 0xffff_ffff << offset;
397        pub mod R {}
398        pub mod W {}
399        pub mod RW {}
400    }
401}
imxrt_ral/blocks/imxrt1011/gpt.rs

imxrt_ral/blocks/imxrt1011/
gpt.rs
