rp2040_pac/ppb/
nvic_ipr5.rs

Help
1#[doc = "Register `NVIC_IPR5` reader"]
2pub type R = crate::R<NVIC_IPR5_SPEC>;
3#[doc = "Register `NVIC_IPR5` writer"]
4pub type W = crate::W<NVIC_IPR5_SPEC>;
5#[doc = "Field `IP_20` reader - Priority of interrupt 20"]
6pub type IP_20_R = crate::FieldReader;
7#[doc = "Field `IP_20` writer - Priority of interrupt 20"]
8pub type IP_20_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `IP_21` reader - Priority of interrupt 21"]
10pub type IP_21_R = crate::FieldReader;
11#[doc = "Field `IP_21` writer - Priority of interrupt 21"]
12pub type IP_21_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `IP_22` reader - Priority of interrupt 22"]
14pub type IP_22_R = crate::FieldReader;
15#[doc = "Field `IP_22` writer - Priority of interrupt 22"]
16pub type IP_22_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `IP_23` reader - Priority of interrupt 23"]
18pub type IP_23_R = crate::FieldReader;
19#[doc = "Field `IP_23` writer - Priority of interrupt 23"]
20pub type IP_23_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21impl R {
22    #[doc = "Bits 6:7 - Priority of interrupt 20"]
23    #[inline(always)]
24    pub fn ip_20(&self) -> IP_20_R {
25        IP_20_R::new(((self.bits >> 6) & 3) as u8)
26    }
27    #[doc = "Bits 14:15 - Priority of interrupt 21"]
28    #[inline(always)]
29    pub fn ip_21(&self) -> IP_21_R {
30        IP_21_R::new(((self.bits >> 14) & 3) as u8)
31    }
32    #[doc = "Bits 22:23 - Priority of interrupt 22"]
33    #[inline(always)]
34    pub fn ip_22(&self) -> IP_22_R {
35        IP_22_R::new(((self.bits >> 22) & 3) as u8)
36    }
37    #[doc = "Bits 30:31 - Priority of interrupt 23"]
38    #[inline(always)]
39    pub fn ip_23(&self) -> IP_23_R {
40        IP_23_R::new(((self.bits >> 30) & 3) as u8)
41    }
42}
43impl W {
44    #[doc = "Bits 6:7 - Priority of interrupt 20"]
45    #[inline(always)]
46    #[must_use]
47    pub fn ip_20(&mut self) -> IP_20_W<NVIC_IPR5_SPEC> {
48        IP_20_W::new(self, 6)
49    }
50    #[doc = "Bits 14:15 - Priority of interrupt 21"]
51    #[inline(always)]
52    #[must_use]
53    pub fn ip_21(&mut self) -> IP_21_W<NVIC_IPR5_SPEC> {
54        IP_21_W::new(self, 14)
55    }
56    #[doc = "Bits 22:23 - Priority of interrupt 22"]
57    #[inline(always)]
58    #[must_use]
59    pub fn ip_22(&mut self) -> IP_22_W<NVIC_IPR5_SPEC> {
60        IP_22_W::new(self, 22)
61    }
62    #[doc = "Bits 30:31 - Priority of interrupt 23"]
63    #[inline(always)]
64    #[must_use]
65    pub fn ip_23(&mut self) -> IP_23_W<NVIC_IPR5_SPEC> {
66        IP_23_W::new(self, 30)
67    }
68    #[doc = r" Writes raw bits to the register."]
69    #[doc = r""]
70    #[doc = r" # Safety"]
71    #[doc = r""]
72    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.bits = bits;
76        self
77    }
78}
79#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
80
81You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
82pub struct NVIC_IPR5_SPEC;
83impl crate::RegisterSpec for NVIC_IPR5_SPEC {
84    type Ux = u32;
85}
86#[doc = "`read()` method returns [`nvic_ipr5::R`](R) reader structure"]
87impl crate::Readable for NVIC_IPR5_SPEC {}
88#[doc = "`write(|w| ..)` method takes [`nvic_ipr5::W`](W) writer structure"]
89impl crate::Writable for NVIC_IPR5_SPEC {
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
92}
93#[doc = "`reset()` method sets NVIC_IPR5 to value 0"]
94impl crate::Resettable for NVIC_IPR5_SPEC {
95    const RESET_VALUE: u32 = 0;
96}
rp2040_pac/ppb/nvic_ipr5.rs

rp2040_pac/ppb/
nvic_ipr5.rs
