rp2040_pac/usbctrl_regs/
main_ctrl.rs

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1#[doc = "Register `MAIN_CTRL` reader"]
2pub type R = crate::R<MAIN_CTRL_SPEC>;
3#[doc = "Register `MAIN_CTRL` writer"]
4pub type W = crate::W<MAIN_CTRL_SPEC>;
5#[doc = "Field `CONTROLLER_EN` reader - Enable controller"]
6pub type CONTROLLER_EN_R = crate::BitReader;
7#[doc = "Field `CONTROLLER_EN` writer - Enable controller"]
8pub type CONTROLLER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `HOST_NDEVICE` reader - Device mode = 0, Host mode = 1"]
10pub type HOST_NDEVICE_R = crate::BitReader;
11#[doc = "Field `HOST_NDEVICE` writer - Device mode = 0, Host mode = 1"]
12pub type HOST_NDEVICE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SIM_TIMING` reader - Reduced timings for simulation"]
14pub type SIM_TIMING_R = crate::BitReader;
15#[doc = "Field `SIM_TIMING` writer - Reduced timings for simulation"]
16pub type SIM_TIMING_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Enable controller"]
19    #[inline(always)]
20    pub fn controller_en(&self) -> CONTROLLER_EN_R {
21        CONTROLLER_EN_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Device mode = 0, Host mode = 1"]
24    #[inline(always)]
25    pub fn host_ndevice(&self) -> HOST_NDEVICE_R {
26        HOST_NDEVICE_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 31 - Reduced timings for simulation"]
29    #[inline(always)]
30    pub fn sim_timing(&self) -> SIM_TIMING_R {
31        SIM_TIMING_R::new(((self.bits >> 31) & 1) != 0)
32    }
33}
34impl W {
35    #[doc = "Bit 0 - Enable controller"]
36    #[inline(always)]
37    #[must_use]
38    pub fn controller_en(&mut self) -> CONTROLLER_EN_W<MAIN_CTRL_SPEC> {
39        CONTROLLER_EN_W::new(self, 0)
40    }
41    #[doc = "Bit 1 - Device mode = 0, Host mode = 1"]
42    #[inline(always)]
43    #[must_use]
44    pub fn host_ndevice(&mut self) -> HOST_NDEVICE_W<MAIN_CTRL_SPEC> {
45        HOST_NDEVICE_W::new(self, 1)
46    }
47    #[doc = "Bit 31 - Reduced timings for simulation"]
48    #[inline(always)]
49    #[must_use]
50    pub fn sim_timing(&mut self) -> SIM_TIMING_W<MAIN_CTRL_SPEC> {
51        SIM_TIMING_W::new(self, 31)
52    }
53    #[doc = r" Writes raw bits to the register."]
54    #[doc = r""]
55    #[doc = r" # Safety"]
56    #[doc = r""]
57    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
58    #[inline(always)]
59    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
60        self.bits = bits;
61        self
62    }
63}
64#[doc = "Main control register  
65
66You can [`read`](crate::generic::Reg::read) this register and get [`main_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
67pub struct MAIN_CTRL_SPEC;
68impl crate::RegisterSpec for MAIN_CTRL_SPEC {
69    type Ux = u32;
70}
71#[doc = "`read()` method returns [`main_ctrl::R`](R) reader structure"]
72impl crate::Readable for MAIN_CTRL_SPEC {}
73#[doc = "`write(|w| ..)` method takes [`main_ctrl::W`](W) writer structure"]
74impl crate::Writable for MAIN_CTRL_SPEC {
75    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
77}
78#[doc = "`reset()` method sets MAIN_CTRL to value 0"]
79impl crate::Resettable for MAIN_CTRL_SPEC {
80    const RESET_VALUE: u32 = 0;
81}
rp2040_pac/usbctrl_regs/main_ctrl.rs

rp2040_pac/usbctrl_regs/
main_ctrl.rs
