rp2040_pac/clocks/
clk_gpout1_selected.rs

1#[doc = "Register `CLK_GPOUT1_SELECTED` reader"]
2pub type R = crate::R<CLK_GPOUT1_SELECTED_SPEC>;
3impl core::fmt::Debug for R {
4    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5        write!(f, "{}", self.bits())
6    }
7}
8impl core::fmt::Debug for crate::generic::Reg<CLK_GPOUT1_SELECTED_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        core::fmt::Debug::fmt(&self.read(), f)
11    }
12}
13#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
14 This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
15
16You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17pub struct CLK_GPOUT1_SELECTED_SPEC;
18impl crate::RegisterSpec for CLK_GPOUT1_SELECTED_SPEC {
19    type Ux = u32;
20}
21#[doc = "`read()` method returns [`clk_gpout1_selected::R`](R) reader structure"]
22impl crate::Readable for CLK_GPOUT1_SELECTED_SPEC {}
23#[doc = "`reset()` method sets CLK_GPOUT1_SELECTED to value 0x01"]
24impl crate::Resettable for CLK_GPOUT1_SELECTED_SPEC {
25    const RESET_VALUE: u32 = 0x01;
26}