rp2040_pac/io_qspi/
proc0_ints.rs

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1#[doc = "Register `PROC0_INTS` reader"]
2pub type R = crate::R<PROC0_INTS_SPEC>;
3#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "]
4pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader;
5#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "]
6pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader;
7#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "]
8pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader;
9#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "]
10pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader;
11#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "]
12pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader;
13#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "]
14pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader;
15#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "]
16pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader;
17#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "]
18pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader;
19#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "]
20pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader;
21#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "]
22pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader;
23#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "]
24pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader;
25#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "]
26pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader;
27#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "]
28pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader;
29#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "]
30pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader;
31#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "]
32pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader;
33#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "]
34pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader;
35#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "]
36pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader;
37#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "]
38pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader;
39#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "]
40pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader;
41#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "]
42pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader;
43#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "]
44pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader;
45#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "]
46pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader;
47#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "]
48pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader;
49#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "]
50pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader;
51impl R {
52    #[doc = "Bit 0"]
53    #[inline(always)]
54    pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R {
55        GPIO_QSPI_SCLK_LEVEL_LOW_R::new((self.bits & 1) != 0)
56    }
57    #[doc = "Bit 1"]
58    #[inline(always)]
59    pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R {
60        GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0)
61    }
62    #[doc = "Bit 2"]
63    #[inline(always)]
64    pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R {
65        GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0)
66    }
67    #[doc = "Bit 3"]
68    #[inline(always)]
69    pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R {
70        GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0)
71    }
72    #[doc = "Bit 4"]
73    #[inline(always)]
74    pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R {
75        GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0)
76    }
77    #[doc = "Bit 5"]
78    #[inline(always)]
79    pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R {
80        GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0)
81    }
82    #[doc = "Bit 6"]
83    #[inline(always)]
84    pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R {
85        GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0)
86    }
87    #[doc = "Bit 7"]
88    #[inline(always)]
89    pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R {
90        GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0)
91    }
92    #[doc = "Bit 8"]
93    #[inline(always)]
94    pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R {
95        GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0)
96    }
97    #[doc = "Bit 9"]
98    #[inline(always)]
99    pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R {
100        GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0)
101    }
102    #[doc = "Bit 10"]
103    #[inline(always)]
104    pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R {
105        GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0)
106    }
107    #[doc = "Bit 11"]
108    #[inline(always)]
109    pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R {
110        GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0)
111    }
112    #[doc = "Bit 12"]
113    #[inline(always)]
114    pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R {
115        GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0)
116    }
117    #[doc = "Bit 13"]
118    #[inline(always)]
119    pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R {
120        GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0)
121    }
122    #[doc = "Bit 14"]
123    #[inline(always)]
124    pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R {
125        GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0)
126    }
127    #[doc = "Bit 15"]
128    #[inline(always)]
129    pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R {
130        GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0)
131    }
132    #[doc = "Bit 16"]
133    #[inline(always)]
134    pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R {
135        GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0)
136    }
137    #[doc = "Bit 17"]
138    #[inline(always)]
139    pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R {
140        GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0)
141    }
142    #[doc = "Bit 18"]
143    #[inline(always)]
144    pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R {
145        GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0)
146    }
147    #[doc = "Bit 19"]
148    #[inline(always)]
149    pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R {
150        GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0)
151    }
152    #[doc = "Bit 20"]
153    #[inline(always)]
154    pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R {
155        GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0)
156    }
157    #[doc = "Bit 21"]
158    #[inline(always)]
159    pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R {
160        GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0)
161    }
162    #[doc = "Bit 22"]
163    #[inline(always)]
164    pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R {
165        GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0)
166    }
167    #[doc = "Bit 23"]
168    #[inline(always)]
169    pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R {
170        GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0)
171    }
172}
173#[doc = "Interrupt status after masking &amp; forcing for proc0  
174
175You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
176pub struct PROC0_INTS_SPEC;
177impl crate::RegisterSpec for PROC0_INTS_SPEC {
178    type Ux = u32;
179}
180#[doc = "`read()` method returns [`proc0_ints::R`](R) reader structure"]
181impl crate::Readable for PROC0_INTS_SPEC {}
182#[doc = "`reset()` method sets PROC0_INTS to value 0"]
183impl crate::Resettable for PROC0_INTS_SPEC {
184    const RESET_VALUE: u32 = 0;
185}
rp2040_pac/io_qspi/proc0_ints.rs

rp2040_pac/io_qspi/
proc0_ints.rs
