imxrt_ral/blocks/imxrt1011/
otfad.rs
1#[doc = "OTFAD"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x0c00],
5 #[doc = "Control Register"]
6 pub CR: crate::RWRegister<u32>,
7 #[doc = "Status Register"]
8 pub SR: crate::RWRegister<u32>,
9 _reserved1: [u8; 0xf8],
10 #[doc = "no description available"]
11 pub CTX: [ctx::RegisterBlock; 4usize],
12}
13#[doc = "Control Register"]
14pub mod CR {
15 #[doc = "IRQE"]
16 pub mod IRQE {
17 pub const offset: u32 = 0;
18 pub const mask: u32 = 0x01 << offset;
19 pub mod R {}
20 pub mod W {}
21 pub mod RW {
22 #[doc = "SR\\[KBERR\\] = 1 does not generate an interrupt request."]
23 pub const IRQE_0: u32 = 0;
24 #[doc = "SR\\[KBERR\\] = 1 generates an interrupt request."]
25 pub const IRQE_1: u32 = 0x01;
26 }
27 }
28 #[doc = "Force Error"]
29 pub mod FERR {
30 pub const offset: u32 = 1;
31 pub const mask: u32 = 0x01 << offset;
32 pub mod R {}
33 pub mod W {}
34 pub mod RW {
35 #[doc = "No effect on the SR\\[KBERE\\] indicator."]
36 pub const FERR_0: u32 = 0;
37 #[doc = "SR\\[KBERR\\] is immediately set after a write with this data bit set."]
38 pub const FERR_1: u32 = 0x01;
39 }
40 }
41 #[doc = "Force Security Violation Mode"]
42 pub mod FSVM {
43 pub const offset: u32 = 2;
44 pub const mask: u32 = 0x01 << offset;
45 pub mod R {}
46 pub mod W {}
47 pub mod RW {
48 #[doc = "No effect on the operating mode."]
49 pub const FSVM_0: u32 = 0;
50 #[doc = "Force entry into SVM after a write with this data bit set and the data bit associated with FLDM cleared. SR\\[MODE\\] signals the operating mode."]
51 pub const FSVM_1: u32 = 0x01;
52 }
53 }
54 #[doc = "Force Logically Disabled Mode"]
55 pub mod FLDM {
56 pub const offset: u32 = 3;
57 pub const mask: u32 = 0x01 << offset;
58 pub mod R {}
59 pub mod W {}
60 pub mod RW {
61 #[doc = "No effect on the operating mode."]
62 pub const FLDM_0: u32 = 0;
63 #[doc = "Force entry into LDM after a write with this data bit set. SR\\[MODE\\] signals the operating mode."]
64 pub const FLDM_1: u32 = 0x01;
65 }
66 }
67 #[doc = "Key Blob Scramble Enable"]
68 pub mod KBSE {
69 pub const offset: u32 = 4;
70 pub const mask: u32 = 0x01 << offset;
71 pub mod R {}
72 pub mod W {}
73 pub mod RW {
74 #[doc = "Key blob KEK scrambling is disabled."]
75 pub const KBSE_0: u32 = 0;
76 #[doc = "Key blob KEK scrambling is enabled."]
77 pub const KBSE_1: u32 = 0x01;
78 }
79 }
80 #[doc = "Key Blob Processing Enable"]
81 pub mod KBPE {
82 pub const offset: u32 = 5;
83 pub const mask: u32 = 0x01 << offset;
84 pub mod R {}
85 pub mod W {}
86 pub mod RW {
87 #[doc = "Key blob processing is disabled."]
88 pub const KBPE_0: u32 = 0;
89 #[doc = "Key blob processing is enabled."]
90 pub const KBPE_1: u32 = 0x01;
91 }
92 }
93 #[doc = "Key Blob CRC Enable"]
94 pub mod KBCE {
95 pub const offset: u32 = 6;
96 pub const mask: u32 = 0x01 << offset;
97 pub mod R {}
98 pub mod W {}
99 pub mod RW {
100 #[doc = "CRC-32 during key blob processing is disabled."]
101 pub const KBCE_0: u32 = 0;
102 #[doc = "CRC-32 during key blob processing is enabled."]
103 pub const KBCE_1: u32 = 0x01;
104 }
105 }
106 #[doc = "Restricted Register Access Enable"]
107 pub mod RRAE {
108 pub const offset: u32 = 7;
109 pub const mask: u32 = 0x01 << offset;
110 pub mod R {}
111 pub mod W {}
112 pub mod RW {
113 #[doc = "Register access is fully enabled. The OTFAD programming model registers can be accessed \"normally\"."]
114 pub const RRAE_0: u32 = 0;
115 #[doc = "Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI."]
116 pub const RRAE_1: u32 = 0x01;
117 }
118 }
119 #[doc = "Start key blob processing"]
120 pub mod SKBP {
121 pub const offset: u32 = 30;
122 pub const mask: u32 = 0x01 << offset;
123 pub mod R {}
124 pub mod W {}
125 pub mod RW {
126 #[doc = "Key blob processing is not initiated."]
127 pub const SKBP_0: u32 = 0;
128 #[doc = "Properly-enabled key blob processing is initiated."]
129 pub const SKBP_1: u32 = 0x01;
130 }
131 }
132 #[doc = "Global OTFAD Enable"]
133 pub mod GE {
134 pub const offset: u32 = 31;
135 pub const mask: u32 = 0x01 << offset;
136 pub mod R {}
137 pub mod W {}
138 pub mod RW {
139 #[doc = "OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing."]
140 pub const GE_0: u32 = 0;
141 #[doc = "OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration."]
142 pub const GE_1: u32 = 0x01;
143 }
144 }
145}
146#[doc = "Status Register"]
147pub mod SR {
148 #[doc = "Key Blob Error"]
149 pub mod KBERR {
150 pub const offset: u32 = 0;
151 pub const mask: u32 = 0x01 << offset;
152 pub mod R {}
153 pub mod W {}
154 pub mod RW {
155 #[doc = "No key blob error detected."]
156 pub const KBERR_0: u32 = 0;
157 #[doc = "One or more key blob errors has been detected."]
158 pub const KBERR_1: u32 = 0x01;
159 }
160 }
161 #[doc = "MDPC Present"]
162 pub mod MDPCP {
163 pub const offset: u32 = 1;
164 pub const mask: u32 = 0x01 << offset;
165 pub mod R {}
166 pub mod W {}
167 pub mod RW {}
168 }
169 #[doc = "Operating Mode"]
170 pub mod MODE {
171 pub const offset: u32 = 2;
172 pub const mask: u32 = 0x03 << offset;
173 pub mod R {}
174 pub mod W {}
175 pub mod RW {
176 #[doc = "Operating in Normal mode (NRM)"]
177 pub const MODE_0: u32 = 0;
178 #[doc = "Unused (reserved)"]
179 pub const MODE_1: u32 = 0x01;
180 #[doc = "Operating in Security Violation Mode (SVM)"]
181 pub const MODE_2: u32 = 0x02;
182 #[doc = "Operating in Logically Disabled Mode (LDM)"]
183 pub const MODE_3: u32 = 0x03;
184 }
185 }
186 #[doc = "Number of Contexts"]
187 pub mod NCTX {
188 pub const offset: u32 = 4;
189 pub const mask: u32 = 0x0f << offset;
190 pub mod R {}
191 pub mod W {}
192 pub mod RW {}
193 }
194 #[doc = "Context Error"]
195 pub mod CTXER0 {
196 pub const offset: u32 = 8;
197 pub const mask: u32 = 0x01 << offset;
198 pub mod R {}
199 pub mod W {}
200 pub mod RW {
201 #[doc = "No key blob error was detected for context \"n\"."]
202 pub const NOERROR: u32 = 0;
203 #[doc = "Either a key blob integrity error or a key blob CRC error was detected in context \"n\"."]
204 pub const ERROR: u32 = 0x01;
205 }
206 }
207 #[doc = "Context Error"]
208 pub mod CTXER1 {
209 pub const offset: u32 = 9;
210 pub const mask: u32 = 0x01 << offset;
211 pub mod R {}
212 pub mod W {}
213 pub mod RW {
214 #[doc = "No key blob error was detected for context \"n\"."]
215 pub const NOERROR: u32 = 0;
216 #[doc = "Either a key blob integrity error or a key blob CRC error was detected in context \"n\"."]
217 pub const ERROR: u32 = 0x01;
218 }
219 }
220 #[doc = "Context Error"]
221 pub mod CTXER2 {
222 pub const offset: u32 = 10;
223 pub const mask: u32 = 0x01 << offset;
224 pub mod R {}
225 pub mod W {}
226 pub mod RW {
227 #[doc = "No key blob error was detected for context \"n\"."]
228 pub const NOERROR: u32 = 0;
229 #[doc = "Either a key blob integrity error or a key blob CRC error was detected in context \"n\"."]
230 pub const ERROR: u32 = 0x01;
231 }
232 }
233 #[doc = "Context Error"]
234 pub mod CTXER3 {
235 pub const offset: u32 = 11;
236 pub const mask: u32 = 0x01 << offset;
237 pub mod R {}
238 pub mod W {}
239 pub mod RW {
240 #[doc = "No key blob error was detected for context \"n\"."]
241 pub const NOERROR: u32 = 0;
242 #[doc = "Either a key blob integrity error or a key blob CRC error was detected in context \"n\"."]
243 pub const ERROR: u32 = 0x01;
244 }
245 }
246 #[doc = "Context Integrity Error"]
247 pub mod CTXIE0 {
248 pub const offset: u32 = 16;
249 pub const mask: u32 = 0x01 << offset;
250 pub mod R {}
251 pub mod W {}
252 pub mod RW {
253 #[doc = "No key blob integrity error was detected for context \"n\"."]
254 pub const NOINTEGRITYERR: u32 = 0;
255 #[doc = "A key blob integrity error was detected in context \"n\"."]
256 pub const INTEGRITYERR: u32 = 0x01;
257 }
258 }
259 #[doc = "Context Integrity Error"]
260 pub mod CTXIE1 {
261 pub const offset: u32 = 17;
262 pub const mask: u32 = 0x01 << offset;
263 pub mod R {}
264 pub mod W {}
265 pub mod RW {
266 #[doc = "No key blob integrity error was detected for context \"n\"."]
267 pub const NOINTEGRITYERR: u32 = 0;
268 #[doc = "A key blob integrity error was detected in context \"n\"."]
269 pub const INTEGRITYERR: u32 = 0x01;
270 }
271 }
272 #[doc = "Context Integrity Error"]
273 pub mod CTXIE2 {
274 pub const offset: u32 = 18;
275 pub const mask: u32 = 0x01 << offset;
276 pub mod R {}
277 pub mod W {}
278 pub mod RW {
279 #[doc = "No key blob integrity error was detected for context \"n\"."]
280 pub const NOINTEGRITYERR: u32 = 0;
281 #[doc = "A key blob integrity error was detected in context \"n\"."]
282 pub const INTEGRITYERR: u32 = 0x01;
283 }
284 }
285 #[doc = "Context Integrity Error"]
286 pub mod CTXIE3 {
287 pub const offset: u32 = 19;
288 pub const mask: u32 = 0x01 << offset;
289 pub mod R {}
290 pub mod W {}
291 pub mod RW {
292 #[doc = "No key blob integrity error was detected for context \"n\"."]
293 pub const NOINTEGRITYERR: u32 = 0;
294 #[doc = "A key blob integrity error was detected in context \"n\"."]
295 pub const INTEGRITYERR: u32 = 0x01;
296 }
297 }
298 #[doc = "Hardware Revision Level"]
299 pub mod HRL {
300 pub const offset: u32 = 24;
301 pub const mask: u32 = 0x0f << offset;
302 pub mod R {}
303 pub mod W {}
304 pub mod RW {}
305 }
306 #[doc = "Restricted Register Access Mode"]
307 pub mod RRAM {
308 pub const offset: u32 = 28;
309 pub const mask: u32 = 0x01 << offset;
310 pub mod R {}
311 pub mod W {}
312 pub mod RW {
313 #[doc = "Register access is fully enabled. The OTFAD programming model registers can be accessed \"normally\"."]
314 pub const RRAM_0: u32 = 0;
315 #[doc = "Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI."]
316 pub const RRAM_1: u32 = 0x01;
317 }
318 }
319 #[doc = "Global Enable Mode"]
320 pub mod GEM {
321 pub const offset: u32 = 29;
322 pub const mask: u32 = 0x01 << offset;
323 pub mod R {}
324 pub mod W {}
325 pub mod RW {
326 #[doc = "OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing."]
327 pub const GEM_0: u32 = 0;
328 #[doc = "OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration."]
329 pub const GEM_1: u32 = 0x01;
330 }
331 }
332 #[doc = "Key Blob Processing Enable"]
333 pub mod KBPE {
334 pub const offset: u32 = 30;
335 pub const mask: u32 = 0x01 << offset;
336 pub mod R {}
337 pub mod W {}
338 pub mod RW {
339 #[doc = "Key blob processing is not enabled."]
340 pub const KBPE_0: u32 = 0;
341 #[doc = "Key blob processing is enabled."]
342 pub const KBPE_1: u32 = 0x01;
343 }
344 }
345 #[doc = "Key Blob Processing Done"]
346 pub mod KBD {
347 pub const offset: u32 = 31;
348 pub const mask: u32 = 0x01 << offset;
349 pub mod R {}
350 pub mod W {}
351 pub mod RW {
352 #[doc = "Key blob processing was not enabled, or is not complete."]
353 pub const KBD_0: u32 = 0;
354 #[doc = "Key blob processing was enabled and is complete."]
355 pub const KBD_1: u32 = 0x01;
356 }
357 }
358}
359pub mod ctx {
360 #[doc = "no description available"]
361 #[repr(C)]
362 pub struct RegisterBlock {
363 #[doc = "AES Key Word"]
364 pub CTX_KEY: [crate::RWRegister<u32>; 4usize],
365 #[doc = "AES Counter Word"]
366 pub CTX_CTR: [crate::RWRegister<u32>; 2usize],
367 #[doc = "AES Region Descriptor Word0"]
368 pub CTX_RGD_W0: crate::RWRegister<u32>,
369 #[doc = "AES Region Descriptor Word1"]
370 pub CTX_RGD_W1: crate::RWRegister<u32>,
371 _reserved0: [u8; 0x20],
372 }
373 #[doc = "AES Key Word"]
374 pub mod CTX_KEY {
375 #[doc = "AES Key"]
376 pub mod KEY {
377 pub const offset: u32 = 0;
378 pub const mask: u32 = 0xffff_ffff << offset;
379 pub mod R {}
380 pub mod W {}
381 pub mod RW {}
382 }
383 }
384 #[doc = "AES Counter Word"]
385 pub mod CTX_CTR {
386 #[doc = "AES Counter"]
387 pub mod CTR {
388 pub const offset: u32 = 0;
389 pub const mask: u32 = 0xffff_ffff << offset;
390 pub mod R {}
391 pub mod W {}
392 pub mod RW {}
393 }
394 }
395 #[doc = "AES Region Descriptor Word0"]
396 pub mod CTX_RGD_W0 {
397 #[doc = "Start Address"]
398 pub mod SRTADDR {
399 pub const offset: u32 = 10;
400 pub const mask: u32 = 0x003f_ffff << offset;
401 pub mod R {}
402 pub mod W {}
403 pub mod RW {}
404 }
405 }
406 #[doc = "AES Region Descriptor Word1"]
407 pub mod CTX_RGD_W1 {
408 #[doc = "Valid"]
409 pub mod VLD {
410 pub const offset: u32 = 0;
411 pub const mask: u32 = 0x01 << offset;
412 pub mod R {}
413 pub mod W {}
414 pub mod RW {
415 #[doc = "Context is invalid."]
416 pub const VLD_0: u32 = 0;
417 #[doc = "Context is valid."]
418 pub const VLD_1: u32 = 0x01;
419 }
420 }
421 #[doc = "AES Decryption Enable."]
422 pub mod ADE {
423 pub const offset: u32 = 1;
424 pub const mask: u32 = 0x01 << offset;
425 pub mod R {}
426 pub mod W {}
427 pub mod RW {
428 #[doc = "Bypass the fetched data."]
429 pub const ADE_0: u32 = 0;
430 #[doc = "Perform the CTR-AES128 mode decryption on the fetched data."]
431 pub const ADE_1: u32 = 0x01;
432 }
433 }
434 #[doc = "Read-Only"]
435 pub mod RO {
436 pub const offset: u32 = 2;
437 pub const mask: u32 = 0x01 << offset;
438 pub mod R {}
439 pub mod W {}
440 pub mod RW {
441 #[doc = "The context registers can be accessed normally (as defined by SR\\[RRAM\\])."]
442 pub const RO_0: u32 = 0;
443 #[doc = "The context registers are read-only and accesses may be further restricted based on SR\\[RRAM\\]."]
444 pub const RO_1: u32 = 0x01;
445 }
446 }
447 #[doc = "End Address"]
448 pub mod ENDADDR {
449 pub const offset: u32 = 10;
450 pub const mask: u32 = 0x003f_ffff << offset;
451 pub mod R {}
452 pub mod W {}
453 pub mod RW {}
454 }
455 }
456}