nrf52840_pac/spim0/iftiming/
csndur.rs

Help
1#[doc = "Register `CSNDUR` reader"]
2pub struct R(crate::R<CSNDUR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CSNDUR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CSNDUR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CSNDUR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CSNDUR` writer"]
17pub struct W(crate::W<CSNDUR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CSNDUR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CSNDUR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CSNDUR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CSNDUR` reader - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."]
38pub type CSNDUR_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `CSNDUR` writer - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."]
40pub type CSNDUR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSNDUR_SPEC, u8, u8, 8, O>;
41impl R {
42    #[doc = "Bits 0:7 - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."]
43    #[inline(always)]
44    pub fn csndur(&self) -> CSNDUR_R {
45        CSNDUR_R::new((self.bits & 0xff) as u8)
46    }
47}
48impl W {
49    #[doc = "Bits 0:7 - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."]
50    #[inline(always)]
51    pub fn csndur(&mut self) -> CSNDUR_W<0> {
52        CSNDUR_W::new(self)
53    }
54    #[doc = "Writes raw bits to the register."]
55    #[inline(always)]
56    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
57        self.0.bits(bits);
58        self
59    }
60}
61#[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csndur](index.html) module"]
62pub struct CSNDUR_SPEC;
63impl crate::RegisterSpec for CSNDUR_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [csndur::R](R) reader structure"]
67impl crate::Readable for CSNDUR_SPEC {
68    type Reader = R;
69}
70#[doc = "`write(|w| ..)` method takes [csndur::W](W) writer structure"]
71impl crate::Writable for CSNDUR_SPEC {
72    type Writer = W;
73}
74#[doc = "`reset()` method sets CSNDUR to value 0x02"]
75impl crate::Resettable for CSNDUR_SPEC {
76    #[inline(always)]
77    fn reset_value() -> Self::Ux {
78        0x02
79    }
80}
nrf52840_pac/spim0/iftiming/csndur.rs

nrf52840_pac/spim0/iftiming/
csndur.rs
