rp2040_pac/sio/
interp1_ctrl_lane0.rs

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1#[doc = "Register `INTERP1_CTRL_LANE0` reader"]
2pub type R = crate::R<INTERP1_CTRL_LANE0_SPEC>;
3#[doc = "Register `INTERP1_CTRL_LANE0` writer"]
4pub type W = crate::W<INTERP1_CTRL_LANE0_SPEC>;
5#[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"]
6pub type SHIFT_R = crate::FieldReader;
7#[doc = "Field `SHIFT` writer - Logical right-shift applied to accumulator before masking"]
8pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"]
10pub type MASK_LSB_R = crate::FieldReader;
11#[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"]
12pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive)  
14 Setting MSB &lt; LSB may cause chip to turn inside-out"]
15pub type MASK_MSB_R = crate::FieldReader;
16#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive)  
17 Setting MSB &lt; LSB may cause chip to turn inside-out"]
18pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
19#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
20 before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
21pub type SIGNED_R = crate::BitReader;
22#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
23 before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
24pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
26 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
27pub type CROSS_INPUT_R = crate::BitReader;
28#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
29 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
30pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
32pub type CROSS_RESULT_R = crate::BitReader;
33#[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
34pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
36pub type ADD_RAW_R = crate::BitReader;
37#[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
38pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
40 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
41 of pointers into flash or SRAM."]
42pub type FORCE_MSB_R = crate::FieldReader;
43#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
44 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
45 of pointers into flash or SRAM."]
46pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
47#[doc = "Field `CLAMP` reader - Only present on INTERP1 on each core. If CLAMP mode is enabled:  
48 - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of  
49 BASE0 and an upper bound of BASE1.  
50 - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"]
51pub type CLAMP_R = crate::BitReader;
52#[doc = "Field `CLAMP` writer - Only present on INTERP1 on each core. If CLAMP mode is enabled:  
53 - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of  
54 BASE0 and an upper bound of BASE1.  
55 - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"]
56pub type CLAMP_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."]
58pub type OVERF0_R = crate::BitReader;
59#[doc = "Field `OVERF1` reader - Indicates if any masked-off MSBs in ACCUM1 are set."]
60pub type OVERF1_R = crate::BitReader;
61#[doc = "Field `OVERF` reader - Set if either OVERF0 or OVERF1 is set."]
62pub type OVERF_R = crate::BitReader;
63impl R {
64    #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"]
65    #[inline(always)]
66    pub fn shift(&self) -> SHIFT_R {
67        SHIFT_R::new((self.bits & 0x1f) as u8)
68    }
69    #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
70    #[inline(always)]
71    pub fn mask_lsb(&self) -> MASK_LSB_R {
72        MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8)
73    }
74    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)  
75 Setting MSB &lt; LSB may cause chip to turn inside-out"]
76    #[inline(always)]
77    pub fn mask_msb(&self) -> MASK_MSB_R {
78        MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8)
79    }
80    #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
81 before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
82    #[inline(always)]
83    pub fn signed(&self) -> SIGNED_R {
84        SIGNED_R::new(((self.bits >> 15) & 1) != 0)
85    }
86    #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
87 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
88    #[inline(always)]
89    pub fn cross_input(&self) -> CROSS_INPUT_R {
90        CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0)
91    }
92    #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
93    #[inline(always)]
94    pub fn cross_result(&self) -> CROSS_RESULT_R {
95        CROSS_RESULT_R::new(((self.bits >> 17) & 1) != 0)
96    }
97    #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
98    #[inline(always)]
99    pub fn add_raw(&self) -> ADD_RAW_R {
100        ADD_RAW_R::new(((self.bits >> 18) & 1) != 0)
101    }
102    #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
103 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
104 of pointers into flash or SRAM."]
105    #[inline(always)]
106    pub fn force_msb(&self) -> FORCE_MSB_R {
107        FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8)
108    }
109    #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled:  
110 - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of  
111 BASE0 and an upper bound of BASE1.  
112 - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"]
113    #[inline(always)]
114    pub fn clamp(&self) -> CLAMP_R {
115        CLAMP_R::new(((self.bits >> 22) & 1) != 0)
116    }
117    #[doc = "Bit 23 - Indicates if any masked-off MSBs in ACCUM0 are set."]
118    #[inline(always)]
119    pub fn overf0(&self) -> OVERF0_R {
120        OVERF0_R::new(((self.bits >> 23) & 1) != 0)
121    }
122    #[doc = "Bit 24 - Indicates if any masked-off MSBs in ACCUM1 are set."]
123    #[inline(always)]
124    pub fn overf1(&self) -> OVERF1_R {
125        OVERF1_R::new(((self.bits >> 24) & 1) != 0)
126    }
127    #[doc = "Bit 25 - Set if either OVERF0 or OVERF1 is set."]
128    #[inline(always)]
129    pub fn overf(&self) -> OVERF_R {
130        OVERF_R::new(((self.bits >> 25) & 1) != 0)
131    }
132}
133impl W {
134    #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"]
135    #[inline(always)]
136    #[must_use]
137    pub fn shift(&mut self) -> SHIFT_W<INTERP1_CTRL_LANE0_SPEC> {
138        SHIFT_W::new(self, 0)
139    }
140    #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
141    #[inline(always)]
142    #[must_use]
143    pub fn mask_lsb(&mut self) -> MASK_LSB_W<INTERP1_CTRL_LANE0_SPEC> {
144        MASK_LSB_W::new(self, 5)
145    }
146    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)  
147 Setting MSB &lt; LSB may cause chip to turn inside-out"]
148    #[inline(always)]
149    #[must_use]
150    pub fn mask_msb(&mut self) -> MASK_MSB_W<INTERP1_CTRL_LANE0_SPEC> {
151        MASK_MSB_W::new(self, 10)
152    }
153    #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
154 before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
155    #[inline(always)]
156    #[must_use]
157    pub fn signed(&mut self) -> SIGNED_W<INTERP1_CTRL_LANE0_SPEC> {
158        SIGNED_W::new(self, 15)
159    }
160    #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
161 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
162    #[inline(always)]
163    #[must_use]
164    pub fn cross_input(&mut self) -> CROSS_INPUT_W<INTERP1_CTRL_LANE0_SPEC> {
165        CROSS_INPUT_W::new(self, 16)
166    }
167    #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
168    #[inline(always)]
169    #[must_use]
170    pub fn cross_result(&mut self) -> CROSS_RESULT_W<INTERP1_CTRL_LANE0_SPEC> {
171        CROSS_RESULT_W::new(self, 17)
172    }
173    #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
174    #[inline(always)]
175    #[must_use]
176    pub fn add_raw(&mut self) -> ADD_RAW_W<INTERP1_CTRL_LANE0_SPEC> {
177        ADD_RAW_W::new(self, 18)
178    }
179    #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
180 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
181 of pointers into flash or SRAM."]
182    #[inline(always)]
183    #[must_use]
184    pub fn force_msb(&mut self) -> FORCE_MSB_W<INTERP1_CTRL_LANE0_SPEC> {
185        FORCE_MSB_W::new(self, 19)
186    }
187    #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled:  
188 - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of  
189 BASE0 and an upper bound of BASE1.  
190 - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"]
191    #[inline(always)]
192    #[must_use]
193    pub fn clamp(&mut self) -> CLAMP_W<INTERP1_CTRL_LANE0_SPEC> {
194        CLAMP_W::new(self, 22)
195    }
196    #[doc = r" Writes raw bits to the register."]
197    #[doc = r""]
198    #[doc = r" # Safety"]
199    #[doc = r""]
200    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
201    #[inline(always)]
202    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
203        self.bits = bits;
204        self
205    }
206}
207#[doc = "Control register for lane 0  
208
209You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
210pub struct INTERP1_CTRL_LANE0_SPEC;
211impl crate::RegisterSpec for INTERP1_CTRL_LANE0_SPEC {
212    type Ux = u32;
213}
214#[doc = "`read()` method returns [`interp1_ctrl_lane0::R`](R) reader structure"]
215impl crate::Readable for INTERP1_CTRL_LANE0_SPEC {}
216#[doc = "`write(|w| ..)` method takes [`interp1_ctrl_lane0::W`](W) writer structure"]
217impl crate::Writable for INTERP1_CTRL_LANE0_SPEC {
218    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
219    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
220}
221#[doc = "`reset()` method sets INTERP1_CTRL_LANE0 to value 0"]
222impl crate::Resettable for INTERP1_CTRL_LANE0_SPEC {
223    const RESET_VALUE: u32 = 0;
224}
rp2040_pac/sio/interp1_ctrl_lane0.rs

rp2040_pac/sio/
interp1_ctrl_lane0.rs
